GB2115247A - An improved analog to digital converter system for application to pulse code audio modulation - Google Patents
An improved analog to digital converter system for application to pulse code audio modulation Download PDFInfo
- Publication number
- GB2115247A GB2115247A GB08229333A GB8229333A GB2115247A GB 2115247 A GB2115247 A GB 2115247A GB 08229333 A GB08229333 A GB 08229333A GB 8229333 A GB8229333 A GB 8229333A GB 2115247 A GB2115247 A GB 2115247A
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- GB
- United Kingdom
- Prior art keywords
- analog
- digital
- signal
- digital converter
- coupled
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/40—Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
An A/D converter system is described in which an analogue input is supplied on line 22B to an operational amplifier comparator 12D. Feedback is provided on line 22A from a low-noise high-speed D/A 22 controlled by a successive approximation register. <IMAGE>
Description
SPECIFICATION
An improved analog to digital converter system for application to pulse code audio modulation
This application is related to the copending application "Acircuitfor Improving the Performance of
Digital to Analog Converters" filed on even date herewith one ofthe inventors hereof.
The present invention relates to a method and apparatus for converting a wide band audio signal into a series of discrete coded pulses and more particularly a method and means for converting such a signal into coded pulses with low noise and distortion.
It has been demonstrated that instead of transmitting a continuous version of a signal containing intelligence, it is sufficient to sample the signal at regular discrete time intervals and to transmitthe samples ofthe modulating signal in the form of a periodic pulse train which can be subsequently demodulated aftertransmission via a chosen medium.
Various pulse modulation methods have been used for years on voice grade and telex circuits because of several advantages; which include relative noise immunity, ease of multiplexing by interlacing pulses from two or more signal sources and the ease with which pulses can be reshaped with regenerative repeaters on long transmission circuits. In fact, pulse modulators/demodulators (MODEMS) are supplied to the wire services.
Until recently, the requirement that the pulse repetition frequency be at least twice the highest frequency in the signal source has limited application of pulse modulators to voice grade communications, teletype and data circuits whose the upperfrequency limit is about 4 kilohertz. The availability of components which can change state in nanoseconds has resulted in high speed comparators and digital-toanalog converters (DACs) but noise and distortion have heretofore precluded the obtention of highfidelity digital reproduction of wide-band audio or music material.
This invention describes a system digitizing wideband audio signals by use of high-speed DAC means having low noise.
Accordingly it is an object of the present invention to provide a method and apparatus for periodically sampling an audio electrical signal art a predetermined rate and generating a multi-bit binary number which accurately describes the audio signal at the moment of sampling.
It is a further object ofthe invention to generate the desired sequence of binarywords by using a combination of an improved multibitdigital to analog converter, a control unit and a comparator unit which compares a constructed signal with the incoming signal and generates a multibitword when coincidence occurs.
According to one aspect of the present invention there is provided an analog-to-digital converter, comprising: digital counting meansforgenerating a stream of binary bits: digital-to-analog conversation means coupled to said digital counting means for converting said stream of binary bits into a first analog signal;firstmeansforreceiving an input analog signal; and second means coupled to said first means and to said digital-to-analog conversion means and having an output coupled to said digital counting meansforcomparing said input analog signal with said first analog signal to determine when they are substantially equal.
According to another aspect of the presentinven- tion, there is provided a system for digitally encoding a wide-band audio signal comprising in combination: meansfor sampling said signal at about a 50 kilohertz sampling-period to generate a multibit digital signal corresponding to the amplitude of said signal during said period; digital-to-analog conversion means with low noise capabilityforcreating a reconstructed analog signal of said multibitsignal; and comparator means coupled with said wide-band signal and said reconstructed analog signal for verifying the accuracyofsaid multibitdigital signal.
An embodimentofthe invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure lisa block schematic diagram of an analog to digital conversion system assembled and connected in accordance with this invention.
Figu re 2 il lustrates the netcircuitresultofthe components connected together in Figure 1 and shows parasitic ground resistances within the analog to digital conversion loop and within the audio input loop.
Figure 3 shows an enlarged view ofthe audio input at the point where the signal crosses the zero axis and changes polarity from negative to positive.
Figure 1 shows a blockdiagram oftheacomposite analog to digital converter (ACD) as shown as a single entity in Figure 2. Block 10 contains components which control operation of the composite ADC.
Op-ams 12A, B, C and Dare Norton current differencing amplifiers such as the LM3900 Amplifier.
Op-amp 1 2A is connected as a clock driver preferably operating at about 48 to 50 kilo-hertzto achieve an audio bandwithof about 20 kilohertz. Op-amps 1 2B and 12C perform a high speed switching function.
The output of clock driver 12A can have an equal mark space ratio, although if multiplexing is anticipated a mark pulse of.8 or less would be desirableto reduce cross-talk.
In one embodimentofthe invention item 14in block 10 is a successive approximation register to the
DM3504. An alternate circuit arrangement within control block 10 would incorporate a CMOS counter similartothe CD 4040.
Control block 10 has two inputs and two outputs.
Inputs 16 allows a start or initiate pulse to be entered into control block 10 so the successive approximation or counting function can be started. Input 1 6A is from comparator 12D. Output 18 from control block 10 is to indicate the end of a conversion sequence which may indicate the need for an additional start pulse to input 16. Output 20 consists of a stream of binary bits generated by control block 10 and parallel output 20A isthefinished product of the composite ADC.
Block 22 is an improved digital-to-analog converter (DAC) such as the DAC described in the referenced related copending patent application. Output 22A of
DAC 22 is coupled to the inverting input of comparator 12D is a constructed analog voltage which ultimately equals the audio voltage connected to 22B, the non-inverting input to comparator 12D.
In Figure 2 block 1 OA includes ail the components shown in Figure 1. The audio frequency input shown at22B is originating from generator 22C which is also connected to ground 24.
Output of block 1 OA which is a digitized bit stream based on the analog input 22B is shown at 20A. Block 1 OA includes the collection of components shown in
Figure 1,the most important of which is 22, the low-noise DAC. Switching currents in the DAC ground give rise to common mode voltages and are an unavoidable source of output noise causing differential non-linearity at the cross-over points as when the audio signal goes th rough zero. Resistor 24B shows howvoltages can be generated by ground currents within a DAC, such as 22 in Figure 1 ,which can contribute to noise and differential non-linearity during the mid-scale transition.Resistor 24A shows how voltages may be generated by currents in the control unit 10 and comparator 12D in Figure 1,which voltages are generally of small magnitude and make minimal contribution to noise and distortion in the system.
Figure 3 shows the mid-scaletransition sampling intervals of the audio signal 26 crossing the zero voltage axis 28. The effect of step variations caused by switching voltages in the DAC ground resistances is shown by the dotted step additions 26A. These switching voltages or differential non-linearities derived from ground currents are a major contribution to noise and cross-over distortion in DAC based ADC systems. Design features in an improved DAC descibed in the herein before referenced copending patent application greatly reduce the effects of ground currents which makes them ideally suited for usage in DAC based ADC systems.
Operation of the composite ADC is initiated by applying a signal to terminal 16 (see Figure 1). A successive approximation or counting process (IC14 in Figure 1) sends a series of pulses via 20 to DAC 22.
DAC 22 generates a constructed analog outputvia 22Ato comparator 1 2D. The comparator 1 2D compares the constructed analog signal with the incoming audio signal 22B. At some pointthe comparator will become satisfied with the equality of the contructed signal and the incoming signal. Operation of theADCfunctioning as a system continues as long as the audio input signal continues and an intervalled bit streamwill be available at20A(Figure 1). An interruption or a long pause in the incoming signal may make it necessary to restartthe ADC system operation.
While the invention has been described with respect to a preferred physical embodimentcon- structed in accordance therewith, it will be apparent to those skilled in the artthatvarious modifications and improvements may be madewithoutdeparting from the scope and spirit of the invention. For example, while the invention is contingent on the inclusion of low-noise DAC, a variety of commercially available integrated circuits may be usedforswitching, clocking, counting and comparison in lieu of the
IC's mentioned in the specification without materially altering the ADC system performance. A DAC with low noise must also be used in the decoding portion of the system (not shown) for high4idelity reproduction of the encoded wide-band signal.
Claims (12)
1. An analog-to-digitai converter, comprising: digital counting meansforgenerating a stream of binary bits: digital-to-anaiog conversion means coupled to said digital counting meansforconverting said stream of binary bits into a first analog signal; first means for receiving an input analog signal; and second means coupled to said first means and to said digital-to-analog conversion means and having an output coupled to said digital counting means for comparing said input analog signal with said first analog signal to determine when they are substantially equal.
2. An analog-to-digital converter according to claim 1 wherein said second means comprises a first operational amplifier having a first input coupled to the output ofsaid digital-to-ana log conversion means and a second input coupled to receive said input analog signal.
3. An analog-to-digital converter according to
Claim 2 wherein said digital counting means includes a clock driver.
4. An analog-to-digital converteraccordingto Claim 3 wherein said clock driver is an operational amplifier.
5. An analog-to-digital converter according to claim 2wherein said digital counting means includes a successive approximation register.
6. An analog-to-digital converter according to claim 2 herein said digital counting means includes a digital counter.
7. An analog-to-digital converter according to claim 2furthercomprising: third means for initiating the analog-to-digital conversion process; and forth means for indicating that the conversaion process has ended.
8. Asystemfordigitallyencodingawide-band audio signal comprising in combination: means for sampling said signal at about a 50 kilohertz samplingperiod to generate a multibit digital signal corresponding to the amplitude of said signal during said period; digital-to-analog conversion means with low noise capabilityforcreating a reconstucted analog signal of said multibitsignal; and comparator means coupled with said wide-band signal and said reconstructed analog signal for verifying the accuracy of said multibitdigital signal.
9. The system of claim 8,furtherincluding means for receiving and recording said multibitdigital signal.
10. The system of claim 9, further including meansfor receivi ng said recorded signal and lownoise digital-to-analog conversion means for providing a second reconstructed analog signal replicating said wide-band audio signal.
11. An analog-to-digital converter substantially as hereinbefore described with reference to the accompanying drawings.
12. A system for digitally encoding a wide-band audio signal substantially as herein before described with reference to the accompanying drawings.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB08229333A GB2115247B (en) | 1982-10-14 | 1982-10-14 | An improved analog to digital converter system for application to pulse code audio modulation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB08229333A GB2115247B (en) | 1982-10-14 | 1982-10-14 | An improved analog to digital converter system for application to pulse code audio modulation |
Publications (2)
Publication Number | Publication Date |
---|---|
GB2115247A true GB2115247A (en) | 1983-09-01 |
GB2115247B GB2115247B (en) | 1986-01-02 |
Family
ID=10533589
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB08229333A Expired GB2115247B (en) | 1982-10-14 | 1982-10-14 | An improved analog to digital converter system for application to pulse code audio modulation |
Country Status (1)
Country | Link |
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GB (1) | GB2115247B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5119097A (en) * | 1987-08-13 | 1992-06-02 | Nissan Motor Company, Limited | Analog-to-digital converter having decreased reference voltage to reduce display flicker |
US6917323B2 (en) | 2001-04-07 | 2005-07-12 | Roke Manor Research Limited | Analogue to digital converter |
-
1982
- 1982-10-14 GB GB08229333A patent/GB2115247B/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5119097A (en) * | 1987-08-13 | 1992-06-02 | Nissan Motor Company, Limited | Analog-to-digital converter having decreased reference voltage to reduce display flicker |
US6917323B2 (en) | 2001-04-07 | 2005-07-12 | Roke Manor Research Limited | Analogue to digital converter |
Also Published As
Publication number | Publication date |
---|---|
GB2115247B (en) | 1986-01-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19941014 |