GB2102237A

GB2102237A - Chrominance signal processing circuits

Info

Publication number: GB2102237A
Application number: GB08214731A
Authority: GB
Inventors: Nobuhiro Hori; Yutaka Nakagawa
Original assignee: Sony Corp
Current assignee: Sony Corp
Priority date: 1981-05-21
Filing date: 1982-05-20
Publication date: 1983-01-26
Also published as: DE3219273C2; NL192177B; ATA201782A; GB2102237B; DE3219273A1; AU555815B2; AT384518B; AU8382982A; NL8202085A; NL192177C; JPS57192190A

Abstract

A multi (e.g. PAL or NTSC) standards chrominance processing circuit contains a common front-end circuit portion 4, leading to circuit portions which are automatically sequentially switched (16, 17, 27, 35) from one standards operating mode to another until circuitry (45) (e.g. detecting the level of the colour burst signal, passed by a band pass filter 2, having its centre frequency switched from PAL to NTSC sub carrier and back) determines that the switched mode equates to the received television signal, whereupon a holding means 46 prevents further switching. <IMAGE>

Description

SPECIFICATION Chrominance signal processing circuits This invention relates to chrominance signal processing circuits capable of receiving and processing a plurality of composite video signals corresponding respectively to a plurality of different television standards.

Previously, when composite colour television signals of a plurality of different television standards are to be processed, different processing circuits or parts of processing circuits are required, and the appropriate circuits or parts of circuits are manually switched. If the user fails to perform the switching correctly, no picture is reproduced.

According to the present invention there is provided a chrominance signal processing circuit capable of receiving and processing a plurality of composite video signals corresponding respectively to a plurality of different television standards, the circuit comprising: a first circuit portion common to a plurality of composite video signals; and a second circuit portion switched by a switching means so that said plurality of composite video signals can be selectively processed; wherein the second circuit portion comprises: a switch control means for switching said switching means with a predetermined period, a detecting means for detecting the level of a colour burst signal contained in each of said plurality of composite video signals; and a holding means for holding said switching means in response to the output of said detecting means.

The invention will now be further described by way of illustrative and non-limiting example, with reference to the accompanying drawing, in which: Figure 1 is a block diagram showing an example of a chrominance signal processing circuit embodying this invention; and Figure 2 is a block diagram showing a modified part of the signal processing circuit of Figure 1.

A chrominance signal processing circuit embodying this invention will now be described with reference to Figure 1. The circuit is suitable for use in a colour television receiver, and is capable of processing the carrier chrominance signals of composite colour video signals, for a plurality of television standards, for example, for both the NTSC system and PAL system.

In Figure 1, there is shown an input terminal 1 to which a composite colour video signal of the NTSC or PAL system is supplied. The colour video signal supplied to the input terminal 1 is supplied to a band-pass filter 2, the centre frequency of the pass band being switched between 3. 58 MHz (for the NTSC system) and 4.43 MHz (for the PAL system) by a control signal supplied to a control signal input terminal 3. The carrier chrominance signal of the NTSC or PAL system, which is separated and extracted from the colour video signal by the band-pass filter 2, is supplied to a control circuit 4.

An example of the control circuit 4 will be described in detail. The carrier chrominance signal derived from the band-pass filter 2 is fed to an ACC (automatic chrominance control) amplifier 5, and the output signal of the amplifier 5 is then supplied to a burst gate circuit 7 wherein a burst signal is separated from the output signal. The phase of the burst signal is changed at every 1 H (H is the horizontal period) to +1350 in the PAL system. The burst gate circuit 7 is supplied with a burst gate signal through an input terminal 8. The burst gate signal extracted by the burst gate circuit 7 is fed to an ACC detecting circuit 9 and the detected output is supplied to one end of a capacitor, 6 the other end of which is earthed, and the detected output is also supplied to the ACC amplifier 5 to control its gain.The carrier chrominance signal from the ACC amplifier 5 is also supplied to a control amplifier 10 which is also supplied with a colour control signal through an input terminal 11, a picture control signal through an input terminal 12 and a killer voltage from a killer detecting circuit 45 which will be described later.

In Figure 1, change-over switches 16 and 1 7 are switched according to whether the composite colour video signal received is of the NTSC system or of the PAL system. When a colour video signal is received at the terminal 1 of the NTSC system, the carrier chrominance signal from the control amplifier 10 is supplied through the change-over switches 1 6 and 1 7 (when in the position shown in Figure 1) to blue and red colour difference signal demodulators 18 and 19, respectively. Blue and red colour difference signals are supplied from the demodulators 18 and 19 to output terminals 20 and 21 respectively.

When a colour video signal of the PAL system is received, the carrier chrominance signal from the control amplifier 10 is supplied to a 1 H delay line 13, an adder 14 and a subtracter 1 5, respectively. In this case, the output signal from the delay line 13 is supplied to both the adder 1 4 and the subtracter 1 5. A blue colour difference signal is derived from the adder 14, and is fed through the change-over switch 1 6 to the blue colour signal demodulator 18, while a red colour difference signal, which is derived from the subtracter 1 5 and whose phase is inverted at every 1 H, is applied through the change-over switch 1 7 to the red colour signal demodulator 1 9.

A sub-carrier signal generating circuit 22 will now be described. The circuit 22 includes a voltage controlled type crystal oscillator 23 which comprises a voltage controlled oscillator 24, and a change-over switch 27 for changing over crystal vibrators 25 and 26 according to whether the processing circuit is to be responsive to the NTSC system or the PAL system. The burst signal from the burst gate circuit 7 is supplied through a hue control phase shifting circuit 30 (when a colour video signal according to the NTSC system is being processed) and then to a phase comparator 28, which is also supplied with the oscillation signal from the voltage controlled oscillator 24, wherein the phase of the oscillation signal is compared with the phase of the output of the circuit 30.The phase-compared output signal from the phase comparator 28 is fed to a low-pass filter 29, the output of which is supplied to the oscillator 23 to control the oscillation frequency of the voltage controlled oscillator 24.

The sub-carrier signal (whose frequency is 3.58 MHz for the NTSC system or 4.43 MHz for the PAL system) generated by the sub-carrier signal generating circuit 22 is fed through 900 phase shifter 36 to the blue colour difference signal demodulator 18.

When the colour video signal of the NTSC system is received, the sub-carrier signal from the sub-carrier signal generating circuit 22 is fed through a change-over switch 32 (when in the position shown in Figure 1) to the red colour difference signal demodulator 1 9. However, when the colour video signal of the PAL system is received, the phase of the sub-carrier signal is changed to positive and the sub-carrier signal is inverted at every 1 H by means of the change-over switch 32 and an inverter 31. The sub-carrier signal is then fed to the red colour difference signal demodulator 19.

The change-over switch 32 is controlled by a flip-flop circuit 33 which is supplied with horizontal pulses of the PAL system supplied to an input terminal 34 through a change-over switch 35. The change-over switch 35 connects the flipflop circuit 33 to the input terminal 34 upon the reception of the colour video signal of the PAL system but disconnects the flip-flop circuit 33 and the input terminal 34 upon receiving the colour video signal of the NTSC system.

The above-mentioned killer detecting circuit 45 will be now described. A phase comparator 37 is provided which is supplied with the burst signal from the burst gate circuit 7 and the sub-carrier signal after having been transmitted through the change-over switch 32 and compares their phases. The phase compared output signal therefrom is applied to a low-pass filter 38 which comprises a resistor 39 and a capacitor 40.In this embodiment. a killer voltage derived from the lowpass filter 38 is selected to be such that when the received signal is either a monochromatic signal or a colour video signal of another television system (that is, to which the processing circuit is not responsive), the killer voltage is a high level signal, but when the received signal is a colour signal of a correct systen (that is, a television system to which the processing circuit is responsive), the killer voltage is a low level signal. The killer voltage is supplied to the control amplifier 10. so that the gain of the amplifier 10 may be controled by the killer voltage in addition to the carrier chrominance signal, the colour control signal and the picture control signal.

Thus, the output signal from the control amplifier 10 becomes a low DC voltage superimposed with an AC voltage when the video signal is a colour signal of the correct television system and becomes only a high DC voltage when the video signal is a monochromatic signal our a colour signal of another television system. The killer voltage is also applied to the flip-flop circuit 33. Thus, the changed-over state of the change-over switch 32 when the processing circuit is operative for the PAL system results in the colour video signal being synchronously controlled by the polarity of the burst signal of the PAL system.

In Figure 1, a change-over control circuit 41 changeably controls the centre frequency of the pass band of the band-pass filter 2 and the change-over switches 16, 17, 27 and 35 with a predetermined period. The change-over control circuit 41 is formed in such a way that a vertical synchronizing signal is supplied through an input terminal 42 to a clock input terminal CK of a 1 6scale counter 43. The output signal of the counter 43 is supplied to its clear terminal CL and also to a flip-flop circuit 44. As a result, the flip-flop circuit 44 produces a rectangular waveform signal having a period corresponding to 32 vertical periods and having a duty factor of 50%.By means of this rectangular waveform signal derived from the flipflop circuit 44, the centre frequency of the pass band of the band-pass filter 2 and the change-over switches 1 6, 1 7, 27 and 35 are changeably controllable according to the NTSC and PAL systems at every 1 6 vertical periods. The low-pass filter 38 in the killer detecting circuit 45 has a time constant which is smaller than the predetermined time period, so that the change-over switches 1 6, 17, 27 and 35 are changeably controllable at every 1 6 vertical periods.

In Figure 1, a hold control circuit 46 which discriminates between the television system of the carrier chrominance signal is based upon the killer detected output (voltage) from the killer detecting circuit 45. The hold control circuit holds the centre frequency of the pass band of the band-pass filter 2 and the changed-over states of the respective change-over switches 16, 17,27 and 35 to the state in compliance with the discriminated television system. The hold control circuit 46 will now be described in detail. A pnp-type transistor 47 is provided and has its collector grounded through a resistor 49, the base connected to the output terminal of the low-pass filter 38 and the emitter connected through a reverse current blocking diode 48 to a voltage source 55 of a predetermined voltage. The voltage source 55 is made adjustable so that when the received signal is a monochromatic signal or a colour signal of another television system, the transistor 47 is turned OFF, while when the colour video signal is a colour signal according to the correct television system, the transistor 47 is turned ON. For example, the voltage of the voltage source 55 may be selected so that when the received signal is a monochromatic signal or a colour signal of another television system, the base voltage of the transistor 47 is 8V, but when the received signal is a colour signal of the correct television system, the base voltage of the transistor 47 is about 6V, hence the voltage of the voltage source 55 is set at about 7.5V.The collector of the transistor 47 is connected through a resistor 56 to the base of a transistor 57 which has its emitter grounded and its collector connected to the input terminal 42.

An explanation will now be given of the operation of the circuit shown in Figure 1. When a colour television receiver (not shown) is switched ON, the centre frequency of the pass band of the band-pass filter 2 and the change-over switches 16, 17,27 and 35 are changed over at the predetermined period by the change-over control circuit 41. If the colour video signal received is, for example, in accordance with the NTSC system, upon the changed-over state of the NTSC system, the transistor 47 in the hold control circuit 46 turns ON. Thus, its collector voltage becomes high so that the transistor 57 turns ON. As a result, the vertical synchronizing signal supplied to the input terminal 42 is by-passed through the transistor 57 and hence is not supplied to the counter 43.

Therefore, the flip-flop circuit 44 maintains a stable state at that time. Therefore, the colour video signal of the NTSC system is processed by the control circuit 4. When the colour video signal of the PAL system is received, a similar operation is performed.

In the above described example, the supply of the vertical synchronizing signal to the counter 43 is controlled by the output voltage from the killer detecting circuit 45. Since, however, the DC level of the output voltage from the control amplifier 10 is in proportion to the output voltage from the killer detecting circuit 45, the supply of the vertical synchronizing signal to the counter 43 can be controlled by utilizing the output voltage from the control amplifier 1 0.

Furthermore, when the colour video signals of the NTSC system (pure NTSC system), the PAL system and a quasi-NTSC system (in which the colour sub-carrier frequency is 4.43 MHz, equal to that of the PAL system) are processed by the common chrominance signal processing circuit, the change-over control circuit 41 may be constructed as shown in Figure 2 and the control signal derived therefrom is used to control the change-over at the respective change-over switches in Figure 1.

In Figure 2, in place of the flip-flop circuit 44 in Figure 1, there is provided a ternary counter 50 having output terminals 51, 52 and 53. A "1" may be delivered in according with the PAL, pure NTSC and quasi-NTSC systems to any of the output terminals 51, 52 and 53. The outputs appearing at the output terminals 51, 52 and 53 are used to control the above-mentioned change-over switches, respectively.

In orderforthe chrominance signal processing circuit to be operative when receiving the quasi NTSC system, the sub-carrier frequency of the sub-carrier signal generating circuit 22 (Figure 1) is selected as 4.43 MHz, that is, equal to that of the PAL system. The change-over switches 1 6, 17, 27 and 35 are then respectively switched to be the same states as those for the pure NTSC system.

This invention can be applied to cases where, as employed in Central and South America, the carrier chrominance signals of the colour video signals of the PAL-N (in which the sub-carrier frequency is 3.58 MHz), PAL-M (in which the subcarrier frequency is 3.57 MHz) and NTSC (in which the sub-carrier frequency is 3.58 MHz) systems are processed by the common chrominance signal processing circuit.

Claims

1. A chrominance signal processing circuit capable of receiving and processing a plurality of composite video signals corresponding respectively to a plurality of different television standards, the circuit comprising: a first circuit portion common to a plurality of composite video signals; and a second circuit portion switched by a switching means so that said plurality of composite video signals can be selectively processed; wherein the second circuit portion comprises: a switch control means for switching said switching means with a predetermined period; a detecting means for detecting the level of a colour burst signal contained in each of said plurality of composite video signals; and a holding means for holding said switching means in response to the output of said detecting means.

2. A chrominance signal processing circuit according to claim 1 wherein said detecting means comprises a low-pass filter with a time constant smaller than said predetermined period.

3. A chrominance signal processing circuit according to claim 1 wherein said predetermined period is defined by a counter having a clock input terminal to which is supplied the vertical synchronizing signals contained in the currently received composite video signal.

4. A chrominance signal processing circuit according to claim 3 wherein said holding means comprises a switching circuit connected to said clock input terminal and is controlled by the output of said detecting means.

5. A chrominance signal processing circuit according to claim 1 wherein said detecting means comprises a phase detector in which the phase of said colour burst signal is compared with the phase of a reference sub-carrier signal, said phase detector generating an output, the level of which corresponds to the level of said burst signal.

6. A chrominance signal processing circuit according to claim 1 wherein said first circuit portion includes a control amplifier for amplifying a carrier chrominance signal contained in each of said plurality of composite video signals, said control amplifier being controlled by the output of said detecting means such that said control amplifier interrupts said carrier chrominance signal when the output of said detecting means is lowerthan a predetermined level, said control amplifier generating an output having a DC level depending on the level of said output of said detecting means, and said holding means being controlled by the output of said amplifier.

7. A chrominance signal processing circuit substantially as herein described with reference to Figure 1 of the accompanying drawing.

8. A chrominance signal processing circuit substantially as herein described with reference to Figure 1 as modified by Figure 2 of the accompanying drawing.