GB2100439A

GB2100439A - Data acquisition and display system

Info

Publication number: GB2100439A
Application number: GB8111391A
Authority: GB
Original assignee: Texas Instruments Ltd
Current assignee: Texas Instruments Ltd
Priority date: 1981-04-10
Filing date: 1981-04-10
Publication date: 1982-12-22
Also published as: GB2100439B

Abstract

A data acquisition and display system has a processor arranged to perform an initialisation program when the system is switched on, which program serves to establish parameters relating to the number and type of data sources and parameters determining the form of the display produced. After initialisation the processor executes data acquisition functions and produces a corresponding display at 21 of the acquired data in accordance with the parameters established during initialisation. The system may be arranged to monitor the functioning (i.e. d.c. short- circuit, open-circuit) of at least some of the sources and if a failure or some other emergency is detected to implement an emergency routine resulting in a modification of the parameters so that the system pays particular attention to the signals from one source and/or a specific display is produced drawing attention to the malfunction. The system may have an input circuit with a multiplexer 7, 16 and digital data storage. The display may be an array of electro-optical elements with a display RAM 4 having a data memory and a multiplex phase memory, which latter stores the display parameters. <IMAGE>

Description

SPECIFICATION Data acquisition and display system This invention relates to a data acquisition and display system which is particularly suitable for use in a motor vehicle but can be used in many other situations such as, for example, displaying the variables in a chemical plant or other kind of factory.

In producing any kind of electronic system it is clearly advantageous if the same design of system can be used in a wide variety of applications since the cost of mass production of a single item is much lower than the cost of a custom-built system. For inclusion in a motor vehicle an electronic system must be arranged to monitor different variables in different cars and possibly also produce different forms of display.

Hitherto it has been necessary to produce different systems for different vehicles at a proportionately higher cost than would be needed if the same system were to be used.

Microprocessors have been employed to process information relating to variables monitored around a motor vehicle, but it has been found that a fast powerful microprocessor is necessary for the display to have a satisfactory performance and appearance to represent the values of, say, between six and ten variables.

It is an object of the present invention to provide a data acquisition and display system in which the processing demands made on a microprocessor are reduced but the flexibility provided by a microprocessor-based system is retained.

According to the present invention there is provided a data acquisition and display system having an input circuit for signals from a plurality of sources indicating physical conditions at the sources, storage means for storing digital representations derived from the signals, processing means responsive to the stored representations to produce output signals suitable for generating a display of indications of the physical conditions, and an output circuit including a display means responsive to the output signals to produce the display of indications, wherein the processing means is arranged to perform an initialisation program when the system is switched on, which program serves to establish parameters within the input and output circuits adapting the system to a particular combination of types of sources and influencing the form of the display produced.

The system may be arranged so that the processing means does not change the values of the parameters once the initialisation program has been completed following switching on.

The initialisation program may be repeated occasionally during the operation of the system, for example if the parameters of the input and/or output circuits have been altered whilst the system is in operation due to the occurrence of an emergency as explained below, to restore the system and its display to normal when the emergency is past.

The input circuit may include multiplexing means enabling the signals from the plurality of sources to be handled sequentially and digital representations derived therefrom to be applied in turn to the storage means. The sources may produce analogue signals, digital signals or a sequence of pulses the repetition frequency or width of which indicates the particular condition.

The sources may, for example, consist of variable resistive means and the input circuit may be arranged to apply a current of known magnitude to the sources so that voltages of a suitable size and polarity are derived from the sources for application to an analogue to digital converter. If the signals obtained from the sources are sequences of pulses, the input circuit may include one or more counters which either count the pulses received from the source during a predetermined time interval or count pulses from a clock oscillator source during a pulse from the source or in the interval between successive pulses from a source. The initialisation program may be arranged to determine the number of sources which the multiplexing means can handle and there may be separate multiplexing means provided for analogue and digital sources.

The output circuit may include a display random access memory divided into two parts, a data memory and a multiplex phase memory. The initialisation program may insert into the multiplex phase memory a combination of signals which determine the way in which the data stored in the data memory is displayed. The display means may be a two-dimensional array of light emitting diodes or other electro-optical devices and the items of data in the data memory may be applied to cause the energisation of particular ones or groups of these devices depending on the signals recorded in the multiplex phase memory.

The initialisation program may allocate different areas of the display memory to the multiplex phase information, leaving the remainder of the display memory for data storage.

The system may be arranged to monitor the functioning of at least some of the sensors and in the event of failure or other emergency to modify the parameters of the input and/or output circuits so that, for example, the system pays particular attention to the signals for one of the sensors and/or a specific display is produced drawing attention to the malfunction. For example, if the engine oil pressure of a motor vehicle were to fall below a threshold value, the system could be arranged to monitor the temperature of the oil in addition to the pressure and produce a warning display. As part of the monitoring operation the running program, as distinct from the initialisation program 1 of the procesor could involve the periodic d.c. testing (i.e. short-circuit, opencircuit) of at least some of the sensors suited to such testing.

In order that the invention may be fully understood and readily carried into effect an example of it will now be described with reference to the accompanying drawings, of which: Figure 1 is a block diagram of a system according to the invention; Figure 2 is a diagram showing in more detail the display RAM and the display controller of Figure 1; Figure 3 shows the waveforms of three clock signals used in Figure 2; Figure 4 illustrates one possible relationship between the data in the display RAM and the form of the display produced; Figure 5 shows one application of the multiplex phase memory in controlling the form of display; Figure 6 shows an alternative way of using the multiplex phase memory; and Figure 7 shows one example of serially loaded display drivers which enables the number of connections to the display to be reduced to a relatively small number.

The example of the invention shown in Figure 1 has a microprocessor 1 connected to a bus system 2 including address, data and control buses. The program for the microprocessor 1 is stored in ROM 3 and the bus 2 is also connected to a random access memory 4 divided into three sections, a control RAM, a data acquisition RAM and a display RAM. The data acquired from a plurality of sensors is recorded in the data acquisition RAM and the processed data resulting from the acquired data appears in the display RAM. The control RAM is used to store the parameters for the data input circuits by means of which the signals obtained from the sensors are converted to a form suitable for recording in the data acquisition RAM. The control RAM also stores parameters for defining the format of the display to be produced from the data stored in the display RAM.Further details of these processes will be given later.

The input circuits of the system are designated generally by the reference 5 and include input circuits for analogue sensors and input circuits for digital sensors. The sensors themselves are not shown because their form is immaterial to the present invention. Many suitable forms of sensor have already been described.

The analogue sensors are connected through input protection circuits 6 to an analogue multiplexer 7 controlled by output signals from a multiplex selection counter 8 driven by a clock not shown. The output of the counter 8 is compared with the output of a current sink selection register 9 in a parallel comparator 10. When the address in the register 9 is the same as the total registered in the counter 8 the comparator 10 produces an output signal which opens a switch 11 causing current to flow from a current source 12 to the particular one of the analogue sensors selected by the multiplexer 7. The current flow through the sensor appears as a voltage on conductor 13 which is applied to an analogue to digital and digital to analogue converter 14 from which the resulting digital output is applied to the data acquisition RAM.An analogue output from the converter 14 to the current source 12 is used to adjust the value of the current produced by the source 12 so that the voltage on the conductor 1 3 is within the range suited to the analogue to digital converter.

The converter 14 may consist of an analogue to digital converter which includes a digital to analogue converter the output of which is compared with an analogue input, and in the event of a difference causes a digital counter to be incremented or decremented accordingly, the digital counter providing the digital input is the digital to analogue converter. The analogue to digital conversion function of the converter 14 is used as described above and the digital to analogue conversion function is responsive to a digital input from the control RAM to produce a corresponding output voltage which is stored on a capacitor and applied to determine the current output of the source 12.

It is envisaged that not all of the analogue sensors will require current from the source 12, but some could produce a d.c. voltage output. For such sensors the switch 11 is open circuit because the register 9 does not store the multiplex counts for the sensors. The multiplex numbers of those sensors requiring current are entered cyclically into the register 9 from the control RAM in advance of the counting of the counter 8 so that the number of the next sensor requiring current is in the register 9 when the counter 8 reaches it.

The digital sensors are connected through input protection circuits 1 5 and a digital multiplexer 1 6 to counters 1 7 used to store digital values representing the repetition frequency or width of the incoming pulses. The counter 17 may also be arranged to store digital values derived directly from the sensors without counting.

Associated with counters 1 7 but not shown is a clock pulse generator used either to measure the frequency of the incoming pulses by being applied to the counter for the interval of time between successive incoming pulses or the width of the incoming pulses by being applied to the counter during the duration of the pulses. A multiplex selection register and counter 1 8 is used to control the multiplexer 1 6. As indicated by the broken lines, both the current sink selection register 9 and the multiplex selection register in unit 1 8 form part of the control RAM.

The microprocessor 1 performs the processing necessary to convert the digital information stored in the data acquisition RAM into a form suitable for display and the data so processed is stored in the display RAM. The display RAM is connected to a display control 1 9 which is also connected to the microprocessor bus 2 and is used as described later to convert the data stored in the display RAM into signals suitable for application to display drivers 20. The drivers 20 are connected to the display 21.

The system shown in Figure 1 has two modes of operation; in the first mode which is operative immediately on applying power to the system the microprocessor 1 performs a series of operations under control of a program stored in the ROM 3 to cause initialisation of the system. In the second mode the microprocessor 1 performs the operations necessary to convert the acquired data stored in the data acquisition RAM into a form suitable for generating the display when it is then stored in the display RAM. During initialisation data is stored in the control RAM which defines the operations to be performed by the input circuits 5 and the output circuit formed by the display controller 19, display drivers 20 and display 21. It is this data which varies with the different applications of the system.Amongst the data stored in the control RAM during initialisation are the following, although other parameters will be referred to later in the context of their applications and it will be apparent that these also are stored in the control RAM as a result of the initialisation program: Sample time register which records the length of time for which each analogue sensor is connected through the analogue multiplexer to the converter 14, the contents of this register determines the clocking rate of the multiplexer 7; Time base period register which records the time base period and therefore the clocking rate for the digital multiplexer 18; Current sink selection register which records to which of the analogue sensors the current source 12 is to be connected.

As mentioned above, certain of the analogue sensors may produce an output voltage without having a current applied to them from the source 1 2 and therefore it is not always necessary for the switch 11 to be closed to pass current to the source 12 when a sensor is connected to the conductor 1 3. In order to set the current supplied by the source 12 to a suitable value for the sensor concerned, the digital to analogue converter in the unit 14 responds to a value from the control RAM to cause corresponding voltage to be generated which is stored on a capacitor, not shown, and applied to control the current supplied by the source 12, which may be a conventional controlled current source.When the counter 8 selects the same one of the analogue sensors as is identified by the register 9, the switch 11 is closed so that current is fed by the source 12 through the particular sensor and the resulting voltage is applied to the analogue to digital converter 14. For diagnostic purposes if the voltage appearing on the conductor 13 is either zero or very large the analogue to digital converter 12 may be arranged to indicate that the corresponding sensor is either short-circuited or open-circuited. This signal may be used to interrupt the normal program of the microprocessor 1 and initiate an emergency routine and display. Where the design of the digital sensors is suitable their d.c. conductivity could also be tested by a connection from the analogue multiplexer used for test purposes only.

In addition to the multiplex selection register the control RAM contains a digital multiplex control register which stores the maximum number of digital sensors which the multiplexer 1 6 is required to address. This control register is used to cause the register and counter 18 to step through outputs corresponding to all of the digital sensors which the system is intended to scan. The counters 1 7 which receive the digital inputs from the multiplexer 1 6 consist of two 1 6-bit counters to one of which the output of the multiplexer 1 6 is permanently connected. In addition to these counters there are two auxiliary control registers which store overflow from the counters when the total exceeds the capacity of the counters.By means not shown, the two 1 6-bit counters can be reconfigured by the control RAM as a 24-bit counter and 8-bit counter so as to permit extra long counts when more resolution is required and a reduction in the period necessary to scan a particular sensor where lower resolution is all that is required. The counters 1 7 also contain gates for switching over the inputs from the multiplexer 1 6 and the clock pulse inputs to enable the counters to measure the width of pulse width modulated inputs.

All of the data acquired from the sensors after either being converted to digital form or counted, is transferred to the data acquisition RAM where it is accessible to the microprocessor 1 for the calculations necessary to convert the data to a form suitable for producing the display. It will be apparent that after the initialisation program has been completed and the various parameters of the multiplexes in the input circuits have been established, the input circuits 5 can be left to run at their own speed independently of further control from the microprocessor 1; the only conflict likely is when the microprocessor 1 wishes to address the data acquisition RAM whilst either the converter 14 or the counter 1 7 are preparing to transfer data to the data acquisition RAM; under these circumstances the microprocessor 1 is given priority and the input circuit is caused to delay its data transfer.

The display controller 1 9 is shown in detail in Figure 2 in which the display RAM of Figure 1 is represented by the block 30 which is divided into two parts, a multiplex phase matrix and a data matrix. Associated with the block 30 are X and Y decoder drivers 31 and 32 having respectively column and row conductors for the matrix of storage elements in the block 30. The left-hand column of the block 30 is duplicated and forms the data latch column which will be referred to later. The multiplex phase information and the data stored in the two parts of the block 30 are used as described later with reference to Figures 4 to 7 to drive the display itself. The addressing of the display RAM 30 is effected by X and Y addresses generated in a display refresh counter 33 driven by phase 01 of a clock not shown. The three phases of that clock are shown in Figure 3.

The counter 33 scans all combinations of values of X and Y within preset ranges to cause the generation of the display. A maximum value of Y is stored in a register MAX Y 34 in response to the initialisation program so as to limit the number of rows of the display RAM to only those required to generate the particular display which the system is to produce. The value of Y in the counter 33 is compared with the value stored in the register 34 by a display refresh counter comparator 35 which produces an output when the two Y addresses are equal, which output resets the counter 33 and also applies a signal to the clock input of a trigger circuit 36. The function of the trigger circuit 36 is to permit specific X and Y addresses to be entered by the microprocessor 1 when entering data in the display RAM.When this occurs microprocessor 1 produces a signal DMAREQ which is applied to the D input of the trigger circuit 36 and by means of its Q output enables X and Y addresses from a RAM X register 37 and a RAM Y register 38 to be fed via the X and Y buses to the decoder drivers 31 and 32.

The microprocessor 1 also provides an indication of how much of the display RAM should be allocated to the multiplex phase matrix and how much to the data matrix. The column number containing the rightmost column of the multiplex phase matrix is referred to as X REF which parameter is set up during the initialisation of the system and is stored in a register 39. A display index register comparator 40 compares the values stored in the register 39 with the values stored in the RAM X Register 37 and when these are equal enabies the entry of multiplex phase data from a multiplex phase register 41 during the initialisation phase. Whilst the microprocessor 1 has control of the addressing of the display RAM 30, the display refresh counter 33 is stopped by the application of an inhibition signal DMA ACK to a gate 42.

The output signals derived from the display RAM consist of a display latch signal, a display data signal and a display clock signal which are employed as described later with reference to Figure 7 to generate the required display. Each row of the display RAM (a single Y address) represents one or one combination of activated points on the display. The display itself is a large panel electronic display and may consist of a matrix of light emitting diodes, a vacuum fluorescent display, a liquid crystal matrix display, an array of electroluminescent elements or a plasma discharge display, for example. As described herein, the display takes the form of a rectangular array of points, but it could be arranged in any suitable form to produce a display required which may consist of 7-segment figures, bar graphs, simulated needle rotating about points, or specific messages.In Figure 4 there is shown an example of how the data and multiplex phase information stored in a single row of the display RAM could be used to generate two adjacent light spots on a rectangular array of elements. The contents of the particular row shown at 50 is used to operate the switches of a driver circuit 51, shown purely diagrammatically as mechanical switches and the output connections of the driver circuit 51 are connected to row and column conductors of a display 52.

Note that the first five digits of the particular row are allocated to the multiplex phase field and are used to apply voltages selectively to the row conductors of the display, whereas the remaining digits cause the selective application of voltages to the column conductors of the display.

The multiplex phase information is used to determine the time of excitation of the corresponding row conductors of the display and the arrangement of the connections between the particular row of the display RAM selected for producing the display at the time and the driver circuit are such that the digit of the multiplex phase field is used to select the time of operation of the first five switches of the driver circuit 51 so that no two of those switches are operated simultaneously. Depending on the particular form of the display so the proportion of the display RAM allocated to the multiplex phase matrix is adjusted during the initialisation in accordance with the value of X REF as mentioned above. In Figure 5 there are four phases to the multiplex and four rows to the display.In Figure 6 there are 20 phases to the multiplex and 20 columns to the display; in this instance the rows and columns of the display are exchanged. In a particular example of the display RAM, it consists of 20 registers of 32 bits. In Figure 6 each register is allocated to a different multiplex phase, whereas in Figure 5 several registers are allocated to each multiplex phase.

It will be apparent from a consideration of Figure 2 that the refreshing of the display which is carried out by the refresh counter 33 is independent of the operation of the microprocessor 1 once the value of MAX Y stored in the register 34 has been set up during initialisation. Although it is not shown the values stored in the X REF Register 39 can be used to operate a series of switches to distinguish the multiplex phase outputs from the data outputs of the display RAM.

Since for many applications the main part of the circuitry of the system will be separate from the display, it is desirable to keep to a minimum the number of conductors which connect the diplay controller to the display drivers, and this is achieved as shown in Figure 7 by the use of a serial data feed to the display drivers. In Figure 7 the digits stored in the display RAM 30 (Figure 2) are read out by row serially and applied to a serial data input terminal 60 in synchronism with an input display data clock applied to a terminal 61, this clock being phase 53 of the main display clock shown in Figures 2 and 3. The clock signals applied to terminal 61 are used as stepping pulses to step the data input on the terminal 60 into a row of trigger stages A which act as a shifting register.

When an entire row or rows of digits from the display RAM 30 is stored in the triggers A of Figure 7 a display latch signal is generated in response to the addressing of the data latch column of the display RAM and causes the parallel transfer of the digits stored in the triggers A into a second row of triggers B, the display latch signal being applied to a terminal 62 in Figure 7.

The triggers B have both Q and Q outputs which are used to operate respective switches connected in series between a display ground conductor 63 and a display supply conductor 64.

Again, the switches are shown as mechanical switches but could in fact be constituted by MOS or bipolar transistors. The junction of each pair of switches associated with a trigger B is connected to a corresponding output terminal for the display itself. It would be apparent by the use of serial data transfer in this way the number of information carrying conductors is reduced to three for virtually any size of display.

Claims (filed on 6 April 1982) 1. A data acquisition and display system having an input circuit for signals from a plurality of sources indicating physical conditions at the sources, storage means for storing digital representations derived from the signals, processing means responsive to the stored representations to produce output signals suitable for generating a display of indications of the physical conditions, and an output circuit including a display means responsive to the output signals to produce the display of indications, wherein the processing means is arranged to perform an initialisation program when the system is switched on, which program serves to establish parameters within the input and output circuits adapting the system to a particular combination of types of sources and influencing the form of the display produced.

2. A system according to claim 1 wherein the processing means is also arranged to perform the initialisation program during the operation of the system in response to the occurrence of emergency conditions requiring a modification of one or more parameters or in the form of display produced, and when the emergency conditions no longer exist to restore the parameters and the form of display to normal.

3. A system according to claim 1 or 2 wherein the input circuit includes multiplexing means enabling signals from a plurality of sources to be handled sequentially and digital representations derived therefrom to be applied in turn to the storage means.

4. A system according to claim 3 wherein the input circuit includes one or more input channels for analogue signals from the sources and an analogue signal multiplexing means connecting the analogue signals in turn to an analogue to digital converter.

5. A system according to claim 4 wherein means is provided for causing current to flow through at least one selected source to cause it to produce an analogue signal output, the magnitude of the current being arranged so that the analogue signal output lies within the input signal range of the analogue to digital converter.

6. A system according to claim 4 or 5 wherein if the analogue signal from a source is either zero or very large an indication may be produced that the corresponding source is short-circuited or open-circuited.

7. A system according to any of claims 3 to 6 wherein at least some of the sources produce digitally coded signals.

8. A system according to any of claims 3 to 7 wherein at least some of the sources produce pulse sequences and the input circuit includes one or more counters either for counting the pulses in a sequence within a predetermined time interval or for counting clock pulses during a pulse of the sequence or between successive pulses of a sequence, whereby the number recorded in the counter forms a digital representation of the signal from the source.

9. A system according to claim 4, 5 or 6 including separately multiplexing means for analogue and digital signals from the sources.

10. A system according to any preceding claim wherein the output circuit includes a display random access memory divided into a data memory and a multiplex phase memory, wherein the multiplex phase memory is arranged to store data which determine the way in which the data in the data memory are displayed.

11. A system according to claim 10 wherein the initialisation program determines what part of the display random access memory is data memory and what part is multiplex phase memory.

1 2. A system according to any preceding claim wherein the running program includes the periodic testing of the sensors forming the sources of input signals.

1 3. A data acquisition and display system substantially as described herein with reference to the accompanying drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. parallel transfer of the digits stored in the triggers A into a second row of triggers B, the display latch signal being applied to a terminal 62 in Figure 7. The triggers B have both Q and Q outputs which are used to operate respective switches connected in series between a display ground conductor 63 and a display supply conductor 64. Again, the switches are shown as mechanical switches but could in fact be constituted by MOS or bipolar transistors. The junction of each pair of switches associated with a trigger B is connected to a corresponding output terminal for the display itself. It would be apparent by the use of serial data transfer in this way the number of information carrying conductors is reduced to three for virtually any size of display. Claims (filed on 6 April 1982)

1. A data acquisition and display system having an input circuit for signals from a plurality of sources indicating physical conditions at the sources, storage means for storing digital representations derived from the signals, processing means responsive to the stored representations to produce output signals suitable for generating a display of indications of the physical conditions, and an output circuit including a display means responsive to the output signals to produce the display of indications, wherein the processing means is arranged to perform an initialisation program when the system is switched on, which program serves to establish parameters within the input and output circuits adapting the system to a particular combination of types of sources and influencing the form of the display produced.