GB2099651A - Electronic circuit device - Google Patents

Abstract

An electronic circuit device (PC) which can be used as a driver in an EPROM has an invertor (D2, E2) to invert an input signal (IN) and a delay circuit (CR1) to correct for the phase shift produced by the invertor, whereby substantially truly antiphase drive signals are applied to the gates of push-pull output transistors (E3, E4), thereby substantially reducing the transient through switching current (ID1). A bootstrap driver circuit (BC) uses an invertor (E7, D4) and delay circuit (CR2) to boost the potential of node H above that of the supply (VCC) when input signal E goes from LOW to HIGH, thereby turning output device E10 fully ON. <IMAGE>

Description

SPECIFICATION Electronic circuit device The present invention relates to an electronic circuit device including a push-pull output stage, and more particularly to an electronic circuit device which is effective when applied to an EPROM (electrically programable read only memory).

In recent years, electronic circuit devices which are manufactured in the form of semiconductor integrated circuits have needed to be increasingly high in performances and high in integration densities.

In an electronic circuit device such as EPROM, various push-pull output stages are arranged for the purposes of driving a desired load in order to provide a signal at a comparatively high speed, thereby keeping the low power dissipation to a minimum.

The push-pull output stage requires an inverted signal and a non-inverted signal in order to drive the two transistors included therein in push-pull operation. The inverted signal and the noninverted signal can be delivered from an appropriate driver circuit which includes an inverter. The driver circuit, however, involves an operation delay. As a result, the timings of changes of the inverted and non-inverted signals are changed undesirably. The two transistors constituting the push-pull output stage are simultaneously brought into the "on" state in such a way that the inverted are non-inverted signals have the same level at the same time, e.g.

the high level. Therefore, a through current of comparatively great level develops. The through current of the push-pull output stage causes an undesirable potential fluctuation in the power supply line of the circuit.

Accordingly, the magnitudes of the inverted signal and the non-inverted signal must be reduced in order to prevent undesirable fluctuations in the power supply.

A circuit including a bootstrap capacitor can be coupled with the push-pull output stage in order to properly increase the level of a signal which is delivered therefrom. In this case, a signal of appropriate timing is needed for charging the bootstrap capacitor.

It is an object of the present invention to overcome the above mentioned disadvantages.

According to a first aspect of the present invention there is provided an electronic circuit device including: (a) a first node which is supplied with an input signal; (b) an inverter circuit which delivers an output signal inverted with respect to said input signal supplied to said first node; (c) delay means to deliver a delay signal delayed with respect to said input signal supplied to said first node; (d) an output node; (e) a first MISFET which has a drain-source path connected between a first terminal of a power source and said output node, and a gate electrode to be supplied with said output signal of said inverter circuit; and (f) a second MISFET which has a drain-source path connected between said output node and a second terminal of said power source, and a gate electrode to be supplied with said delay signal.

According to a second aspect of the present invention there is provided an electronic circuit device including: (a) a first circuit which has a signal inverter circuit, a first output node to deliver a first signal, and a second output node to deliver a second signal of a level inverted with respect to said first signal; (b) a bootstrap circuit which includes first and second MISFETs with their drain electrodes and source electrodes connected in series between first and second power source terminals, and a bootstrap capacitor coupled between a gate electrode and said source electrode of said first MISFET; (c) coupling means to supply said first signal to said gate electrode of said first MISFET; and (d) delay means to supply said second signal to a gate electrode of said second MISFET with a predetermined delay time.

The present invention will now be described in greater detail by way of example with reference to the accompanying drawings, wherein: Figure 1 is a block diagram of an EPROM to which the electronic circuit device is applied; Figures 2 and 3 are circuit diagrams of the block X-DCR shown in Figure 1; Figure 4 is a circuit diagram of a preferred form of electronic circuit device; Figure 5 is a waveform diagram to explain the operation of the circuit shown in Figure 4; Figure 6 is also a waveform diagram to explain the operation of the circuit shown in Figure 4; Figure 7 is a layout diagram of the circuit elements which constitute a push-pull circuit; Figure 8 is a sectional view taken along the line A-A' of Figure 7; Figure 9 is a layout diagram of circuit elements which constitute a bootstrap circuit;; Figure 10 is a circuit diagram of a delay circuit; Figures 11, 12 and 13 are sectional views each showing different embodiments of delay means; and Figure 14 is a circuit diagram of another embodiment of a delay means.

Referring first to Figure 1, the whole EPROM, that is, the various circuit blocks within an area enclosed with a two-dot chain line are constructed as a single integrated circuit device by the known MIS (metal-insulatorsemiconductor) ingegrated circuit technology.

The EPROM is provided with external terminals A1 to Anl Vcc, GND, I/O, Vpp, PRG, OE and CE. The external terminals A, to An are supplied with address signals, and the external terminal Vcc is supplied with a voltage source of, e.g. +5 volts.

The external terminal I/O is supplied with a data signal from a write-down device, not shown, in a data write-down operation or a programing operation, and it delivers a data in a data read-out operation. The external terminal Vpp is supplied with a high write-down voltage of, e.g., +25 volts in the data write-down operation. The external terminal Vpp is made a comparatively low potential of, e.g., O or 5 volts in the read-out operation. The external terminals PRG, OE and CE are resepectively supplied with a program control signal, an output enable signal and a chip enable signal.

ADB1 designates a first address buffer circuit which delivers internal address signals a1 and a, to a8 of a non-inverted level and an inverted level corresponding to the address signals fed to the external terminals A1-A8.

X-DCR designates an X-decoder circuit whose operation is controlled by control signals ce and ce respectively fed from control circuits CONT2 and CONT3 and which forms word line select signals for selecting word lines W1 to W258 of a memory array MARY. The X-DCR is brought into the operating status in such a way that the control signals ce and ce are resepectively made the low level and the high level. The X-DCR in the operating status delivers a signal of the high level or selective level to one word line corresponding to the statuses of the internal address signals a1 and a1 to a8. When the control signals ce and ce are at the high level and the low level respectively, the X-DCR is in the non-operating status.At this time, all the word lines W1 to W258 are made the low level or non-selective level irrespective of the combination of the internal addresss signals a1 and a1-a8.

The memory array MARY is constructed of a plurality of semiconductor nonvolatile memory elements F1-F256, arranged in the shape of a matrix, the word lines W1-W256, and bit lines B1Bn.

Although not especially restricted, each of the memory elements F1-F2561 is made of a FAMOS (Floating Gate Avalanche injection MOS) transistor which has a floating gate and a control gate.

In the MARY, the drain electrodes of the memory elements arranged in an identical row are connected in common to the bit line corresponding to the particular row, while the control gate electrodes of the memory elements arranged in an identical column are connected in common to the word line corresponding to the particular column.

Although not especially restricted, the embodiment is provided with switching MISFETs S1 to S288 in one-to-one correspondence with the respective memory element columns of the memory array MARY as shown in Figure 1, in order to prevent leakage currents from flowing to the non-selected memory cells during the writedown operation. The switching MISFET corresponding to one column has its drain electrode coupled to the common source electrode of the memory elements corresponding to the particular column, and has its gate electrode coupled to the word line corresponding to the particular column. The source electrodes of the switching MISFETs S1 to S253 are coupled to earth.

ADB2 indicates a second address buffer circuit, which forms internal address signals a9 to an of the non-inverted level and the inverted level by receiving the address signals through the external terminals AgAnw Among the internal address signals as to an delivered from the second address buffer circuit ADB2,those a1 to an are fed to a first control circuit CONY" and the remaining ones are fed to a Y-decoder circuit Y-DCR.

The Y-decoder circuit Y-DCR decodes the internal address signals fed from the second address buffer circuit ADB2, and thereby forms select signals CS1-CS8 to be fed to a column switch circuit CSW.

The column switch circuit CSW has its operation controlled by the select signals CS1 to CS8.

Although not especially restricted, the memory array MARY shown in Figure 1 is provided with the bit lines B1 to Bn in a number of 32. Four common bit lines CB1 to CB4 are arranged for the 32 bit lines. Accordingly, eight bit lines correspond to one common bit line.

Thus, when one select signal has been delivered from the Y-decoder circuit Y-DCR1,four bit lines corresponding to the select signal are coupled with the respectively corresponding common bit lines through the column switch circuit CSW.

In the case where a plurality of common bit lines are arranged as described above, the capacitances of stray capacitors, parasitic capacitors etc. to couple with or exist on each common bit line can be made less than in the case where only one bit line is arranged for the 32 bit lines B1Bn According to the arrangement of the embodiment, the capacitances which limit a signal variation speed can be reduced, so that a signal of high speed is allowed to be applied to the common bit line.

The common bit lines CB1-CB4 are respectively coupled to corresponding read out/write down circuits R/W1-R/W4. The readout/write-down circuits R/W1 to R/W4 have their respective operations controlled by signals which are delivered from the first control circuit CONT and the second control circuit CONT2.

The first control circuit CONT1 operates, in effect, as a decoder which decodes the internal address signals an~1an fed from the ADO2. The output signals of the CONT1 are supplied to the read-out/write-down circuits R/W1-R/W4 as operation control signals.

The four read-out/write-down R/W1-R/W4 have only one of them brought into the operating status by the output control signals from the first control circuit CONT,. The operation mode of the read-out/write-down circuit to be brought into the operating status is controlled by the control signal fed from the second control circuit CONT2.

The read-out/write-down circuit held in the operating status is brought into a write-down operation mode in response to the high level of the control signal we. In the write-down mode, a write-down signal corresponding to the data signal which is supplied through an input/output buffer circuit IOC from the external terminal I/O is fed to the corresponding common bit line from the read-out/write-down circuit held in the operating status. The remaining common bit lines are made a potential, e.g. earth potential in accordance with the non-operating status of the respectively corresponding read-out/write-down circuits.

The read-out/write-down circuit held in the operating status is brought into a read-out operation mode in response to the low level of the control signal we.

In the read-out operation mode, the signal of the common bit line corresponding to the readout/write-down circuit held in the operating status is supplied to the input/output buffer circuit IOC through the particular read-out/write-down circuit. Signals on the remaining common bit lines are neglected because the respectively corresponding read-out/write-down circuits are not in the operating status.

In the case where data of 1 byte (8 bits) needs to be written down and read out by the address signals A1 to A, the number of bit lines of the memory array MARY is set at 32x8 or 256. In this case, circuits CSW, R/W and IOC similar to those in Figure 1 are arranged for each group of 32 bit lines.

The second control circuit CONT2 forms internal control signals ce, we, cs etc. in response to the chip enable signal, output enable signal, program signal and high write-down voltage which are respectively fed to the external terminals CE, OE, PRG and Vpp. The third control circuit CONT3 forms the internal control signal ce which is opposite in phase to the internal control signal ce.

Figure 2 shows an example of a practicable circuit of the X-DCR in the EPROM of Figure 1.

Although not especially restricted, the X-DCR has three divided circuit parts, namely, address decode portions DOUR1, DC R2 and DOUR3.

The address decode portion DCR1 has its operation controlled by the control signal ce and ce, and provides the non-inverted signal and the inverted signal by decoding the internal address signals of the lower 3 bits a1 to a3. The address decode portion DCR3 has it operation controlled by the output signals of the address decode portion DCR1, and decodes the internal address signals of the medium 3 bits. The address decode portion DCR2 provides the word line select signals by receiving the internal address signals of the upper 2 bits and the output signal of the address decode portion DOUR3.

Although Figure 2 illustrates only one unit circuit constituting the address decode portion DCR,, this address decode portion DCR, is constructed of a plurality of unit circuits having the AND and NAND functions. Each unit circuit of the DCR, is supplied with the internal address signals of the lower 3 bits and the control signals ce. The DCR1 includes eight unit circuits so as to decode eight statuses indicated by the address signals of the 3 bits. The practicable arrangement and operation of the unit circuit constituting the address decode portion DCR1 will be described in detail later with reference to Figure 3.

Although not especially restricted, the address decode portion DCR3 is constructed of a plurality of unit circuits having the OR-NAND function.

Figure 2 illustrates only one unit circuit Ond constituting the address decode portion DOUR3.

As shown in the figure, the unit circuit Ond is constructed of a depletion-mode load MISFET Q2, enhancement-mode driving MISFETs Q3-Q6 the respective gates of which are supplied with the output signal dcrl of the DOR1 and the internal address signals of the 3 bits a6Wa6, and an enhancement-mode power switch MISFET Q1 which is located between the load MISFET Q2 and the power source terminal Vcc and whose gate is supplied with the output signal dcrl of the DOUR1.

Although no restriction is especially intended, one unit circuit Ond corresponds to four word lines in this example. Accordingly, 64 unit circuits Ond are arranged for the 256 word lines W1- W2689 With this measure, the unit circuits of the DCR3 can be arranged without limiting the pitches of the word lines in the integrated circuit device. In other words, the packaging density of the plurality of memory elements in the memory array MARY need not be lowered.

The outputs dcrl and dcrl of the respective unit circuits of the address decode portion DOUR1 are supplied to the corresponding eight unit circuits in the address decode portion DOUR3.

Since the corresponding decoded address signals dcr1 are delivered from the respective unit circuits of the DCR1,the number of the driving MISFETs in the unit circuit Ond of the DCR3 can be reduced.

Owing to the above arrangement, the output dcr3 of one unit circuit in the DCR3 is made the high level only when the address signals of 6 bits are brought into a predetermined status. That is, among the outputs of the 64 unit circuits in the DOUR3, only the output of one unit circuit corresponding to the status of the 6-bit address signals fed to the DCR1 and DCR3 is made the high level.

The output signal dcr3 of one unit circuit in the DCR3 is supplied in common to one-side electrodes of four enhancement-mode transfer gate MISFETs Q7, Q , Q and Q,3 which correspond to the word lines one to one, respectively. These transfer gate MISFETs are controlled "on" and "off" by the output signals of the address decode portion DOUR2.

The address decode portion DOUR3 is constructed of four unit circuits each of which decodes the address signals of 2 bits thereby to deliver the non-inverted signal and the inverted signal. Figure 2 illustrates one unit circuit Nnd among the four unit circuits constituting the address decode portion DOUR2. The output signal dcr2 of the unit circuit Nnd is supplied to the gate of the transfer gate MISFET Q7. Likewise, the gates of the remaining transfer gate MISFETs Q,, Q" and Q,3 are supplied with the output signals of the unit circuits not shown.

The transfer gate MISFETs Q7, Q,, Q" and Q,3 are alternatively brought into the "on" state by the signals fed from the address decode portion DOUR2. Accordingly, one output signal of the address decode portion DCR2 is transmitted through one of the four transfer gate MíSFETs to the other-side electrode or output electrode of the particular MISFET.

Enhancement-mode MíSFETs Q8, Q,,, Qa2 and Q,4 are located between the respective output terminals of the enhancement-mode transfer gate MlSFETsC7, C9, Q11 and Q,3 and the earth terminal GND of the circuit. The gate of the MISFET C8 is supplied with a signal dcr2 delivered from the unit circuit Nnd.Likewise, the gates of the MlSFETs Qao, Q12 and Q14 are respectively supplied with signals which are opposite in phase to the signals fed to the gates of the transfer gate MISFETs Q9, Q" and Q,3. Accordingly, one set of the MISFET and the transfer MISFET, for example, those Q8 and Q7 are complementarily switched and operated.

Transfer gate MISFETs C18-Q18 of the depletion mode are located between the respective output-side electrodes of the transfer gate MISFETs Q7, Q,, Q11 and Q13 and the word lines W1-W4 corresponding to these output electrodes. A write-down control signal we is applied in common to the gates of the transfer gate MISFETs C15-C19. Depletion-mode MISFETs C19, Q20 etc. each of which has its gate and source connected and which serve as load means are located between the word lines and the high write-down voltage terminal Vpp.Although not especially restricted, the depletion-mode MISFETs Q,5Q20 are put into the stacked gate structure, thereby to possess drain breakdown voltages of a value greater than the high voltage which is applied to the high write-down voltage terminal Vpp.

The 256 (64x4) word lines W1-W288 can be selected by the X-DCR of the above arrangement.

As will become apparent from later description, the non-selected word lines are made the low level which is approximately equal to earth potential (0 volt) of the circuit. On the other hand, the selected word lines are made the high level approximately equal to the power source voltage (+5 volts) at the terminal Vcc during the read-out operation, and they are made a high voltage substantially equal to the high voltage (+25 volts) fed to the high write-down voltage terminal Vpp during the write-down operation.

Figure 3 shows a practicable circuit of an embodiment of the unit circuit constituting the address decode portion DCR,.

Referring to figure 3, the decode portion is constructed of a depletion-mode load MISFET Q2.

whose gate electrode and source electrode are coupled, driving MISFETs C23-C25 whose gates are respectively supplied with the internal address signals a1-a3, and a MISFET Q22 which is located between the common-connected source electrodes of the driving MISFETs C23-C28 and the earth terminal and whose gate is supplied with the control signal ce. The output signal of the decode portion is supplied, on one hand, through a cutting MISFET C26 to the gates of a MISFET Q28 and an output MISFET Q30 arranged on the power source terminal side, and on the other hand, to the gates of enhancement-mode driving MISFETs Q37 and Q40.

An inverter circuit is constructed of a depletion-mode load MISFET Q36 whose gate electrode and source electrode are coupled, the enhancement-mode driving MISFET C37, and an enhancement-mode power switch MISFET Q38 whose gate is supplied with the control signal ce.

The output signal of this inverter circuit is applied to the gates of output MISFETs Q32 and Q39, and is also applied to the gate of a MISFET Q3 through a delay circuit CR3. As will be described in detail later with reference to Figure 4, the delay circuit CR3 is provided in order to cause a bootstrap capacitor C8 to store large quantities of charges.

Afirst push-pull output circuit is constructed of MlSFETs of the enhancement-mode Q40 and Q41 which are connected in series and whose gates are respectively supplied with the output signal of the decode portion and the control signal ce, and the output MISFET Q39 whose gate is supplied with the output signal of the inverter circuit. The first push-pull output circuit provides the decode signal dcr1 which is inverted with respect to the output signal of the decode portion.

The output MISFETs Q30 and Q32 construct a second push-pull output circuit. Owing to a circuit connection as shown in the figure, the decode signal dcr1 is delivered from the common juncture of the output MlSFETs Q30 and C32.

In Figure 3, the MISFETs Q28 and Q31 and the bootstrap capacitor C9 constitute a bootstrap circuit. The decode signal supplied to the gates of the output MISFETs Q30 and Q33 through the cutting MISFET Q26 has its level raised above the power source voltage Vcc by the bootstrap circuit.

The output MISFET Q30 has its gate potential raised sufficiently, resulting in possessing a sufficiently low "on" resistance. Owing to the sufficiently low "on" resistance of the output MISFET Q30, even when the DCR3 forms a comparatively heavy capacitive load, the rise speed of the decoder signal dcr1 is permitted to be sufficiently high. In addition, since the level of the decoder signal dcr1 can be sufficiently raised, the loss of the word line selection level relative to the power source voltage Vcc in the read-out operation can be made low.

In Figure 3, a MISFET Q27 is provided in order to discharge the stored charges of the bootstrap capacitor CB, and the "on" and "off" states~ thereof are controlled by the control signal ce.

In the circuit of Figure 3, a voltage divider circuit and resistance means as stated below are further provided in order to permit the operation of performing read-out in the state in which the high voltage (for example, +25 volts) is applied to the high write-down voltage terminal Vpp, or the so-called the verify operation.

An enhancement-mode MISFET Q34 and a depletion-mode MISFET Q35 which constitute the voltage divider circuit are connected in series between the high write-down voltage terminal Vpp and the logic power source voltage terminal Vcc.

The gates of these MISFETs Q34 and Q35 are connected to the respective drains. Although not especially restricted, the MISFETs Q34 and Q35 are put into the stacked gate structure thereby to possess comparatively high drain breakdown voltages.When the high write-down voltage of, for example, +25 volts is kept applied to the terminal Vpp, a voltage which is higher than the power source voltage of the terminal Vcc is delivered to the common junction of the MISFETs Q34 and Q35. In the verify operation, it is more desirable that the potential of the word line to be selected is made a level which is substantially equal to the voltage level of the word line to be selected in the data read-out operation, in other words, a level which is substantially equal to the power source voltage Vcc. As will be understood from later description, the potential level of the word line to be selected from among the word lines shown in Figure 2 is made substantially equal to the level of the output signal dcr3 of the decoder portion DCR3 during the verify operation.

Accordingly, the high level of the output signal dcr3 must be made substantially equal to the level of the power source voltage Vcc during the verify operation in spite of the presence of the enhancement-mode power switch MISFET Q1 The voltage which is delivered to the common junction of the MISFETs Q34 and Q35 upon the application of the high write-down voltage of +25 volts to the terminal Vpp is made approximately +7 volts in order to favorably bring the power switch MISFET Q1 into the "on" state.This voltage can be obtained by properly setting the conductance ratio between the MISFETs Q34 and Q35 This voltage of +7 volts is supplied to the source electrode of the output MISFET C30 through a MISFET C33 as the resistance means.

When the signal dcr1 is raised to the level of +7 volts by the MISFET Q33, the output MISFET Q30 must be put into the "off" state.

Assuming that the gate voltage of the output MISFET Q30 rises above the voltage of the terminal Vcc in excess of the threshold voltage of the MISFET, this output MISFET Q30 maintains the "on" state even when its source potential is made the voltage of the terminal Vcc or above. As a result, the high level of the decode signal dcr1 is clamped substantially at the voltage of the terminal Vcc by the output MISFET C30 in the "on" state.

In Figure 3, to the end of preventing the high level of the decode signal dcrl from being limited by the output MISFET Q30, a clamping MISFET C29 is located between the power source terminal Vcc and the gate of the MISFET Q30. The threshold voltage of this MISFET C29 is set to be smaller than that of the MISFET Q30.

The clamping MISFET Q29 falls into the "on" state when a bootstrap voltage has risen above the power source voltage Vcc in excess of the threshold voltage thereof. Accordingly, the bootstrap voltage is clamped at a magnitude which is substantially equal to the sum between the power source voltage Vcc and the threshold voltage of the MISFET Q29 Owing to the clamp of the bootstrap voltage in this manner, the output MISFET C30 is automatically brought into the "off" state when its source potential is made approximately the power source voltage Vcc. As a result, the high level of the decode signal dcr1 can be raised to a magnitude near the voltage formed by the voltage divider circuit (Q34, C38).

The operation of the address decode portion DCR1 shown in Figure 3 becomes as stated below.

When the chip non-selection status is indicated by the high level of the control signal supplied to the external terminal CE in Figure 1, the internal control signal ce is responsively made the low level, and that ce the high level. In this chip non-selection status, the power switch MISFET C22 is brought into the "off" state by the internal control signal ce of the low level. The decode portion therefore provides a voltage substantially equal to the voltage of the terminal Vpp irrespective of the address signals supplied to the driving MISFETs C23-C25 included therein.

Since the power switch MISFET C41 is kept in the "off' state by the control signal ce of the low level, the decode signal dcr1 is made the high level substantially equal to the voltage of the terminal Vpp. Since the output MISFET C32 is kept in the "on" state, the decode signal dcr1 is made the low level substantially equal to earth potential of the circuit. Meantime, the MISFET C27 is kept in the "on" state by the internal control signal ce of the high level. The MISFETs Q28 and Q30 are brought into the "off" state because their gate electrodes are held at the low level by the MISFET C27 in the "on" state.Accordingly, no through current flows in the output MISFETs Q30 and Q31 connected in series. The bootstrap capacitor C8 is put in the discharge state because its two terminals are made the low level by the MlSFETs Q27 and C31 in the "on" state, respectively.

When the control signal supplied to the external terminal CE is made the low level or the chip selection level, the internal control signals ce and ce are made the low level and the high level, respectively. Thus, the decode portion in Figure 3 is brought into the operating status. If the address signals a1-a3 are not in a status to be decoded, that is, if at least one of the address signals a1-a3 is made the high level, then at least one of the MISFETs C23-C25 is brought into the "on" status, and hence, the decode portion provides a signal of the low level, namely, a signal of the nonselective level. Thus, the decode signals dcrl and dcr1 are left intact at the high level and the low level, respectively.

If the address signals a1-a3 are in the status to be decoded, then all the MISFETs Q23Q2s are brought into the "off" state, so that the decode portion provides a signal of the high level or a signal of the selective level. In response to this signal, the decode signals dcr1 and dcrl are respectively changed into the low level and the high level.

The operations of the second push-pull output circuit and the bootstrap circuit at the time when the output signal of the decode portion has been changed as described above, become as stated below.

When the internal control signal cue is made the low level thereby to bring the MISFET Q27 into the "off" state, the output signal of the decode portion is supplied through the cutting MISFET C26 to the gate of the output MISFET Q30 and one terminal of the bootstrap capacitor C8. The gate of the output MISFET C32 is supplied with the low level signal from the drain of the MISFET Q37. As a result, the decode signal dcrl is made the high level.

The drain voltage of the MISFET C37 is made the low level in response to the high level output signal of the decode portion when the internal control signal ce has been made the high level.

The low level drain voltage of the MISFET C37 is supplied to the gate electrode of the MISFET Q through the delay circuit CR3.

The MISFET C3i is brought into the "off" until a delay time determined by the delay circuit Cur, lapses since the internal control signals ce and ce have been made the high level and the low level respectively. Accordingly, the bootstrap capacitor C8 is started to be charged by the high level output of the decode portion.

The MISFET C31 is brough intot into the "off" state after the predetermined time decided by the delay circuit CR3. The other terminal of the bootstrap capacitor C8 is responsively supplied with a comparatively high voltage from the source of the MISFET Q28 As a result, the gate of the output MISFET C30 is supplied with the bootstrap voltage. At this time, the cutting MISFET 028 is automatically brought into the "off" state by the bootstrap voltage. Accordingly, the cutting MISFET 028 prevents the stored charges of the bootstrap capacitor C8 from being discharged undesirably.Since the undesirable discharge of the charges in the bootstrap capacitor C8 is prevented, the bootstrap voltage is maintained at a good level for a comparatively long time.

In the case where the delay circuit CR3 has been removed from the arrangement of Figure 3, the MISFET C31 is brought into the "off" state as soon as the drain output of the MISFET C37 is made the low level. Therefore, it becomes difficult to set a period of time suitable for charging the bootstrap capacitor C8. Since sufficient charges are not stored into the bootstrap capacitor C8, it becomes impossible to apply a bootstrap voltage of sufficient level to the gate electrodes of the MISFETs Q30 and Q33. In consequence, it becomes difficult to satisfactorily bring the output MISFET Q30 and the MISFET Q33 into the "on" state.

The circuit arrangement of Figure 3 can be replaced with an arrangement in which the drain output of the MISFET C37 is applied in common to the gates of the MlSFETs Q31 and Q32 through a delay circuit. In this case, however, the ensuing problems occur. Since the switching operation of the MISFET C32 is delayed a delay time, the generation timing of the decode signal dcrl cannot be quickened. Moreover, the output MISFETs Q30 and Q32 are simultaneously held in the "on" state for a period of time approximately equal to the delay time of the delay circuit.As a result, a comparatively great through current flows to the output MISFETs Q30 and Q32 over the comparatively long time.

In the circuit of Figure 3, the gate of the cutting MISFET 028 is supplied with the voltage of the power source terminal Vcc. During the chip non selection, therefore, direct currents flow to the load MISFET Q21, the cutting MISFET Q26 and the MISFET C27 of the decoder portion. In the case where such current consumption during the chip non-selection needs to be avoided, the internal control signal ce is applied to the gate of the cutting MISFET C28.

Although not shown, a practicable circuit of the address decode portion DCR2 is constructed similarly to the circuit of the address decode portion DCR1 in Figure 3.

However, the unit circuit which constitutes the address decode portion DCR2 is different from the circuit shown in Figure 3 in the two points that it is supplied with the address signals of medium two bits and that it is not provided with MISFETs corresponding to the MISFETs Q38 and C41.

Accordingly, the signal of the non-inverted level such as the signal dcr2 to be delivered from the address decode portion DCR2 is made the selective level substantially equal to the power source voltage Vc or the non-selective level substantially equal to earth potential in the data read-out operation mode, and it is made the selective level nearly equal to +7 volts or the nonselective level substantially equal to earth potential in the write-down operation mode and the verify operation mode. The signal of the inverted level such as the signal dcr2 is made the selective level substantially equal to earth potential, or the non-selective level substantially equal to (VccVth) (where Vth denotes the threshold voltage of the MlSFETsuch as the MISFET Q39 in Figure 3).

The MISFET such as the transfer gate MISFET Q7 which corresponds to the word line to be selected is favourably put into the "on" state even in the verify operation mode because the output signal of the address decode portion DCR2 is made the level as described above.

In the address decode portions DCR1 and DCR2, in order to make the threshold voltage of the MISFET such as the clamping MISFET 028 smaller than that of the MISFET such as the output MISFET Q30, the short channel effect is utilized though no special restriction is intended.

That is, the MISFET such as the MISFET C28 has its channel length made smaller than the channel length of the MISFET such as the output MISFET Q30. In this case, the relationship of magnitudes of the threshold voltages between the MISFETs of different channel lengths is not substantially affected by the dispersion of the manufacturing process of the IC. Accordingly, the gate voltage of the MISFET such as the output MISFET C30 is clamped at an appropriate level by the MISFET such as the MISFET Q29 This method exploiting the short channel effect has the advantage that the number of stages of work for.

the manufacture of the IC need not be increased.

Now, the operation of the EPROM in Figures 1 to 3 will be described.

The FAMOS transistor as the memory element is caused to hafe a comparatively low threshold voltage of, e.g., +2 volts in the state in which a data has been erased, that is, in the state in which substantially no charge is stored in the floating gate thereof. The FAMOS transistor is also caused to have a comparatively high threshold voltage of, e.g., +7 volts or above in the state in which a data has been written down, that is, charges are stored in the floating gate thereof.

The write-down of a data into the+AMOS transistor is executed as stated below. The high write-down voltage of a value often volts or greater is generated from the read-out/writedown circuit, and it is supplied through the CSW to the bit line with which the memory element to be selected is coupled. Simultaneously therewith, the signal of the high level of a value of, e.g., +25 volts is supplied from the X-DCR to the word line to be selected. Owing to these voltages, hot electrons are created in the vicinity of the drain of the FAMOS transistor to-be-selected by the high drain voltage and channel current. The hot electrons flow into the floating gate through a gate insulating film.No data is written down into the non-selected FAMOS transistors whose drains are coupled with the selected bit line, because the respectively corresponding word lines are held at the low level or non-selective level which is substantially equal to zero volts.

In reading out a data from the memory element, the selected word line is made a level intermediate between the lower threshold voltage and higher threshold voltage of the memory element or a level approximately equal to the power source voltage Vcc, while the non-selected word lines are made the non-selective level approximately equal to zero volts. In the read-out of the data, accordingly, the selected memory element falls into the "on" state or "off" state in accordance with the lower threshold voltage previously determined by the written data.

Now, the verify operation will be described. In the verify operation, the high voltage of, e.g., +25 volts is kept applied to the high write-down voltage terminal Vpp.

Let it now be supposed that predetermined ones of the internal address signals a1 to a8 have been made the low level so as to select the first word line W1 shown in Figure 2. In this case, the decode signal dcr1 of the address decode portion DCR1 shown in Figure 2 is made the high voltage level of approximately 7 volts, while the decode signal dcrl is made the low level approximately equal to earth potential. The decode signal dcr2 of the address decode portion DCR2 is made the high voltage level of approximately 7 volts, while the decode signal dcr2 is made the low level approximately equal to earth potential.

The power MISFET Q1 in Figure 2 is brought into the "on" state by the decode signal dcr1 of the high level. The drain of the MISFET Q2 is supplied through the MISFET Q1 with 5 volts being substantially the level of the power source voltage Vcc. The MISFETs C3-C8 are brought into the "off" state by the low level of the decode signal dcrl and the low level of the address signals a8-a8, with the result that the decode signal dcr3 is made the high level of approximately 5 volts. The transfer gate MISFET Q7 is brought into the "on" state because the decode signal dcr2 supplied to its gate electrode has been made the high level of approximately 7 volts.Therefore, the decode signal dcr3 of approximately 5 volts is transmitted to the output electrode of the transfer MISFET Q7.

The verify operation is appointed by, for example, making the external terminals PRG and OE the high level and the low level respectively. In the verify operation, the internal control signal we is made the high level of, e.g., +5 volts approximately equal to the voltage of the power source terminal Vc. The depletion-mode MISFETs Q,5 to Q18 are brought into the "on" state by the internal control signal we of the high level.

Accordingly, the decode signal dcr3 transmitted to the output electrode of the transfer gate MISFET Q7 is further transmitted to the word line W1 through the depletion-mode MISFET Q,5.

In the verify operation, in the case where the high level of the decode signal dcr2 is approximately equal to the high level of the decode signal dcr3, the selected word line W, is made the high level of approximately +25 volts in accordance with the write-down voltage supplied to the terminal Vpp, as will now be explained.

The input electrode of the transfer gate MISFET Q7 acts as a source electrode. The transfer gate MISFET Q7 is substantially brought into the "off" state because the level difference between the decode signal dcr3 applied to its source electrode and the decode signal dcr2 applied to its gate electrode is small. As a result, the voltage of the word line W, is raised by the MISFET Q,g up to a voltage substantially equal to the voltage supplied to the terminal Vpp.

When each unit circuit constituting the decode portion DCR2 is made the arrangement similar to the circuit of Figure 3 ;as described before, the decode signal dcr2 has its high level made a sufficiently great voltage. The transfer gate MISFET Q7 is favourably brought into the "on" state by the decode signal dcr2 of the high voltage applied to the gate electrode thereof. As a result, the word line W, to be selected can be made the desirable value of approximately +5 volts.

The word lines other than the word line W1, that is, the non-selected word lines are respectively made the low level approximately equal to earth potential because the MISFETs Q10, Q,2, Q,4 etc. are brought into the "on" state by the inverted signal of the address decode portion DCR2.

In the write-down operation, the levels of the respective word lines are made as follows.

Assuming that the word line W1 is to be selected, the transfer gate MISFET Q7 is brought into the "on" state as described before. In response thereto, the decode signal dcr3 of approximately +5 volts is applied to the source electrode of the depletion-mode transfer gate MISFET Q15 through the transfer gate MISFET Q7 The transfer gate MISFET Q15 has its gate electrode held at approximately zero volt by the internal control signal we. Accordingly, the transfer gate MISFET C15 is brought into the "off' state because its gate electrode potential is equivalently made approximately5 volts when its source electrode potential is regarded as zero volts.

The MISFET C18 as high resistance means is connected between the word line W1 and the terminal Vpp. Accordingly, when the transfer gate MISFET Q15 has been brought into the "off' state, the word line W1 is made approximately 25 volts by the voltage which is fed through the load MISFET C18 from the terminal Vpp. On the other hand, the non-selected word lines are made the low level approximately equal to earth potential because the MISFETs Q1O, Q,2, Q,4 etc. are brought into the "on" state similarly to the above whereby the transfer gate MISFETs Q,6Q,8 are brought into the "on" state.

In the read-out operation, the high write-down voltage terminal Vpp is made 5 volts.

The enhancement-mode MISFET Q34 constituting the voltage divider circuit shown in Figure 3 is brought into the "off" state in such a way that the terminal Vpp is made +5 volts.

Accordingly, the MISFET Q34 does not exert any adverse effect on the read-out operation.

Since, in the EPROM of this embodiment, the decoder portions has the circuit arrangement as shown in Figures 2 and 3, the write-down depth of a data in the memory element or the threshold voltage of the memory element can be decided as will be explained below.

In deciding the threshold voltage, first of all, the high write-down voltage terminal Vpp is made coincident with the threshold voltage level to-bedecided, for example, +12 volts. Subsequently, the data of the respective memory elements are read out in the verify operation mode. Data signals delivered to the external terminal I/O are compared with an expected value.

During the operation of deciding the threshold voltage, the voltage divider circuit which divides the voltage across the terminals Vpp and Vcc delivers a divided voltage lower than the aforecited voltage of +7 volts because the voltage of the terminal Vpp is made a comparatively low value of, e.g., + 1 2 volts. The lowering of the divided voltage results in lowering the high level of the decode signals to be provided from the decoder portion DCR2. The transfer gate MISFETs Q7, Qs, Q", Qa3 etc. fail to fall into the "on" state even when the high level signals are delivered from the decoder portion DCR2. As a result, the word line to be selected, for example, W1 is made coincident with the voltage equal to that of the terminal Vpp, i.e., the decision level.The nonselected word lines are made the low level approximately equal to earth potential because the respectively corresponding MlSFETs Q10, Qua2, Q,4 etc. are brought into the "on" state by the outputs of the decoder portion DCR2.

The memory element having the greater threshold is not substantially brought into the "on" state even by the voltage of the decision level applied to the gate electrode thereof.

Accordingly, whether or not the threshold voltage of each memory element has been made greater than the voltage of the terminal Vpp can be decided by referring to the data signal delivered to the external terminal I/O.

The circuits shown in Figures 1 to 3 can be modified.

For example, the voltage divider circuit can be altered into various ones including one constructed merely of resistance means. Further, the practicable circuit of the X-DCR may be any circuit that employs enhancement-mode transfer gate MlSFETs in an output stage so as to form word line selection signals. In addition, the voltage clamp means such as the MISFET Q29 may well be one utilizing a diode or the like.

Figure 4 shows a practicable circuit of the control circuit which forms the internal control signals ce and ce of suitable levels by receiving the control signal from the external terminal CE.

The circuit of Figure 4 is composed of a first circuit PC which is constructed substantially of a push-pull circuit, and a second circuit BC which is constructed of a push-pull circuit including a bootstrap circuit.

Signal waveforms at various nodes in the circuit of Figure 4 are shown in Figure 5. Symbols assigned to the signal waveforms in Figure 5 correspond to symbols assigned to the nodes in Figure 4.

First, the second circuit BC will be explained.

This second circuit BC is constructed of an enhancement-mode MISFET E8 whose gate is supplied with an output signal from the first circuit PC, a depletion-mode MISFET D3, a cutting MISFETE8, a depletion-mode MISFET D4, an enhancement-mode MISFET E7, a bootstrap capacitor C8, enhancement-mode MISFETs E8, Eg, E10 and Ear1, and a delay circuit CR2.

The MISFETs E5 and D3 constitute one inverter circuit. Similarly, the MISFETs E7 and D4 constitute one inverter circuit. The MISFETs E10 and E" constitute a push-pull output stage.

As shown in the figure, the delay circuit CR2 is constructed of a resistor R2 and capacitors Cs3 and Cs4, and it is connected between the gate electrode of the MISFET E" and the gate electrode of the MISFET E8.

The cutting MISFET E8 is provided in order to electrically isolate a node E and a node H when the voltage level of the node H has been raised above the power source voltage Vcc. Since the cutting MISFET E6 is provided stored charges of the bootstrap capacitor C8 are prevented from being discharged undesirably.

The operation of the second circuit BC will now be described.

When a node D is kept at the low level as is substantially equal to earth potential, the MISFET E8 is thereby held in the "off' state. The "off" state of the MISFET E8 renders the node E the high level which is substantially equal to the power source voltage Vcc. The node H is made the high level in correspondence with the high level of the node E.

A node F is held at the low level because the MISFET E7 is held in the "on" state by the high level of the node. E. A node G is held at the low level similarly to the node F. Since the node H is held at the high level and the node F at the low level, the push-pull output stage constructed of the MlSFETs E10 and E" provides the output signal ce of the high level.

In the case where the node D is kept at the high level approximately equal to the level of the power source voltage Vcc, the output signal of the push-pull stage is made the low level approximately equal to earth potential because the MISFETs E10 and E" included therein are respectively brought into the "off" state and the "on" state.

The bootstrap capacitor C8 is charged in a comparatively short period at the time when the signal at the node E has been turned from the low level to the high level.

More specifically, in the case where the node E is kept at the low level, the MISFET E8 is held in the "on" state owing to the high level of the node G. A node I is kept at the low level approximately equal to earth potential because the MISFET E8 is held in the "on" state. Since the cutting MISFET E6 has its gate electrode maintained at the power source voltage Vcc, it maintains the "on" state as long as the potential of its electrode acting as a source electrode between its input and output electrodes is kept at a value lower than (VccVth) (where Vth denotes the threshold voltage of the MISFET E6). Accordingly, the bootstrap capacitor has its charges discharged through the MISFETs E8 and E5.

When the node E has been turned from the low level to the high level approximately equal to the power source voltage level, the node H responds thereto to become the high level. The node I is made the high level in such a way that the MISFET E8 having been in the "on" state is brought into the "off" state. The bootstrap capacitor C8 is accordingly charged in the period after the node E has been made the high level and before the MISFET E8 is made the "off" state.

When the MISFET E8 has been brought into the "off" state, the node I is made the high level by the MISFET E8. The node H is made a potential above the power source voltage Vcc by the bootstrap capacitor C8 charged in advance. Owing to the rise of the potential of the node H to above the power source voltage, the output MISFET E10 comes to have a sufficiently low "on" resistance.

Since the MISFET E,, has the potential of its gate electrode raised in excess of the power source voltage Vcc, it is favourably brought into the "on" state even when the potential of an output terminal OUT has reached substantially the power source voltage Vcc. As a result, it is permitted to supply a signal of high speed and sufficient level to a capacitive load, not shown, which is coupled with the output terminal OUT.

The charging speed of the bootstrap capacitor C8 is limited by the "on" resistances of the MISFETs D3, E8 and E8. In the case where the delay circuit CR2 has been removed from the second circuit BC shown in Figure 4, the MISFET E8 is brought into the "off" state within a comparatively short time after the node E has been made the high level. As a result, it becomes difficult to afford sufficient stored charges to the bootstrap capacitor C8. Insufficient charging of the bootstrap capacitor C8 renders it difficult to sufficiently increase a bootstrap voltage.

In contrast, owing to the provision of the delay circuit CR2 in the embodiment, the signal which is applied to the MISFET E8 can be delayed appropriately relative to the signal at the node E.

As a result, as illustrated in Figure 5, the MISFET E8 can be held in the "on" state for a while after the MISFET E" has fallen into the "off" state. Thus, the period of time t22 during which the node H is at the high level with respect to the node I becomes long as in the circuit of Figure 3, so that the quantity of charges to be stored into the bootstrap capacitor C8 can be made large. In consequence, when the MISFET E8 has turned from the "on" state into the "off" state, the level of the node H can be made sufficiently high, and it becomes possible to apply a sufficiently high voltage to the gate of the MISFET E10. The mutual conductance g, of the MISFET E10 therefore becomes sufficiently great, so that the drivability for the load can be enhanced.

In the next place, the first circuit PC which is constructed as a preceding-stage circuit for the second circuit BC will be described.

The first circuit PC is constructed of an inverter circuit which is composed of an enhancementmode driving MISFET E1 having its gate connected to an input node IN and a depletionmode load MISFET D, connected to the MISFET E" an inverter circuit which is composed of an enhancement-mode driving MISFET E2 and a depletion-mode load MISFET D2, a push-pull output circuit which is composed of enhancement-mode MISFETs E3 and E4, and a delay circuit CR,. Although not especially restricted, the delay circuit CR1 is constructed of a resistor R1 and capacitors C51 and Cs2 and is connected between the gate electrode of the MISFET E2 and that of the MISFET E4.

By appropriately setting the values of the resistor R, and the capacitors C81 and Cs2, the delay circuit CR1 is endowed with a delay characteristic substantially equal to that of the inverter circuit composed of the MISFETs D2 and E2.

As will be explained below, the delay circuit CR1 reduces the power consumption of the pushpull circuit PC. In addition, the delay circuit CR1 suppresses the generation of noise in the circuitry.

In consequence, when the whole circuit of Figure 4 is implemented as an IC, this circuit and other circuits formed on an identical chip can be stably operated with a comparatively small power source.

For a better understanding of the reason why the delay circuit CR1 is used, there will be first explained the circuit operation in the case where the delay circuit CR1 is not provided.

In the inverter circuit composed of the MISFETs D2 and E2, an output signal to be provided therefrom is delayed by parasitic capacitances which are coupled with the output end thereof and which include the drain capacitance of the MISFET E2, the source capacitance of the MISFET D2, the gate capacitance of the MISFET E3, and wiring capacitances (none of them being shown).

In the case where the delay circuit CR1 is not provided, an inverted signal which is supplied to a node C through the inverter circuit composed of the MISFETs D2 and E2 is delayed relative to a signal which is supplied to a node B or a signal which is supplied to a node A. In accordance with the signal delay, the period of time during which the nodes B and C are simultaneously made above the threshold values of the MISFETs arises.

This results in the following problems.

(i) The period of time during which both the MlSFETs E3 and E4 are "on" arises, and a through current flows in these MISFETs E3 and E4. The control signal formed by the MISFETs E3 and E4 is supplied in common to a plurality of circuits as shown in Figure 3. The plurality of circuits have a great input capacitance as a whole even when the input capacitance of each of them is comparatively small. In consequence, a comparatively heavy capacitive load is coupled to the output terminal of the push-pull output circuit composed of the MISFETs E3 and E4. For this reason, the MISFETs E3 and E4 are made comparatively large in size to the end of permitting a comparatively great current to flow to the output node D.

Therefore, the through current which flows through the MISFETs E3 and E4 connected in series comes to have a large value as comapred with currents which flow through the other inverter circuits etc. The aforecited through current increases the power dissipation of the EPROM comparatively greatly.

(ii) In an integrated circuit device, power source wirings formed on a semiconductor substrate, such as a power source wiring layer, connector wire for a power source and a lead wire for the power source, include resistance components and inductance components which are not negligible.

Moreover, the power source wirings substantially form undesirable coupling capacitances with various signal wiring layers of the circuitry.

The through current which flows to the seriallyconnected MISFETs E3 and E4 in the transient period of a signal change causes on the power source wirings comparatively great potential changes as are deemed noise. In the semiconductor integrated circuit device, a plurality of circuits are coupled with an identical power source wiring. Accordingly, the potential changes on the power source wirings are also supplied directly to various circuits not shown.

The various circuits become prone to malfunctions because the reference potential thereof is changed by the potential change on one wiring of the power source.

The fluctuating potential of the power source wiring also affords an undesirable potential change as deemed a noise, on a signal line through the undesirable coupling capacitance as stated above. By way of example, a capacitive coupling develops between the positive power source wiring Vcc and the node E in Figure 4 through a capacitance not shown. Therefore, the level of the node E fluctuates in accordance with the fluctuation of the level of the positive power source wiring, and a malfunction or the lowering of the operating speed takes place in this circuit.

(iii) An experiment has revealed that, when a comparatively great through current flows through the serially-connected MISFETs E3 and E4,the level of the output node D varies as indicated by a solid-line curve NO in Figure 6.

Regarding the fact that the signal level increases at approximately the medium level in the fall of the output signal as shown by the solid-line curve NO in Figure 6, the cause has not been satisfactorily cleared. It is conjectured, however, that transient changes will occur in the positive side power source voltage and the reference potential side power source voltage on account of the through current and the inductance components, capacitance components etc. existing on the power source wirings.

Anyway, in the case where the signal at the output node D varies as indicated by the solid-line curve NO in Figure 6, the fall time of the signal at this output node is substantially increased, with the result that the operating speed of the EPROM is limited. In Figure 6, the level of the threshold voltage Vth of the circuit as in Figure 3 to which the signal of the output node D is supplied is indicated by a dot-and-dash line.

In contrast, when the delay circuit CR1 of the delay characterstic as previously stated is provided the problems as described above are solved.

More specifically, when the level of the node A has been turned from the low level to the high level as shown in B of Figure 5, the signal at the node C responds thereto to become lower than the threshold voltage Vth of the MISFET E3 after a delay time determined by the inverter (D2, E2) as illustrated in C of Figure 5. On the other hand, the signal at the node B is subjected to a time adjustment relative to the signal of the node A as illustrated in B of Figure 5 because the delay circuit CRa is provided. That is, the period of time in which the signal of the node B becomes higher than the threshold voltage Vth of the MISFET E4 is equalized to the period of time in which the signal of the node C becomes lower than the threshold voltage Vth of the MISFET E3.As a result, the period of time during which the MISFETs E3 and E4 are simultaneously held in the "on" state is substantially prevented from being formed, whereby the through current to flow through the MISFETs E3 and E4 is remarkably reduced. In this case, the signal at the node D falls within a comparatively short time as indicated by a broken-line curve N1 in Figure 6.

It is accordingly permitted to operate the EPROM at a comparatively high speed.

In the case where, conversely to the above case, the level of the node A is turned from the high level to the low level, it can take place due to the disposition of the delay circuit CR1 that the period of time during which both the nodes B and C become the high level is formed. Such period of time, however, can be shortened to a substantially negligible extent by making the MISFET D2 in the inverter (D2, E2) a proper size.

More specifically, when the level of the node A has been turned from the high level to the low level, the driving MISFET E2 responds thereto to fall into the "off" state, and hence, the level of the node C rises from the low level to the high level.

In this case, the rise speed of the signal level of the node C is limited by the characteristics of the load MISFET D2 and parasitic capacitances, such as the gate capacitance of the MISFET E3, which are substantially coupled to the node C. By making the load MISFET D2 the proper size, therefore, the rise speed of the signal level of the node C can be appropriately determined. The period of time in which the signal of the node C becomes at least the threshold voltage Vth of the MISFET E3 is appropriately set relative to the period of time in which the signal of the node B becomes at most the threshold voltage of the MISFETE4, whereby the period of time t2, during which the MISFETs E3 and E4 are simultaneously held in the "on" state can be shortened as shown in F of Figure 5.Accordingly, the through current is made a comparatively small value as indicated as lo in F of Figure 5.

In the circuit of Figure 4, the delay circuit CR can be altered into a circuit wherein two or another even number of inverter circuits each being constructed of MISFETs D2 and E, are connected in series. Even in such case, a through current as stated before can be made a substantially negligible level by properly determining the size of the MISFET (not shown) of the inverter circuit for the signal delay.

In accordance with this invention, there are provided suitable structures of circuit elements for constructing the push-pull circuit and the delay circuit.

Figure 7 shows the plan pattern of circuit elements which constitute the first circuit PC in the circuit of Figure 4, while Figure 8 shows the section of a semiconductor substrate along a part A-A' in Figure 7.

Although not especially restricted, the circuit elements shown in Figures 7 and 8 are formed by the known selective oxidation technique, the socalled self-alignment technique introducing an impurity by utilizing also as an impurity introducing mask a polycrystalline silicon layer which is used as a conductor layer or as the gate electrode of a MISFET, and so forth. MISFETs are made the nchannel type, and are formed on a p-type silicon substrate.

In Figure 7, the patterns of semiconductor regions such as the drain regions and source regions of the MISFETs are indicated by two-dot chain lines, and the patterns of polycrystalline silicon layers which are used as the gate electrodes and wiring layers of the MISFETs are indicated by broken lines. Further, the patterns of wiring layers as are made of evaporated aluminium layers are indicated by solid lines. The channel regions of the MISFETs are indicated by rightwardly rising hatching. The contact portions between the conductor layers and the semiconductor regions and those between the conductor layers and the polycrystalline silicon layers are indicated by square patterns to which marks x are affixed.

The principal surface of a semiconductor substrate 1 made of p-type single crystal silicon is formed with a comparatively thick field oxide film 2 which is formed by the local oxidation and which has a thickness of, e.g., about 1 ,um. In the principal surface of the semiconductor substrate 1, parts which are not covered with the field oxide film 2 are used as active regions for forming the circuit elements or semiconductor wiring regions.

On the active regions of the semiconductor substrate 1, a polycrystalline silicon layer 3 for wiring layers or gate electrodes is formed through a comparatively thin gate oxide film. If necessary, the polycrystalline silicon layer 3 is extended also on the field oxide film 2. In the surface of the semiconductor substrate 1 to be made the active regions, parts which are not covered with the polycrystalline silicon layer 3 are formed with ntype semiconductor regions for the source regions and drain regions of the MISFETs or semiconductor wiring regions. On the principal surface of the semiconductor substrate 1 and also on the polycrystalline silicon layer 3, an insulating film 4 for an inter-layer insulator as is made of phosphosilicate glass is further deposited.The insulating film 4 is overlaid with a conductor layer for power source wirings or signal wirings as is made of evaporated aluminum.

In Figure 7, the MISFET, for example, D, is constructed of an n-type semiconductor region RG, as a drain region, an n-type semiconductor region RG2 as a source region, and an n-type polycrystalline silicon layer PSr as a gate electrode which is formed on a channel region sandwiched between the regions RG, and RG2.

In Figure 7, the drain region RG, of the MISFET D, is connected to a wiring layer ME, which is supplied with the power source voltage Vcc, while the source region of the MISFET E, is connected to a wiring layer ME2 which is held at the reference potential GND. The common semiconductor region RG2 which serves as the source region of the MISFET D, and the drain region of the MISFET E, is connnected through a conductor layer ME3 to one end part of the polycrystalline silicon layer PS, serving as the gate electrode of the MISFET D,.

The other end part of the gate electrode PS, of the MISFET D1 is connected through a conductor layer ME4 to one end part of a polycrystalline silicon layer as the gate electrode of the driving MISFET E2 which constitutes the inverter circuit of the succeeding stage. The MISFETs E2 and D2 have their respective drain region and source region constructed of a common semiconductor region. This common semiconductor region is connected through a conductor layer to a polycrystalline silicon layer as the gate electrode of the MISFET D2.

The other end part of the polycrystalline silicon layer as the gate electrode of the MISFET E2 is continuous to a polycrystalline silicon layer as the gate electrode of the MISFET E4 which constitutes the push-pull output circuit, as shown in the figure. Likewise, the other end part of the polycrystalline silicon layer as the gate electrode of the MISFET D2 is continuous to a polycrystalline silicon layer as the gate electrode of the MISFET E3.

In the circuit element structure of Figure 7, there is constructed a delay circuit which exploits the fact that the polycrystalline silicon layer is large as compared with the layer of a metal such as aluminium, and the fact that when the thin insulating film such as the gate insulating film is used as an insulating film, a comparatively great capacitance is formed between the polycrystalline silicon layer and the semiconductor substrate 1 or between the polycrystalline silicon layer and the source of the MISFET. That is, the delay circuit is substantially constructed of the polycrystalline silicon layer forming the gate electrode of the MISFET E2.

In accordance with the structure of Figure 7, the delay circuit is substantially constructed of the MISFET E2 as described above. In spite of the disposition of the delay circuit, therefore, the required area of the semiconductor substrate involves substantially no increase.

Figure 9 shows the plan pattern of circuit elements which constitute the second circuit BC in the circuit of Figure 4. The section of a part A A' in the MISFET E11 is substantially the same as Figure 8 referred to above.

The bootstrap capacitor C8 is constructed of an n-type semiconductor region which is made continuous to the drain region of the MISFET Eg, and a polycrystalline silicon layer which is formed thereon through a thin gate oxide film. The polycrystalline silicon layer serving as one electrode of the bootstrap capacitor is connected through a conductor layer to the gate electrodes of the MISFETs E8 and E10.

In the figure, an n-type polycrystalline silicon layer PS3 as the gate electrode of the MISFET D4 is directly coupled with an n-type polycrystalline silicon layer PS4 as a wiring which is extended on a field oxide film 2. This n-type polycrystalline silicon layer PS4 is directly coupled with one end of an n-type polycrystalline silicon layer PS8 as the gate electrode of the output MISFET E". The other end of the n-type polycrystalline silicon layer PS5 is coupled to an n-type polycrystalline silicon layer PS8 as the gate electrode of the MISFET E8 through a conductor layer ME5 made of evaporated aluminium.

According to the illustrated construction, the stray capacitor which is formed between the ntype polycrystalline silicon layer PS4 as the wiring and a semiconductor substrate 1 becomes a comparatively small capacitance because the field oxide film is made comparatively thick as described before. Accordingly, a time constant which is determined by the resistance of the ntype polycrystalline silicon layer PS4 itself and the stray capacitor becomes a comparatively small value.

In contrast, the stray capacitor which is formed between the n-type polycrystalline silicon layer PS8 as the gate electrode of the output MISFET E" and the semiconductor substrate 1 becomes a comparatively large capacitance because of the fact that the gate oxide film is thin and the fact that the output MISFET E" is made comparatively large in size as shown in the figure. Accordingly, a time constant which is determined by the resistance of the n-type polycrystalline silicon layer PS8 itself and the stray capacitor becomes a comparatively large value.

As a result, the delayed signal to be fed to the MISFET E8 is substantially formed by the gate electrode of the MISFET E".

Figure 10 is a circuit diagram showing another embodiment of the delay circuit. In this embodiment, two inverter circuits which are respectively made up of combinations of a depletion-mode MISFET D5 and an enhancementmode MISFET E,2, and MISFETs D8 and E,3 are connected in cascade. The number of the inverter circuits may well be an even number other than two, and the even number is intended to make an input IN and an output OUT inphase.

Figure 11 is a sectional view of still another embodiment of the delay circuit.

In this embodiment, an n-type polycrystalline silicon layer 3 which is used as a wiring is extended on a comparatively thin insulating film 2'. By way of example, the insulating film 2' is formed simultaneously with the gate insulating films of MISFETs. Since the insulating film 2' is made comparatively thin a comparatively great stray capacitance is formed between the polycrystalline silicon layer 3 and a semiconductor substrate 1 likewise to the gate electrode of the MISFET E". As a result, a delay circuit is formed of the resistance of the polycrystalline silicon layer 3 itself and the stray capacitance.

Figure 1 2 is a sectional view of the delay means in another embodiment. The section of the delay means of this embodiment is similar to that of a depletion-mode MISFET. More specifically, an n-type polycrystalline silicon layer 3 is extended on a thin insulating film 2'. In the surface of a p-type semiconductor substrate 1 underlying the insulating film 2', a depletion region RG,2 is formed. The region RG,2 is formed with n-type semiconductor regions RG,o and RG which are formed simultaneously with the drain region and source region of a MISFET. The depletion region RG,2 is maintained at earth potential of the circuitry through the semiconductor regions RGao and Rug1.

As a result, a delay circuit is substantially formed of the polycrystalline silicon layer 3.

The delay means of the embodiment shown in Figure 1 2 has an advantage as stated below.

In the delay means constructed of the gate electrodes of the enhancement-mode MISFETs as shown in Figures 7 to 9, the stray capacitance coupled to the gate electrode decreases with the increase of the signal level applied to the gate electrode, similarly to that of a typical MOS capacitor.

On the other hand, in the delay means shown in Figure 12, an electric field applied from the polycrystalline silicon layer 3 to the depletion region RG,2 is positive. Accordingly, any depletion layer is not induced in the surface of the depletion region RG,2 in spite of the increase of the signal level applied to the polycrystalline silicon layer 3.

Since no depletion layer is induced in the depletion region RG,2, the stray capacitance coupled to the polycrystalline silicon layer 3 is not changed. As a result, the delay characteristic of the delay means shown in Figure 12 is not affected by the signal level.

Figure 13 shows still another embodiment of the delay means. In this embodiment, a delay means is constructed of the resistance between the source and drain of a depletion-mode MISFET whose gate is connected to earth, and the capacitance between the resistance and earth.

Further, the delay circuit CR, of the push-pull circuit PC can also be constructed of an enhancement-mode MISFET E,4 and a capacitor C88 as shown in Figure 14.

In the circuits of Figures 11-13, the thin insulating film as is formed simultaneously with the gate insulating film of the MISFET is utilized for forming the capacitance. Accordingly, the circuits have the advantage that the delay circuit can be constructed with a remarkably small occupying area and that the delay circuit can be constructed without the increase of any special manufacturing step.

This invention can also employ delay circuits other than the foregoing delay circuits.

As set forth above, according to this invention, the drivability for a load can be enhanced, and the occupying area can be reduced.

Claims (20)

Claims

1. An electronic circuit device including: (a) a first node which is supplied with an input signal; (b) an inverter circuit which delivers an output signal inverted with respect to said input signal supplied to said first node; (c) delay means to deliver a delay signal delayed with respect to said input signal supplied to said first node; (d) an output node; (e) a first MISFET which has a drain-source path connected between a first terminal of a power source and said output node, and a gate electrode to be supplied with said output signal of said inverter circuit; and (f) a second MlSFETwhich has a drain-source path connected between said output node and a second terminal of said power source, and a gate electrode to be supplied with said delay signal.

2. An electronic circuit device according to Claim 1, wherein said delay means comprises a resistive element and a capacitive element, and said resistive element and said capacitive element are respectively formed of a gate electrode of a MISFET and a stray capacitance coupled to said gate electrode.

3. An electronic circuit device according to Claim 1, wherein said delay means comprises a polycrystalline silicon layer which is formed on a semiconductor substrate through a comparatively thin insulating film.

4. An electronic circuit device according to Claim 1, wherein said delay means comprises a semiconductor region of a second conductivity type which is formed on a semiconductor substrate of a first conductivity type and which is maintained at a potential of the second terminal of said power source, and a polycrystalline silicon layer which is formed on said semiconductor region through a comparatively thin insulating film.

5. An electronic circuit device according to Claim 1, wherein said delay means comprises a drain-source path of a depletion-mode MISFET.

6. An electronic circuit device according to Claim 5, wherein a gate electrode of said depletion-mode MISFET is maintained at a potential of the first terminal of said power source.

7. An electronic circuit device according to Claim 1, wherein said delay means comprises an even number of signal inverting means connected in cascade.

8. An electronic circuit device according to Claim 1, wherein said inverter circuit comprises a driving MISFET which has a drain electrode, a source electrode and a gate electrode to be supplied with said input signal, and a load MISFET which is coupled to said drain electrode of said driving MISFET, and wherein said delay means is constructed of a resistive element which is substantially formed of a gate electrode of said load MISFET, and a stray capacitance which is coupled to said gate electrode of said load MISFET.

9. An electronic circuit device including: (a) a first circuit which has a signal inverter circuit, a first output node to deliver a first signal, and a second output node to deliver a second signal of a level inverted with respect to said first signal; (b) a bootstrap circuit which includes first and second MISFETs with their drain electrodes and source electrodes connected in series between first and second power source terminals, and a bootstrap capacitor coupled between a gate electrode and said source electrode of said first MISFET; (c) coupling means to supply said first signal to said gate electrode of said first MISFET, and (d) delay means to supply said second signal to a gate electrode of said second MISFET with a predetermined delay time.

10. An electronic circuit device according to Claim 9, wherein said coupling means comprises a third MISFET whose drain electrode and source electrode are connected in series between said first output node and said gate electrode of said first MISFET.

11. An electronic circuit device according to Claim 10, wherein said third MISFET has its gate electrode supplied with a power source voltage.

1 2. An electronic circuit device according to Claim 10, wherein said delay means comprises a resistive element and a capacitive element, and said resistive element and said capacitive element are respectively formed of a gate electrode of a MISFET and a stray capacitance coupled to said gate electrode.

13. An electronic circuit device according to Claim 10, wherein said delay means comprises a polycrystalline silicon layer which is formed on a semiconductor substrate through a comparatively thin insulating film.

14. An electronic circuit device according to Claim 10, wherein said delay means comprises a semiconductor region of a second conductivity type which is formed on a semiconductor substrate of a first conductivity type and which is maintained at a potential of the second terminal of said power source, and a polycrystalline silicon layer which is formed on said semiconductor region through a comparatively thin insulating film.

1 5. An electronic circuit device according to Claim 10, wherein said delay means comprises a drain-source path of a depletion-mode MISFET.

1 6. An electronic circuit device according to Claim 1 5, wherein a gate electrode of said depletion-mode MISFET is maintained at a potential of the first terminal of the power source.

1 7. An electronic circuit device according to Claim 10, wherein said delay means comprises an even number of signal inverting means connected in cascade.

1 8. An electronic circuit device according to Claim 10, further including a push-pull output circuit which is comprising a fourth MISFET having a drain electrode and a source electrode connected between one of said pair of power source terminals and said third output node, and a fifth MISFET having a drain electrode and a source electrode connected between said third output node and the other of said pair of power source terminals, the gate electrodes of said first and fourth MISFETs being supplied with said first signal through said coupling means, and the gate electrode of said fifth MISFET being supplied with said second signal.

1 9. An electronic circuit device according to Claim 18, wherein said delay means comrises a resistive element and a stray capacitance which are substantially formed of said gate electrode of said fifth MISFET.

20. An electronic circuit device constructed and arranged to operate substantially as herein described with reference to and as illustrated in the accompanying drawings.