GB2095067A

GB2095067A - Digital filter arrangement

Info

Publication number: GB2095067A
Application number: GB8107765A
Authority: GB
Original assignee: Standard Telephone and Cables PLC
Current assignee: STC PLC
Priority date: 1981-03-12
Filing date: 1981-03-12
Publication date: 1982-09-22
Also published as: AU549472B2; AU8119182A; GB2095067B; ES510395A0; DE3208215A1; ES8302971A1; US4484299A; CH658560A5

Description

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SPECIFICATION Digital filter arrangement

This invention relates to a digital filtering arrangement and is particularly suited for use in a 5 high speed pulse density modulation to pulse code modulation translation equipment.

British Patent No. 1 436 878 discloses-a pulse density modulation (PDM) to pulse code modulation (PCM) translation arrangement 10 comprising a digital filter to which a PDM signal is applied and a logic means to which the output of the filter is applied, the logic means being arranged to select every mth group of n pulses in the digital filter output. Typically the translation 15 arrangement can be depicted schematically as shown in Fig. 1. A PDM signal, which is a continuous stream of binary pulses or bits is applied to a digital filter 10 which is designed to suppress, as fc.r as possible, high frequsncy noise. 20 The filtered signals are then applied to a sampling circuit 11 which effectively selects every mth group of n pulses. For example, consider a system in which the PDM rate is 8.064 Mb/s. After filtering this can be regarded as an arbitrary 25 stream of 14-bit words with a word rate of 8.064 Mw/s. If now every 504th 14-bit word is selected the output becomes a PCM signal of 16 Kw/s.

Such an arrangement is suitable for a speech channel of 0—4 KHz bandwidth. The basic rate 30 clock would not be expected to exceed a nominal 8 MHz. However, a channel of 56—112 KHz bandwidth as required for frequency division multiplex (FDM) analogue-to-digital (A/D) conversion, or 0—50 KHz for a possible music 35 A/D, would need a basic clock rate of about 56 MHz (i.e. this is the presently used 4 MHz for speech scaled up by a factor of 14) and there is a technology problem when working at this speed. In particular the power consumption of integrated 40 circuits becomes unacceptable.

The basic principle of a digital filter coupled with selective logic can be explained with reference to Fig. 2. An N-bit shift register 20 has N tap outputs, each tap output having an individual weighting 45 function X applied thereto. Thus the output of tap 1 is weighted by the function X,, that of tap 2 by X2 and so on. For example, if the weighting functions are generally increasing up to tap N/2 and then decreasing, the filter can have an 50 impulse response as indicated by the curve 21 in Fig. 2. The outputs of all the taps are summed in network 22. Now, if the delay between each tap is T equal to 1/fc, where fc is the basic input clock frequency, and the total length of the filter is N 55 taps, then the repetition period of the filter is fs = NXT. If the output of the filter is sampled at a frequency of fc/NT then the filter will receive a new set of data during each period and each bit will be uniquely weighted by only one of the respective 60 tap weights according to its position in the time sequence. However, if the sampling rate is . required to be four times fs each bit will be successively weighted by four separate weights during its progress through the filter. This weighting would normally occur at the prevailing basic clock frequency.

According to the present invention there is provided a digital filter arrangement for a serial pulse stream comprising a plurality of shift registers operating in parallel, means for distributing the pulses of the pulse stream into the shift registers sequentially and cyclically, means for reading in parallel pulses from selected positions in each shift register, addressable memory means for which combinations of the read-out shift register pulses form address words and to which said address words are applied, the memory means being arranged in the form of a multiplicity of storage locations each having stored there in a digital word, means for reading in a non-volatile manner the contents of each storage location when a combination of read-out shift register pulses form an address word for that location, and logic means for serially outputting said read-out storage location contents.

In a preferred embodiment of the invention and memory means comprises a plurality of separate memories, one for each shift register, each separate memory having a number of storage locations addressable by the address words from that shift register only, and the logic means comprises means for adding the read-out contents from all the separate memories once for each input cycle of the serial output.

The above and other features of the invention will become more apparent from the following description of an embodiment of the invention taken in conjunction with Fig. 3 of the accompanying drawings, which illustrates a digital filter arrangement according to the invention.

In the arrangement shown in Fig. 3 an input PDM stream is entered serially into an 8-bit shift register 30. After each consecutive non-overlapping group of 8 bits has been entered the contents of shift register 30 are transferred in parallel to 8 further shift registers 31A—31 H, one bit to each of the further shift registers. The 8 further shift registers are each operated at a clock rate which is -§-th of the PDM input clockrate. Selected stages of each of the further shift registers are read out in parallel to form address words for a set of read-only memories (ROM) 32a—32H. In the example shown, four equally spaced bits A,—A4, B,—B4. Each ROM carries pre-stored weighted outputs which are read-out in accordance with the address words received from the shift registers. Thus each input bit of the PCM stream will pass through the filter in the period equal to p times 8/fc, where p is the number of stages in the shift register, and during this period it will be sampled and weighted four times. This agrees generally with the previously described requirements. Each ROM is also addressed by two bits from a common 2-bit binary counter 33. Hence each ROM contains sixty-four digital words which represent all possible combinations from each of the respective 8 shift registers 31a—31h.

The outputs A', B' H' of the separate ROM's

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are added in adders 34—37 and then in adders 38—39 and lastly in adder 40. The output of adder 40 is fed into a latch 42 via adder 41. Adder 41 and latch 42 together make an accumulator 5 from which a parallel transfer is made into a buffer 43. The contents of buffer 43 are read-out serially at 4 times the repetition period fs of the filter to provide the PCM serial bit stream.

It is to be noted that the detail arrangement of 10 Fig. 3 is by way of example only. Thus the method of distribution of the incoming PCM signals need not necessarily be by a shift register. The 8 shift registers 31A—31H can be scanned sequentially and the incoming bits be read, one at a time, into 15 the relevant shift register. Also the particular arrangement of memories and the method of addressing them can be different. Having one memory per shift register as shown is convenient but other arrangements are possible. For example, 20 at one extreme a single large memory could be envisaged, with all the selected bits in the shift registers being combined to form a single address word. This arrangement would have the advantage that no adders would be required but it 25 would have disadvantages in the size of and operation of the ROM. Other various combinations of shift registers, tap and ROM connections can be used. Another example is where the ROM's may be used to store only the weights representing the 30 impulse response of the filter, when it would then be necessary to use multipliers in conjunction with each shift register tap and add the results separately. This would need more adders besides introducing multipliers, but the ROM's could be 35 reduced in size. Yet again, each address word could be formed from tape from more than one shift register. Thus the address words in Fig. 3 could be, for example, A^EgG,,, B1D2F3H4, A2C3E4GV and so on, or other combinations. 40 Finally, although the memories in Fig. 3 have been referred to as read-only-memories (ROM) they could be, for example, random-access-memories (RAM) the contents of which can be readily altered when required, e.g. on a day-to-day basis.

Claims

45 CLAIMS

1. A digital filter arrangement for a serial pulse stream comprising a plurality of shift registers operating in parallel, means for distributing the pulses of the pulse stream into the shift registers 50 sequentially and cyclically, means for reading out in parallel pulses from selected positions in each shift register, addressable memory means for which combinations of the read-out shift register pulses form address words and to which said 5ot address words are applied, the memory means being arranged in the form of a multiplicity of storage locations each having stored therein a digital word, means for reading in a non-volatile manner the contents of each storage location 60 when a combination of read-out shift register pulses form an address word for that location, and logic means for serially outputting said read-out storage location contents.

2. An arrangement according to claim 1

65 wherein the memory means comprises a plurality of separate memories, one for each shift register, each separate memory having a number of storage locations addressable by the address words from that shift register only, and the logic 70 means comprises means for adding the read-out contents from all the separate memories once for each input cycle of the serial output.

3. An arrangement according to claim 2 wherein each separate memory means is

75 constituted by a read-only memory (ROM).

4. An arrangement according to claim 1 or 2 wherein the memory means is constituted by a random access memory or memories (RAM).

5. An arrangement according to any preceding 80 claim wherein the pulses read-out from the shift registers are read from corresponding positions in each register.

6. An arrangement according to any preceding claim wherein the means for distributing the

85 pulses of the pulse stream into the shift registers comprises an input shift register or registers having one pulse position for each of the plurality of shift registers, the contents of the input shift registers being transferred in parallel to the 90 plurality of shift registers after each consecutive non over-lapping group of input pulses of the pulse stream has been entered into the input shift registers.

7. An arrangement according to any preceding 95 claim wherein the pulses in the plurality of shift registers are shifted therein at a clock rate which is 1/n times the clock rate of the input pulse stream, where n is the number of the plurality of shift registers.

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8. An arrangement according to any preceding claim wherein the pulses read-out from the plurality of shift registers are read from equally spaced selected positions in each register.

9. An arrangement according to claim 8 105 wherein said selected positions include the first and last positions of each shift register.

10. An arrangement according to claim 1 wherein the memory means comprises a single read-only memory having a number of storage

110 locations each addressable by all the pulses from the selected positions combined to form a single address word.

11. An arrangement according to any preceding claim wherein the addressable memory means

115 contains data constituting only the weighting information representing the impulse response of the filter, the arrangement including multipliers in conjunction with each shift register selected position and means for adding the results 120 separately to form the serial output.

12. A digital filter arrangement substantially as described with reference to Fig. 3 of the accompanying drawings.

13. A method of filtering a serial digital pulse 125 stream comprising distributing the pulses of the stream sequentially and cyclically with a plurality of shift registers operating in parallel, reading out in parallel pulses from selected positions in each

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shift register, applying word-forming combinations of the read-out shift register pulses to respective locations in an addressable memory, reading in a memorable manner the contents of each storage 5 location when a combination of read-out shifts register pulses from an address word for that location, and serially outputting said read-out storage location contents.

14. A method of filtering a serial digital pulse 10 stream substantially as hereinbefore described.

Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1982. Published by the Patent Office, 25 Southampton Buildings, London, WC2A 1AY, from which copies may be obtained.