GB2090057A - Test structures for semiconductor integrated circuits - Google Patents
Test structures for semiconductor integrated circuits Download PDFInfo
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- GB2090057A GB2090057A GB8135810A GB8135810A GB2090057A GB 2090057 A GB2090057 A GB 2090057A GB 8135810 A GB8135810 A GB 8135810A GB 8135810 A GB8135810 A GB 8135810A GB 2090057 A GB2090057 A GB 2090057A
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- integrated circuit
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- semiconductor
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- 239000004065 semiconductor Substances 0.000 title claims description 54
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 claims abstract description 23
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 3
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 3
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 3
- 229920005591 polysilicon Polymers 0.000 claims abstract 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 52
- 239000000758 substrate Substances 0.000 claims description 42
- 229910052681 coesite Inorganic materials 0.000 claims description 26
- 229910052906 cristobalite Inorganic materials 0.000 claims description 26
- 239000000377 silicon dioxide Substances 0.000 claims description 26
- 235000012239 silicon dioxide Nutrition 0.000 claims description 26
- 229910052682 stishovite Inorganic materials 0.000 claims description 26
- 229910052905 tridymite Inorganic materials 0.000 claims description 26
- 239000012535 impurity Substances 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 239000011733 molybdenum Substances 0.000 claims 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims 1
- 239000010936 titanium Substances 0.000 claims 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 1
- 239000010937 tungsten Substances 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000004411 aluminium Substances 0.000 abstract 1
- 239000003779 heat-resistant material Substances 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 10
- 229910052698 phosphorus Inorganic materials 0.000 description 10
- 239000011574 phosphorus Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 7
- 235000012431 wafers Nutrition 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/316—Testing of analog circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
MIS structures for use in testing during the manufacture of an IC are provided with gate source and drain electrodes (27, 25, 26) of heat resistant material (e.g. polysilicon, Mo, W, Ti, or Ta). This permits tests to be made at an early stage in the production before the formation of aluminium extension electrodes for the other devices in the IC. The test structures preferably use polysilicon layers formed at the same time as gate electrodes for MISFETs forming a logic circuit in the IC. <IMAGE>
Description
SPECIFICATION
Semiconductor integrated circuit device
Background of the Invention
This invention relates to a semiconductor integrated circuit device (hereinafter referred to as an "IC") consisting of metal insulator semiconductor field effect transistors (hereinafter referred to an "MISFETs") as its basic constituents.
In a semiconductor IC of this kind, MISFETs having the same structure as that of MISFETs forming a logic circuit are formed within the same chip in order to inspect the electrical characteristics of the MISFETs forming the logic circuit. If aluminum (Al) is used for electrodes for the source and drain diffused regions, however, the MISFETfor measuring the characteristics can be formed only after passing through the various fabrication steps such as oxidation, diffusion, vapour growth, vapor depostion, annealing, and so forth. In other words, the MISFETs forming the logic circuit can be inspected only after substantially all of the fabrication steps of the wafer treatment are completed.Hence, the measurement of the characteristics is very timeconsuming and feedback of the data from the measurement of the characteristics to fabricating conditions such as ion implantation, diffusion and the like is retarded. In the interim, defective devices below the quality requirement level are likely to get mixed with approved devices before the final fabrication step. Incidentally, the term "logic circuit" herein denotes a circuit that executes a logical operation, memory, transmission, conversion and the like by use of logical "1" and "0".
Summary of the Invention
One aspect of the present invention provides a semiconductor integrated circuit device comprising: a semiconductor substrate; a plurality of MISFETs forming a logic circuit, disposed in or on part of said semiconductor substrate; and one or more MISFETs for measuring characteristics, disposed in or on another portion of said semiconductor substrate, having the gate, source and drain electrodes thereof made of a heatresistant, electrically conductive material.
A second aspect of the invention provides a method of fabricating such a semiconductor integrated circuit device.
Brief Description of the Drawings
Figure 1 shows the layout pattern of a MIS IC formed in a silicon wafer in accordance with the present invention;
Figure 2 is a sectional view of a MISFET forming a logic circuit of the MIS IC shown in
Figure 1;
Figure 3 is a plan view of a MISFET for measuring characteristics for the MIS IC shown in
Figure 1;
Figure 4 is a sectional view of the MISFET of
Figure 3 for measuring characteristics, taken along
line lV-IV'; and
Figures 5A through 51 are sectional views,
showing the fabrication steps of the MISFET for
forming the logic circuit of the MOS IC shown in
Figure 1 and the MISFET for measuring
characteristics
Description of the Preferred Embodiments
Hereinafter, preferred embodiments of the
present invention will be described by referring to
Figures 1 through 51.
Figure 1 shows the layout pattern of an MIS iC
formed inside a semiconductor wafer (hereinafter
referred to as "silicon wafer"). As shown, a
plurality of IC regions are diposed inside zones
that are divided by scribe lines 2 within the wafer
1. The same kind of IC is to be formed inside each
of the plurality of IC regions. (However, different Cs may also be formed.)
Figure 1 depicts one of these IC regions. In this
IC region, a logic circuit consisting of a MIS, such
as a CPG (clock pulse generator) 3, an ALU
(arithmetic logic unit) 4, a RAM (random access
memory) 5, a register 6, a ROM (read-only
memory) 7 and the like, and MISFETs 8 for
measuring the characteristics are formed at
peripheral portions of each logic circuit.Though
the MISFETs 8 are not connected electrically to
the logic circuit, their fabrication steps, such as ion
implantation or source-drain diffusion or the like,
are effected simultaneously with those bf the
MISFETs of the logic circuit. Hence, the MISFETs 8
can be formed as depletion types, the
enhancement types, and the like.
Figure 2 is a sectional view of a MISFET that functions as a logic circuit. Nt source region 18
and drain region 19 are formed on a P siiicon
substate 10. If boron is shallowly doped onto the
surface of the substate 10 by an ion implantation
process before these source and drain regions 18,
19 are formed an enhancement type FET is
obtained. If phosphorus is doped by the ion implantation process in succession to the boron
doping, depletion type FET is obtained.
Incidentally, reference numeral 11 represents a
thick Six, film formed by LOCOS (local oxidation
of silicon) techniques; 12 is a gate oxide film; 1 3 is
a polycrystalline silicon gate (hereinafter referred
to as a "poly-Si gate"); 14 is a phosphosilicate
glass film; 1 5 is an Al wiring for the source region;
16 is an Al wiring for the drain region; and 17 is an
Al wiring for the gate.
Generally, a P region is formed as a channel
stopper below the field Six, film 11 , but it iS--.not shown in Figure 2. Figure 3 is a plan view showing
the MISFET 8 shown in Figure 1 for measuring the
characteristics. As shown in Figure 3,
polycrystalline silicon layers (hereinafter referred
to as "poly-Si layers") are each connected at one
end as extension electrodes 25, 26 to source and
drain regions 23 and 24, respectively. The other
end of each of the extension electrods 25 and 26
serves as a pad 28, 29. One end of the poly-Si
gate 27 also serves as a pad 30. These pads 28,
29, 30 are at positions the measuring needles are to be placed.
Figure 4 is a sectional view of the MISFET for measuring the characteristics, taken along line IV-IV' of Figure 3. As shown, in the MISFET 8 for measuring the characteristics, one end of the poly
Si layer 25 is directly connected to the source region 23 while one end of the poly-Si layer 26 is connected directly to the drain region 24. The poly-Si layer 25 thus connected to the source region 23 extends over the field SiO2 film 11. The poly-Si layer 26 connected to the drain region 24 also extends over the field SiO2 film 11.
In the abovementioned MISFET 8 for measuring the characteristics, during the patterning step of the poly-Si gate 27, the poly-Si layers 25 and 26 as the extension electrodes for the respective regions are deposited and patterned on the source and drain regions as well as on the field SiO2 film 11, and the pads 28, 29 of the extension electrodes for the source and drain regions and the pad 30 for the poly-Si gate 27 are also patterned. Accordingly, unlike the FET shown in Figure 2, the extension electrodes and the pads of this FET 8 for measuring the characteristic are all formed by poly-Si layers.
Phosphorus is thermally diffused through each through-hole 31,32 formed by patterning the poly-Si layer 25, 26 and at the same time, phosphorus is doped from each poly-Si layer 25, 26 into the P semiconductor substrate 10, thereby forming the N+ source and drain regions 23, 24 shown in Figure 4. At this stage, the source and drain regions 18 and 19 of the MISFET forming the logic circuit are simultaneously formed by diffusion.
The MISFET 8 can measure the characteristics of the MISFET forming the logic circuit immediately after the formation of the source and drain regions 23, 24 shown in Figure 4.
Namely, in the state depicted in Figure 4, diode needles are placed on the three terminals or pads 28, 29 and 30 to make a probing inspection. In this case, the threshold voltage of the 1D5 is measured by changing the gate voltage while applying a predetermined voltage across the source and drain. If a threshold voltage within a desired range is thus obtained, it is judged that the aforementioned ion implantation and diffusion conditions are normal and are in agreement with the conditions requred for normal operation of the MlSFETforming the logic circuit. If, on the contrary, the threshold voltage of the MISFET 8 is found to have deviated, the fabricating conditions must be adjusted to change, especially, the ion implantation condition (such as the quantity of ions implanted).This change of the conditions can be carried out easily and accurately in accordance with the magnitude of the threshold voltage of the
MISFET 8. Thus, the logic MISFET can be produced with a high yield under the correct production conditions by changing the ion implantation condition for fresh wafers immediately after the measurement of the characteristics of the MISFET 8. This MISFET 8 may also be used to re-inspect the characteristics of the M ISFET for the logic circuit after its fabrication has been completed. For this purpose, it is advisable to open a window in the passivation film over the MISFET 8.
Next, the method of fabricating the MISFET for forming the logic circuit and the MISFEI for measuring the characteristics, shown in Figures 1 through 4 on the same substrate, will be described with reference to Figures 5A through 51.
First, as shown in Figure 5A, an SiO2 film 40 about 800A thick is formed on one surface of the
P semiconductor substrate 10 (such as a silicon substrate). Next, an Si3N4 film 41 is selectively formed on this Six, film 40 as shown in Figure 5B, and using this Si3N4fiIm 41 as a mask an impurity such as born is doped into the surface of the P semiconductor substrate below the SiO2 film 40 by the ion implantation process. A P region 42 is selectively formed by this doping. Next, the P semiconductor substrate 10 is heated at about 1,000 C. for several hours with the Si N film 41 as a mask to selectively form a thick field Six, film 11 on the surface of the substrate 10. The field
SiO2 film 11 is formed to selectively encompass the surface of the P substrate 10.The surfaces of the substrate encompassed by the field SiO2 film
11 are represented by reference numerals 55 and 56. The Si N film 41 is then removed by etching.
To adjust the threshold voltage, boron and phosphorus impurities are selectively doped into the semiconductor substrate below the oxide film 40 by ion implantation. Subsequently, throughholes 43, 44 are selectively formed on the SiO2 film 40 on the substrate surface encompassed by the field SiO2 film 11.
A poly-Si layer 45 doped with phosphorus impurity is then formed on the Six, film 40 and the field SiO2 film 11 as shown in Figure 5E. Next,
as shown in Figure 5F, the poly-Si layer 45 and the SiO2 film 40 beneath it are selectively removed by etching. On the substrate surface 55 encompassed by the field SiO2 film 11 are then formed a gate SiO2 film 22, a gate poly-Si layer 27 positioned on the film 22 and poly-Si layers 25, 26 placed on the field S~ 2 film 11 and having one
end each brought into direct contact with the substrate surface 55. The other end of each of the
poly-Si layers 25, 26 has a pad 28, 29 as shown
In Figure 3. A gate SiO2 film 12 and a gate poly-Si
layer 13 placed on the film 12 are then formed on the substrate surface 56.
Next, as depicted in Figure 5G, a phosphorus
impurity is deposited on the exposed substrate surfaces 55 56 and it is heated to about 1 ,0000C.
for about 10 minutes, thereby diffusing the
phosphorus impurity into the substrate surface 55.
In this case, the phosphorus impurity is not doped
into the substrate surface 55 below the gate SiO2 film 22 and into the substrate surface 56 below the gate SiO2 film 12 because the gate poly-Si
layer 27 serves as a mask for the gate Six, film 22
below it, and the gate poly-Si layer 13 serves as a
mask for the gate SiO2 film 12 below it. In this
manner, N+ source and drain regions 23, 24 are
formed on the exposed substrate surface 55, self aligned by the gate poly-Si layer 27 while Nt source and drain regions 1 8, 19 self-aligned by the gate poly-Si layer 13 are formed on the exposed substrate surface 56, respectively.
During the abovementioned diffusion of the phosphorus impurity, the impurity diffuses from poly-Si layers 25, 26 into the substrate surface, thereby forming N+ regions connected to the abovementioned source and drain regions 23, 24.
Inside the first region encompassed by the thick field SiO2 film 11, there is thus formed the MISFET 8 for measuring the characteristics, consisting of the gate poly-Si layer 27, the source and drain regions 23, 24, the poly-Si layer 25 and the poly-Si layer 26. inside the second region encompassed by the field Six, film 11, on the other hand, there is formed the MISFET for forming the logic circuit that consists of the gate poly-Si layer 13 and the source and drain regions 18,19.
Next, as depicted in Figure 5H, a phosphosilicate glass film (hereinafter referred to as a "PGS film") 14 is deposited as a protective film on all of the poly-Si layers 27, 13, the poly-Si layers 25, 26, the field SiO2 film 11 and the source and drain regions. The PSG film 14 on the source and drain regions 1 8, 1 9 of the MISFET for forming the logic circuit is selectively removed by etching and contact-forming holes (hereinafter referred to as the "contact holes") 46, 47 are wormed. As shown in Figure SI, the aluminum (Al) is evaporated so as to bury at least the contact holes 46, 47 and is patterned into a predetermined size and shape by photoresist techniques. Thus, the source and drain electrodes 1 5, 1 6 of the MISFET for forming the logic circuit are formed.
The MISFET 8 for measuring the characteristics is used at the intermediate stage of fabrication of the MISFET before the fabrication is completed, as described above. If some characteristics are found defective, the subsequent fabrication steps are terminated and the ion implantation step or the like in the preceding stages is adjusted to obtain the predetermined fabricating conditions.
Accordingly the characteristics can be checked at an earlier stage and feeding of defective devices to later fabrication steps can therefore be prevented.
Hence, the yield of the logic circuit production can be improved to a marked extend and the work time can also be shortened.
Additionally, in Figure 4, the contact holes for the source and drain regions 23, 24 may contain only the poly-Si layers 25, 26, respectively. For this reason, the area of the source and drain regions can be reduced and the occupation area of the MISFET 8 for measuring the characteristics, which is to be left as an unnecessary portion after completion of the logic circuit, can be reduced.
The present invention is not restricted to the abovementioned embodiment, in particular. For instance, the object of the invention can also be accomplished by the following modifications.
In the structure shown in Figure 2, the MISFET for forming the logic circuit may have an Al structure, for example.
It is only possible to employ a direct contact system in which the poly-Si layer shown in Figure 4 is used as a wiring electrode
In place of the poly-Si layers 25, 26 of the
MISFET for measuring the characteristics, it is also possible to form the extension electrodes from a layer of other materials which, like the poly-Si, are resistant to the temperature (diffusion temperature) at the time of forming the source and drain regions and are electrically conductive.
Specific examples of such materials are metals with a high melting point of 1 ,0000C. or above, such as Mo, W, Ti, Ta or the like. The extension electrodes are preferably used at an intermediate step during fabrication of the MISFET, so it is an essential requirement that the material is heatresistant and electrically conductive.
Furthermore, the semiconductivity types of the aforementioned semiconductor regions may of course be changed. Beside the fabrication method shown in Figure 5A through SI, the object of the invention can also be accomplished by the following method.
(1) In Figure 5C, after the thick field SiO2 film 11 is
formed, the SiO2 film 40 on the substrate
surfaces 55 and 56 encompassed by the field
SiO2 film 11 is removed and a fresh SiO2 film
may be formed on the substate surfaces 55,
56.
(2) In Figures 5F and 5G, after the poly-Si layer 45
is selectively removed, the Six, film 40 below
the poly-Si layer 45 is left unremoved. The
source regions 23, 1 8 and the drain regions 24, 1 9 may then be formed on the substrate
surfaces 55, 56 by doping the phosphorus
impurity into them from above the Six, film 40
by the ion implantation process.
(3) In Figure 5H, the passivation film may be an
undoped SiO2 film formed by the chemical
vapor deposition process (CVD).
Claims (18)
1. A semiconuctor integrated circuit device comprising: a semiconductor substrate; a plurality of MISFETs forming a logic circuit, disposed in or on a part of said semiconductor substrate; and one or more MíSFETs for measuring characteristics, disposed in or on another portion of said semiconductor substate, having the gate, source and drain electrodes thereof made of a heatresistant, electrically conductive material.
2. A semiconductor integrated circuit device as defined in claim 1 wherein said plurality of
MISFETs for forming the logic circuit are formed in a central region of said semiconductor substrate and said plurality of MISFETs for measuring the characteristics are formed at the peripheral portions of said semiconductor substrate.
3. A semiconductor integrated circuit device as defined in claim 1 or claim 2 wherein said heatresistant, electrically conductive material is a poly silicon layer.
4. A semiconductor integrated circuit device as defined in claim 1 or claim 2 wherein said heatresistant, electrically conductive material is molybdenum.
5. A semiconductor integrated circuit device as defined in claim 1 or claim 2 wherein said heatresistant, electrically conductive material is tungsten.
6. A semiconductor integrated circuit device as defined in claim 1 or claim 2 wherein said heatresistant, electrically conductive material is titanium.
7. A semiconductor integrated circuit device as defined in claim 1 or claim 2 wherein said heatresistant, electrically conductive material is tantalum.
8. A semiconductor integrated circuit device as defined in any one of the preceding claims, comprising a thick insulating film so formed on one surface of said semiconductor substrate as to encompass at least first and second areas of said surface, the MISFETs for measuring characteristics being formed on said surface in the first area encompassed by said thick insulating film, and the MISFETs forming the logic circuit being formed on said surface in the second area encompassed by said thick insulating fil.
9. A semiconductor integrated circuit device as defined in claim 8, wherein said semiconductor substate consists of silicon and said thick insulating film consists of an SiO2 film.
10. A semiconductor integrated circuit device comprising: a semiconductor substrate of a first semiconductivity type; a thick insulating film selectively formed on one surface of the substrate in such a manner as to divide said semiconductor substrate into at least first and second semiconductor regions and to encompass said first and second semiconductor regions;MISFETs for measuring characteristics, each consisting of: a first gate electrode consisting of a poly-silicon layer selectively formed on said first semiconductor region encompassed by said thick insulating film; first source and drain regions of a second semiconductivity type, opposite said first semiconductivity type, self-aligned by said first gate electrode: and first and second poly-silicon layers directly connected to said first source and drain regions, respectively; and MISFETs for forming a logic circuit, each consisting of: a second gate electrode consisting of a polysilicon layer selectively formed on said second semiconductor region encompassed by said thick insulating film; second source and drain regions of a second semiconductivity type opposite said first semiconductivity type, self-aligned by said second gate electrode; and respective aluminum layers connected to said second source and drain regions.
11. A semiconductor integrated circuit device as defined in claim 10 wherein said semiconductor substrate has P-type semiconductivity while said first source and drain regions and said second source and drain regions
have N-type semiconductivity.
12. A semiconductor integrated circuit device
as defined in claim 10 or claim 11 wherein said semiconductor substrate consists of silicon and said thick insulating film consists of an SiO2 film.
13. A semiconductor integrated circuit device
of the type in which a plurality of MISFETs are
disposed on one semiconductor substrate,
wherein at least one of said plurality of MISFETs is
disposed as a MISFET for measuring the
characteristics and the gate, source and drain
electrodes of said MISFET for measuring the
characteristics are made of a heat-resistant,
electrically conductive layer.
14. A method of fabricating a semiconductor
integrated circuit device comprising the steps of:
preparing a semiconductor substrate of a first
semiconductivity type; forming a thick insulating film on the surface of said semiconductor
substrate in such a manner as to define first and second surface regions encompassed by said insulating film; forming a layer of a heat-resistant, electrically conductive material on said first and second surface regions and on said thick insulating film; selectively removing said layer of said heat
resistant, electrically conductive material in such a
manner as to define a first gate electrode and an extension electrode having one end thereof
connected to said first surface region and the other extending up to said thick insulating film, and a second gate electrode on said second surface region; forming first source and drain regions of a second semiconductivity type
opposite said first semiconductivity type on said
first surface region and second source and drain
regions of said second semiconductivity type on said second surface region, respectively; forming a
protective film on said first source and drain
regions, said first gate electrode said second
source and drain regions, said second gate
electrode and said thick insulating film; selectively
removing said protective film on said second
source and drain regions to expose the surfaces of
said second source and drain regions; and forming
metal electrodes to be connected to the surfaces
of said second source and drain regions.
IS. A method of fabricating a semiconductor
integrated circuit device as defined in claim 14
wherein said thick insulating film encompassing
said first and second surface regions is effected by
heating said semiconductor substrate.
16. A method of fabricating a semiconductor
integrated circuit device as defined in claim 14 or
claim 15 wherein said first source and drain
regions and said second source and drain regions
are formed by depositing first an impurity of said
second semiconductivity type and then heating
said substrate in order to diffuse said impurity into
said substrate.
17. A method of fabricating a semiconductor
integrated circuit device as defined in any one of
claims 14, 1 5 and 1 6, including a step of testing a
transistor formed by the first gate electrode and
first source and drain regions by making
connections to the electrodes defined by the layer
of the heat-resistant, electrically conductive
material.
18. A semiconductor intergrated circuit device
substantially as any described with reference to
the accompanying drawings.
1 9. A method of fabricating a semiconductor integrated circuit device substantially as any described herein with reference to the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55169553A JPS5793542A (en) | 1980-12-03 | 1980-12-03 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2090057A true GB2090057A (en) | 1982-06-30 |
Family
ID=15888596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8135810A Withdrawn GB2090057A (en) | 1980-12-03 | 1981-11-27 | Test structures for semiconductor integrated circuits |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5793542A (en) |
| DE (1) | DE3146777A1 (en) |
| FR (1) | FR2496989A1 (en) |
| GB (1) | GB2090057A (en) |
| IT (1) | IT1169283B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4440799A (en) * | 1982-10-22 | 1984-04-03 | Rca Corporation | Monitor for impurity levels in aluminum deposition |
| US4567430A (en) * | 1981-09-08 | 1986-01-28 | Recognition Equipment Incorporated | Semiconductor device for automation of integrated photoarray characterization |
| FR2585864A1 (en) * | 1985-08-02 | 1987-02-06 | Gen Electric | METHOD AND STRUCTURE FOR THIN - FILM TRANSISTOR MATRIX ADDRESSED CRYSTAL VISUALIZATION DEVICES. |
| FR2585879A1 (en) * | 1985-08-02 | 1987-02-06 | Gen Electric | TITANIUM DEPOSITION AND CURING OF THE GRID ELECTRODE FOR USE IN THIN-FILM FIELD-EFFECT INVERTED TRANSISTORS |
| FR2585863A1 (en) * | 1985-08-02 | 1987-02-06 | Gen Electric | METHOD AND STRUCTURE FOR THIN FILM ADDRESSED LIQUID CRYSTAL VISUALIZATION DEVICES AND THIN FILM TRANSISTORS. |
| US4855806A (en) * | 1985-08-02 | 1989-08-08 | General Electric Company | Thin film transistor with aluminum contacts and nonaluminum metallization |
| US5457399A (en) * | 1992-12-14 | 1995-10-10 | Hughes Aircraft Company | Microwave monolithic integrated circuit fabrication, test method and test probes |
| EP0685881A1 (en) * | 1994-05-31 | 1995-12-06 | AT&T Corp. | Linewidth control apparatus and method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6148929A (en) * | 1984-08-16 | 1986-03-10 | Matsushita Electronics Corp | Manufacture of insulating gate type semiconductor device |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3697318A (en) * | 1967-05-23 | 1972-10-10 | Ibm | Monolithic integrated structure including fabrication thereof |
| JPS4831516B1 (en) * | 1969-10-17 | 1973-09-29 | ||
| US3774088A (en) * | 1972-12-29 | 1973-11-20 | Ibm | An integrated circuit test transistor structure and method of fabricating the same |
| FR2280203A1 (en) * | 1974-07-26 | 1976-02-20 | Thomson Csf | FIELD-EFFECT TRANSISTOR THRESHOLD TENSION ADJUSTMENT METHOD |
| US4016587A (en) * | 1974-12-03 | 1977-04-05 | International Business Machines Corporation | Raised source and drain IGFET device and method |
| CA1074009A (en) * | 1975-03-03 | 1980-03-18 | Robert W. Brodersen | Charge coupled device memory |
| US4197632A (en) * | 1975-12-05 | 1980-04-15 | Nippon Electric Co., Ltd. | Semiconductor device |
| EP0003413A3 (en) * | 1978-01-19 | 1979-08-22 | Sperry Corporation | Improvements relating to semiconductor memories |
| JPS5530846A (en) * | 1978-08-28 | 1980-03-04 | Hitachi Ltd | Method for manufacturing fixed memory |
| DE2947311C2 (en) * | 1978-11-24 | 1982-04-01 | Hitachi, Ltd., Tokyo | Integrated semiconductor circuit |
-
1980
- 1980-12-03 JP JP55169553A patent/JPS5793542A/en active Pending
-
1981
- 1981-11-25 DE DE19813146777 patent/DE3146777A1/en not_active Withdrawn
- 1981-11-27 GB GB8135810A patent/GB2090057A/en not_active Withdrawn
- 1981-11-30 FR FR8122382A patent/FR2496989A1/en active Pending
- 1981-12-02 IT IT25408/81A patent/IT1169283B/en active
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4567430A (en) * | 1981-09-08 | 1986-01-28 | Recognition Equipment Incorporated | Semiconductor device for automation of integrated photoarray characterization |
| US4440799A (en) * | 1982-10-22 | 1984-04-03 | Rca Corporation | Monitor for impurity levels in aluminum deposition |
| EP0211401A2 (en) * | 1985-08-02 | 1987-02-25 | General Electric Company | N+ Amorphous silicon thin film transistors for matrix addressed liquid crystal displays |
| FR2585879A1 (en) * | 1985-08-02 | 1987-02-06 | Gen Electric | TITANIUM DEPOSITION AND CURING OF THE GRID ELECTRODE FOR USE IN THIN-FILM FIELD-EFFECT INVERTED TRANSISTORS |
| FR2585863A1 (en) * | 1985-08-02 | 1987-02-06 | Gen Electric | METHOD AND STRUCTURE FOR THIN FILM ADDRESSED LIQUID CRYSTAL VISUALIZATION DEVICES AND THIN FILM TRANSISTORS. |
| EP0211402A2 (en) * | 1985-08-02 | 1987-02-25 | General Electric Company | Process and structure for thin film transistor matrix addressed liquid crystal displays |
| FR2585864A1 (en) * | 1985-08-02 | 1987-02-06 | Gen Electric | METHOD AND STRUCTURE FOR THIN - FILM TRANSISTOR MATRIX ADDRESSED CRYSTAL VISUALIZATION DEVICES. |
| EP0211370A2 (en) * | 1985-08-02 | 1987-02-25 | General Electric Company | Deposition and hardening of titanium gate electrode material for use in inverted thin film field effect transistors |
| EP0211402A3 (en) * | 1985-08-02 | 1988-05-04 | General Electric Company | Process and structure for thin film transistor matrix addressed liquid crystal displays |
| EP0211401A3 (en) * | 1985-08-02 | 1988-05-18 | General Electric Company | N+ amorphous silicon thin film transistors for matrix addressed liquid crystal displays |
| EP0211370A3 (en) * | 1985-08-02 | 1988-05-18 | General Electric Company | Deposition and hardening of titanium gate electrode material for use in inverted thin film field effect transistors |
| US4855806A (en) * | 1985-08-02 | 1989-08-08 | General Electric Company | Thin film transistor with aluminum contacts and nonaluminum metallization |
| US5457399A (en) * | 1992-12-14 | 1995-10-10 | Hughes Aircraft Company | Microwave monolithic integrated circuit fabrication, test method and test probes |
| EP0685881A1 (en) * | 1994-05-31 | 1995-12-06 | AT&T Corp. | Linewidth control apparatus and method |
| US5780316A (en) * | 1994-05-31 | 1998-07-14 | Lucent Technologies Inc. | Linewidth control apparatus and method |
Also Published As
| Publication number | Publication date |
|---|---|
| IT8125408A0 (en) | 1981-12-02 |
| JPS5793542A (en) | 1982-06-10 |
| DE3146777A1 (en) | 1982-09-16 |
| FR2496989A1 (en) | 1982-06-25 |
| IT1169283B (en) | 1987-05-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |