GB2089122A - Semiconductor integrated circuit interconnections - Google Patents
Semiconductor integrated circuit interconnections Download PDFInfo
- Publication number
- GB2089122A GB2089122A GB813171A GB8131171A GB2089122A GB 2089122 A GB2089122 A GB 2089122A GB 813171 A GB813171 A GB 813171A GB 8131171 A GB8131171 A GB 8131171A GB 2089122 A GB2089122 A GB 2089122A
- Authority
- GB
- United Kingdom
- Prior art keywords
- signal line
- signal
- integrated circuit
- semiconductor integrated
- signal lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000009792 diffusion process Methods 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 229910020489 SiO3 Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/32—Reducing cross-talk, e.g. by compensating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5225—Shielding layers formed together with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
A first signal line A1, a second signal line B0 and a third signal line A2 are formed on a substrate 1 of a semiconductor integrated circuit. The effective distance 1A1B0 between the first signal line and the second signal line is substantially equal with the effective distance 1A2B0 between the second signal line and the third signal line. The first signal line transmits a first signal e1. The third signal line transmits a third signal -e1, of which the phase is opposite to that of the first signal. Thus, the cross talk from the first signal line to the second signal line can be cancelled by the cross talk from the third signal line to the second signal line. <IMAGE>
Description
SPECIFICATION
Semiconductor integrated circuit
The present invention relates to a semiconductor integrated circuit and seeks to reduce interference between signal lines thereof.
In a semiconductor integrated circuit which processes digital or analog signals, for example as shown in Figure 1,wheretwosignal lines A and B extend closely on the substrate 1, an abnormal voltage is so induced on either the signal line A or the signal line B by electrical capacitive coupling or inductive coupling between the signal lines A and B that a problem of electrical interference (i.e. cross talk) may occur.
For example as shown in Figure 1, electrical interference is liable to occur on the signal line Bo transmitting a signal e2 whose electrical amplitude is relatively small and which is disposed closely to the signal line Ao transmitting a signal e1 whose currentor voltage-amplitude is large and whose frequency is high.
In particular, in digital-analog hybrid circuits remarkable effects occur from a digital signal line to an analog line. As a result noise may be so generated on the analog signal line that the characteristic deteriorate or malfunction may occur. Such a mutual interference between digital signal lines may also cause the occurrence of a malfunction in digital circuits.
In order to prevent electrical interference between signal lines, attempts have been made to dispose these lines as far apart from each other as possible in the design lay-out on the substrate of the semiconductor integrated circuit. As a result, however, there is a problem that freedom in lay-out on the substrate of the semiconductor integrated circuit As a result, however, there is problem that freedom in lay-out decreases or improvement of integration density on a semiconductor chip is prevented.
The present invention provides a semiconductor integrated circuit comprising:
a first signal line formed on a substrate of the semiconductor integrated circuit, arranged to transmit a first signal;
a second signal line formed on the substrate, arranged to transmit a second signal; and
a third signal line formed on the substrate, arranged to transmit a third signal of which the phases opposite to that of the first signal so as to tend to cancel the cross talk between the first signal line and the second signal line by the cross talk between the second signal line and the third signal line.
Hereinafter the embodiments of the present inven- tion will be explained with reference to the drawings, wherein:
Figure 1 is a plan view showing the layout of signal lines in a semiconductor integrated circuit according to the prior art;
Figure 2 is a plan view showing the layout of signal lines in a semiconductor integrated circuit according to one embodiment of the present invention;
Figure 3 is a plan view showing the layout of signal lines in a semiconductor integrated circuit according to another embodiment of the present invention;
Figure 4 is a plan view showing the layout of signal lines in a semiconductor integrated circuit according to another embodiment of the present invention;
Figure 5 is a plan view showing the layout of signal lines in a semiconductor integrated circuit according to another embodiment of the present invention;;
Figure 6(A) and 6(B) are a plan view and a cross-sectional view showing the structure of signal lines in a semiconductor integrated circuit according to the present invention;
Figure 7(A) and (B) are a plan view and a cross-sectional view showing the structure of signal lines in a semiconductor integrated circuit according to the present invention;
Figure 8(A) and (B) are a plan view and a cross-sectional view showing the structure of signal lines in a semiconductor integrated circuit according to the present invention;;
Figure 9(A) and (B) are a plan view and a cross-sectional view showing the structure of signal lines in a semiconductor integrated circuit according to the present invention;
Figure IOIAI and (B) are a plan view and a cross-sectional view showing the structure of signal lines in a semiconductor integrated circuit according to the present invention;
Figure 11(A) and (B) are a plan view and a cross-sectional view showing the structure of signal lines in a semiconductor integrated circuit according to the present invention;
Figure 11(C) is a cross-sectional view showing the structure of signal lines in a semiconductor integrated circuit according to a modified embodiment of the present invention;;
Figure 12(A) and {B) is a plan view and a crosssectional view showing the structure of signal lines in a semiconductor integrated circuit according to the present invention; and
Figure 13(A) and {B) is a plan view and a crosssectional view showing the structure of signal lines in a semiconductor integrated circuit according to the present invention.
In the semiconductor integrated circuits (IC) of the following embodiments only signal lines related to the present invention are illustrated and other circuits or circuit devices existing in the vicinity of these signal lines are omitted.
Figure 2 shows the lay-out of signal lines in a semiconductor integrated circuit according to an embodiment of the present invention.
In the embodiment of Figure 2 the third signal line
A2 which is parallel to the first signal line A1 extends between the first signal line A1 and the second signal line Bo. Signals of opposite phases are transmitted on the first signal line Ar and the second signal line
A2 respectively.When signal line A, is disposed close to signal line A2 and the distance between the signal line A1 and the second signal line Bo is approximately equal with the distance between the signal line A2 and the second signal line Bo (1A1B, t 1A2Bo), voltage or current fluctuations on the signal line Bo induced by inductive coupling and capacitive coupling from the pair of signal lines A, and A2 cancel each other because the phases of signals e1 and -ea of the pair of signal lines Ar and A2 are opposite.As a result signal line Bo can be saved from the influence of the first signal line Al.
Figure 3 shows another embodiment. In the drawing there is disposed the third signal line A2 transmitting signal -e1 whose phase is opposite to that of the signal e1 on the first signal line A. Signal lines A, and A2 cross each other in a twisted fashion and signal currents e1 and -e1 whose phases are opposite each other flow into these signal lines A1 and A2. In this case by making them twisted the pair of signal lines A1 and A2 can be integrated more than in the case of the embodiment shown in Figure 2 and electrical interference on signal line B can be kept much smaller.
In contrast with the above, Figure 3 also illustrates the case where a strong signal current flows into the second signal line B and the second signal line B causes electrical interference on the first signal line A. By disposing signal lines A1 and A2 transmitting signals e1 and -ea of opposite phases in close vicinity to the large current signal line B electric influences from signal line B become equal on the signal lines A, and A2. When outputs of the pair of signal lines A, and A2 are applied to double-end input terminals of a differential amplifier, the difference signals of the noise components at the output terminals of this differential amplifier becomes zero.
As a result the noise can be removed. This structure shown in this embodiment is very effective in particular when a differential amplifier is disposed on the input side and differential outputs are extracted in double-end form.
Figure 4 shows an embodiment in which a differential amplifier 3 is disposed on the receiving side in order to prevent electrical interference or cross talk from the signal line B to a pair of signal lines A, and A2 in the case where the second signal line B carries a signal current e2 of relatively small electrical amplitude and the pair of signal lines A, and A2 carry a pair of signal currents e1 and -e1. In the drawing, numeral 4 represents an input circuit disposed on signal line B. Numeral 5 represents an output circuit on signal line B. Numeral 2 represents a a differential amplifier disposed on the input side of the pair of signal lines A1 and A2.Provision of a differential amplifier 3 on the receiving side (the output side of the pair of signal lines A, and A2) enables common noises at the output terminal of the differential amplifier 3 to be removed by the common-mode rejection function of the differential amplifier 3 and electric effect from signal line B on signal lines A, and A2 to be kept much smaller. This structure shown in Figure 4 is also effective in preventing electric interference from signal lines A1 and A2to signal lines B.
Figure 5 shows an embodiment in which crossing the first and third signal lines in a twisted fashion produces a greater effect than in the embodiment shown in Figure 4. In Figure 5 the same reference numeral symbols as Figure 4 are used to denote similar parts.
Next the structure of the above mentioned signal lines Al, A2 and signal line B on the semiconductor substrate (chip) of the present invention will be explained as follows.
1. The embodiment of using a pair of parallel wirings A1 and A2 which carry signal currents of opposite phases for the purpose of transmitting the first signal e1:
As shown in Figure 6(A) and (B) signal line B for transmitting the second signal e2 and a pair of signal lines A, and A2 which are made of Al (aluminum) films are respectively formed flat on the substrate 1 on an intermediate insulating film (SiO3 film) 6.
The embodiment of Figure 7(A) and (B) shows that a pair of Al signal lines A1 and A2 are formed in double layers, one above the other, with an intermediate insulating film 7 (e.g. polyimide resin layer).
The second signal line B is made of aluminum film on the same level as the lower aluminum film A2.
In Figure 8(A) and (B), of a pair of signal lines A1 and A2 for the first signals the signal line Ar is made of Al film and the other signal line A2 is made of a semiconductor diffusion layer 8 the impurity con ductivitytype of which is different from that of the substrate and which is disposed in the surface of the semiconductor substrate 1 under the insulating film 6. Signal line B for the second signal e2 is formed by an aluminum line in the same plane ass signal line Al.
In Figure 9(A) and (B) a pair of signal lines A1 and
A2 of aluminum wirings for the first signals e1 are formed on the insulating film 6 and a signal line B for the second signal e2 is made of a semiconductor diffusion layer 9 the impurity conductivity type of which is different from that of the substrate and which is disposed in the surface of the semiconductor substrate 1 just below the signal lines A1 and A2.
In Figure 10(A) and (B) signal lines A1 and A2 of Al filmsforthefirstsignals e1 are formed in double layers one above the other with an intermediate insulating film 7. A signal line B for the second signal e2 is made of a semiconductor diffusion layer 10 the impurity conductivity type of which is different from that of the substrate and which is disposed in the surface of the semiconductor substrate 1 just below the signal lines A1 and A2.
2. The embodiment using symmetric twisted lines A1 and A2 which carry the signal currents of opposite phases for the first signal eel : Figure 11(A), Figure 11(B) and Figure 11(C) show that in the signal lines A1 and A2 forthe first signals e1 the signal line A, is made of Al film formed on the substrate over an insulating film 6, and the signal line A2 is made of a semiconductor diffusion layer 8 the impurity conductivity type of which is different from that of the substrate and which is formed on the surface of the semiconductor substrate below the insulating film 6. The signal lines A and A2 cross and recross each other symmetrically when viewed in plan as shown in Figure 11(A). The second signal line B is made of Al film in the same plane as the signal line A1.
Figure 11(C) shows a modified embodiment of
Figure 11(B). In the drawing signal lines A, and A2 for the first signals e1 are formed by Al films in upper and lower layers which are isolated from each other by intermediate insulating film 7, and both of them are wired in twist form when viewed in plan as shown in Figure 11(A).
Figure 12(A) and Figure 12(B) show the following structure.
Namely, a pair of signal lines A, and A2 for the first signals is made of Al films and wired in twist form on the surface of the insulating film 6. At the crossing part of the signal lines A, and A2 a part of the signal line A2 are connected by Al upper layer 12 which is bridging a pair of through-holes 11 formed in the intermediate insulating film 7. Thus, the signal lines A1 and A2 cross each other in electrically isolated condition.
Figure 13(A) and Figure 13(B) show the following structure.
Namely, a pair of signal lines A, and A2 for the first signals is made of Al films and wired in twist form on the surface. At the crossing part of he signal lines A and A2 a part of one signal line (e.g. the signal line
A2) is cut off. Along this cut-off part of the signal line
A2 the impurity diffusion layer 13 the conductivity type of which is different from that of the substrate is formed on the surface of the semiconductor substrate 1. Parts of Al films of the signal line A2 are brought into contact with the diffusion layer 13 through the through-holes 14 which are formed in the insulating film 6. Thus, the signal lines A, and A2 cross each other in electrically isolated condition.
According to the embodiments described above noise which is generated by electric interference between signal lines in the semiconductor integrated circuit can be removed by using a pair of signal lines of opposite phases or a pair of signal lines of twist-symmetrical configuration configuration, or provided with a differential amplifier.
As a result, freedom in layout and easy circuit design can be achieved and integration density is improved.
The present invention may be applied to digital circuits, analog circuits and semiconductor integrated circuits combining the above-mentioned circuits.
Claims (8)
1. A semiconductor integrated circuit comprising:
a first signal line formed on a substrate of the semiconductor integrated circuit, arranged to transmit a first signal;
a second signal line formed on the substrate, arranged to transmit a second signal; and
a third signal line formed on the substrate, arranged to transmit a third signal of which the phase is opposite to that of the first signal so as to tend to cancel the cross talk between the first signal line and the second signal line by the cross talk between the second signal line and the third signal line.
2. A semiconductor integrated circuit according to claim 1, wherein the effective distance between the first signal line and the second signal line is substantially equal with the effective distance between the second signal line and the third signal line.
3. A semiconductor integrated circuit according to claim 2, wherein the first signal line and the third signal line cross each other in a symmetric configuration.
4. A semiconductor integrated circuit according to claim 2 or claim 3 wherein the first and third signal lines are in a symmetric twisted configuration.
5. A semiconductor integrated circuit according to any one of claims 1 to 4, further comprising a differential amplifier of which differential input terminals receive the first signal and the third signal.
6. A semiconductor integrated circuit according to claim 5, wherein the differential amplifier has a common-mode rejection function with respect to the differential input terminals.
7. A semiconductor integrated circuit according to claim 5 or claim 6, further comprising another differential amplifier of which output terminals deliver the first signal and the third signal to the first signal line and the third signal line.
8. A semiconductor integrated circuit substantially as any described herein with reference to
Figures 2 to 13 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55159480A JPS5784149A (en) | 1980-11-14 | 1980-11-14 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2089122A true GB2089122A (en) | 1982-06-16 |
Family
ID=15694687
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB813171A Withdrawn GB2089122A (en) | 1980-11-14 | 1981-10-15 | Semiconductor integrated circuit interconnections |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5784149A (en) |
| DE (1) | DE3145039A1 (en) |
| FR (1) | FR2498852A1 (en) |
| GB (1) | GB2089122A (en) |
| IT (1) | IT1140065B (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2134708A (en) * | 1983-01-18 | 1984-08-15 | Western Electric Co | Integrated circuits |
| GB2269941A (en) * | 1992-08-20 | 1994-02-23 | Hubbell Inc | Connector for communications systems with cancelled crosstalk |
| EP0661744A1 (en) * | 1993-12-28 | 1995-07-05 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device |
| US5432484A (en) * | 1992-08-20 | 1995-07-11 | Hubbell Incorporated | Connector for communication systems with cancelled crosstalk |
| US5435752A (en) | 1992-12-18 | 1995-07-25 | The Siemon Company | Electrically balanced connector assembly |
| US5618185A (en) * | 1995-03-15 | 1997-04-08 | Hubbell Incorporated | Crosstalk noise reduction connector for telecommunication system |
| EP0840376A1 (en) * | 1996-10-31 | 1998-05-06 | Metaflow Technologies, Inc. | Alternating invertors for capacitive coupling reduction in transmission lines |
| EP0856919A2 (en) * | 1997-02-04 | 1998-08-05 | Hubbell Incorporated | Low crosstalk noise connector for telecommunication systems |
| US5944535A (en) * | 1997-02-04 | 1999-08-31 | Hubbell Incorporated | Interface panel system for networks |
| WO2004025838A1 (en) * | 2002-09-13 | 2004-03-25 | Koninklijke Philips Electronics N.V. | Coding of information in integrated circuits |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59231852A (en) * | 1983-06-15 | 1984-12-26 | Hitachi Ltd | Semiconductor device |
| JPS60175470A (en) * | 1984-02-21 | 1985-09-09 | Agency Of Ind Science & Technol | Josephson integrated circuit |
| JPS60254635A (en) * | 1984-05-30 | 1985-12-16 | Fujitsu Ltd | Ic device |
| JPS60254489A (en) * | 1984-05-31 | 1985-12-16 | Fujitsu Ltd | Semiconductor storage device |
| JPS62174943A (en) * | 1986-01-29 | 1987-07-31 | Hitachi Ltd | Circuit device |
| JPH0625015Y2 (en) * | 1986-06-13 | 1994-06-29 | シャープ株式会社 | Semiconductor device |
| JPS63141A (en) * | 1986-06-19 | 1988-01-05 | Fujitsu Ltd | Semiconductor memory |
| JPS6366792A (en) * | 1986-06-27 | 1988-03-25 | テキサス インスツルメンツ インコ−ポレイテツド | Cross connected complementary bit line for semiconductor memory |
| JPS63234657A (en) * | 1987-03-24 | 1988-09-29 | Toshiba Corp | Signal transmission system |
| US5014110A (en) * | 1988-06-03 | 1991-05-07 | Mitsubishi Denki Kabushiki Kaisha | Wiring structures for semiconductor memory device |
| US5005212A (en) * | 1989-12-12 | 1991-04-02 | At&T Bell Laboratories | Interference suppression in optical communication systems |
| ATE130968T1 (en) * | 1991-08-01 | 1995-12-15 | Siemens Ag | CONNECTION FOR DOMESTIC COMPUTER NETWORKS. |
| US5226835A (en) * | 1992-08-06 | 1993-07-13 | At&T Bell Laboratories | Patch plug for cross-connect equipment |
| WO1994005092A1 (en) * | 1992-08-24 | 1994-03-03 | British Telecommunications Public Limited Company | Apparatus and method for crosstalk cancellation in data correctors |
| GB2270422B (en) * | 1992-09-04 | 1996-04-17 | Pressac Ltd | Method and apparatus for cross talk cancellation |
| JPH09326610A (en) * | 1996-06-06 | 1997-12-16 | Mitsubishi Electric Corp | Microwave integrated circuit |
| ES2147495B1 (en) * | 1997-07-30 | 2001-04-01 | Mecanismos Aux Es Ind S L | METHOD FOR IMPROVING THE CHARACTERISTICS OF ELECTROMAGNETIC COMPATIBILITY IN DIFFERENTIAL COMMUNICATION SYSTEMS. |
| DE19809570C2 (en) * | 1998-03-05 | 2000-02-17 | Siemens Ag | Signal connection |
| JP4817354B2 (en) * | 2004-11-05 | 2011-11-16 | ローム株式会社 | Semiconductor chip |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5539073B2 (en) * | 1974-12-25 | 1980-10-08 |
-
1980
- 1980-11-14 JP JP55159480A patent/JPS5784149A/en active Pending
-
1981
- 1981-10-15 GB GB813171A patent/GB2089122A/en not_active Withdrawn
- 1981-10-23 FR FR8119920A patent/FR2498852A1/en not_active Withdrawn
- 1981-11-10 IT IT24940/81A patent/IT1140065B/en active
- 1981-11-12 DE DE19813145039 patent/DE3145039A1/en not_active Withdrawn
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL8400132A (en) * | 1983-01-18 | 1984-08-16 | Western Electric Co | VLSI PLATE WITH REDUCED CLOCK SIGNAL DEVIATION. |
| FR2547676A1 (en) * | 1983-01-18 | 1984-12-21 | Western Electric Co | VERY HIGH-LEVEL INTEGRATION CIRCUIT CHIP WITH CLOCK SHIFT REDUCTION |
| GB2134708A (en) * | 1983-01-18 | 1984-08-15 | Western Electric Co | Integrated circuits |
| US5673009A (en) * | 1992-08-20 | 1997-09-30 | Hubbell Incorporated | Connector for communication systems with cancelled crosstalk |
| GB2269941A (en) * | 1992-08-20 | 1994-02-23 | Hubbell Inc | Connector for communications systems with cancelled crosstalk |
| US5414393A (en) * | 1992-08-20 | 1995-05-09 | Hubbell Incorporated | Telecommunication connector with feedback |
| US6132266A (en) * | 1992-08-20 | 2000-10-17 | Hubbell Incorporated | Method of reducing crosstalk in connector for communication system |
| US5432484A (en) * | 1992-08-20 | 1995-07-11 | Hubbell Incorporated | Connector for communication systems with cancelled crosstalk |
| GB2269941B (en) * | 1992-08-20 | 1995-11-08 | Hubbell Inc | Connectors for communication systems |
| US5435752A (en) | 1992-12-18 | 1995-07-25 | The Siemon Company | Electrically balanced connector assembly |
| US5474474A (en) | 1992-12-18 | 1995-12-12 | The Siemon Company | Electrically balanced connector assembly |
| US5585664A (en) * | 1993-12-28 | 1996-12-17 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device |
| EP0661744A1 (en) * | 1993-12-28 | 1995-07-05 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device |
| US5618185A (en) * | 1995-03-15 | 1997-04-08 | Hubbell Incorporated | Crosstalk noise reduction connector for telecommunication system |
| EP0840376A1 (en) * | 1996-10-31 | 1998-05-06 | Metaflow Technologies, Inc. | Alternating invertors for capacitive coupling reduction in transmission lines |
| EP1353378A1 (en) * | 1996-10-31 | 2003-10-15 | Metaflow Technologies, Inc. | Alternating invertors for capacitive coupling reduction in transmission lines |
| EP0856919A2 (en) * | 1997-02-04 | 1998-08-05 | Hubbell Incorporated | Low crosstalk noise connector for telecommunication systems |
| US5931703A (en) * | 1997-02-04 | 1999-08-03 | Hubbell Incorporated | Low crosstalk noise connector for telecommunication systems |
| EP0856919A3 (en) * | 1997-02-04 | 1999-08-11 | Hubbell Incorporated | Low crosstalk noise connector for telecommunication systems |
| US5944535A (en) * | 1997-02-04 | 1999-08-31 | Hubbell Incorporated | Interface panel system for networks |
| WO2004025838A1 (en) * | 2002-09-13 | 2004-03-25 | Koninklijke Philips Electronics N.V. | Coding of information in integrated circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2498852A1 (en) | 1982-07-30 |
| JPS5784149A (en) | 1982-05-26 |
| IT8124940A0 (en) | 1981-11-10 |
| DE3145039A1 (en) | 1982-09-16 |
| IT1140065B (en) | 1986-09-24 |
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