GB2085265A

GB2085265A - Switching networks for PCM channels

Info

Publication number: GB2085265A
Application number: GB8127267A
Authority: GB
Original assignee: Italtel SpA; Italtel Societa Italiana Telecomunicazioni SpA
Current assignee: Italtel SpA
Priority date: 1980-09-09
Filing date: 1981-09-09
Publication date: 1982-04-21
Also published as: IT1149253B; DE3135757A1; BR8105669A; JPS5779794A; IT8024541A0; FR2490055A1

Abstract

A switching matrix of n x n type is made up by n multiplexers M having n inputs and an output to allow the distribution of channels of n input PCM systems, synchronized with one another, among n output PCM systems, also synchronized with one another. Each input PCM system is connected to the corresponding inputs of all multiplexers, whose outputs are orderly connected to the output PCM systems. In order to improve the matrix operation at high switching speeds, there are provided n first registers R1, each being connected to the output of an input PCM system; n second registers R2, each being placed at the input of a multiplexer and having each of its n cells connected to an input of the multiplexer; and n third registers, each being placed between the output of a multiplexer and the input of an output PCM system. The first, second and third registers are all controlled by the same sequence of timing pulses t. <IMAGE>

Description

SPECIFICATION Improvements in or relating to switching networks for PCM channels The invention relates to a switching network for PCM channels, that is a circuit arrangement adapted to scan the channels forming part ofn input PCM systems and to group them so as to form the frames of n output PCM systems.

Modern telecommunication systems based on digital techniques are becoming increasingly important because they combine the advantage of employing advanced technologies and reliable and tested apparatus such as PCM apparatus with the capacity of being able to send indiscriminately telephone signals, data, images, etc., by the same transmission means.

The increasing adoption of digital techniques in all telecommunication fields has necessarily led to the designing and improving of switching devices, where each PCM channel arriving at such devices from the input PCM systems connected thereto, may be forwarded to any of the other output PCM systems.

Although the present invention may be successfully used for any switching device, it is specifically useful for improving the performance of space switching stages of space-time switching exchanges for PCM signals, such as described in the Italian Patent No. 1,037,256.

In such a switching network, the octets of bits forming each input PCM channel are subjected to a space switching, which transfers them from one PCM system to another PCM system connected to the switching network, as well as to a time switching, which transfers them from the phase of the input PCM system to that of the output PCM system. In a preferred embodiment, the time switching takes place in two successive time intervals and in an intermediate operating phase where space switching takes place. A first time switching stage formed by n input units, ann x n matrix for space switching, and a second time switching stage formed by n output units are therefore provided. Each input and output unit is connected to m PCM systems, where n x m is the total number of PCM systems connected to the switching network.The input and output units are synchronous with one another, being controlled by the same timing signals.

Many possible embodiments of n x n matrix are known from the art. A preferred embodiment relates to that providing n multiplexers, each having its output connected to one of the output units and its inputs connected in order ton input units. Each multiplexer is controlled by a recirculating memory, wherein at the beginning of a connection there is written in a known way what input unit is to be connected to the associated output unit during each time interval.

The correct operation of the switching exchange implies that the sequence of bit available at the input of the space switching stage be perfectly aligned with one another and with the clock driving the recirculating memory. With an increase in the transmission speed, the amount of shift which is allowable is progressively reduced, until the differences in the signal propagation times, due to the different lengths of the connections, become relevant.

This fact mainly concerns the input-multiplexer unit connection, wherein each bit reaches in sequence (and therefore, in different time intervals) the inputs of then multiplexers. Also the connections between multiplexers and output units show traces of the fact that their length is not uniform, it being impossible to place all output units at the same distance from the respective multiplexers.

A careful and sometimes complex study on the procedure according to which input units, multiplexers and output units are to be placed in the frames, for instance by grouping them in subsystems, can reduce but not eliminate the inconvenience (which brings about a limitation to the highest transmission speed).

According to the invention, there is provided a switching network for PCM channels, comprising n multiplexers each having n inputs and an output, n cyclic memories each arranged to control the respective multiplexer to which it is concerned, n input units for the PCM channels, each connected to the corresponding inputs of all the multiplexers, n output units each connected to the output of a respective multiplexer, n first registers each connected to the output of a respective one of the input units, n second registers each having n cells and being provided at the input of a respective one of the multiplexers with the outputs of then cells being connected to the corresponding inputs of the multiplexer, and n third registers each connected to the input of a respective one of the output units, the first, second and third registers being arranged to be controlled by a common sequence of pulses having a period not shorter than the maximum propagation time of a signal from any of the first registers to any of the second registers.

Such a circuit arrangement improves the operation of a space switching stage of the aforedescribed type and permits differences in the propagation times to be tolerated.

The invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 diagrammatically shows a switching network constituting a preferred embodiment of the invention; and Figure 2 shows two time diagrams relating to Figure 1.

Figure 1 illustrates a space-time switching network for PCM signals comprising n input units Ul (Ul1,...Uln), n multiplexers M (M1 ...Mn), each controlled by a cyclic memory MC (MC1 ...MCn) and n output units UU (UU1 ...UUn), each connected to the output of a respective multiplexer M.

The switching network further comprises: a first register R1(R1,1 ...Ri,k...R1,n) at the output of each input unit Ul; a second register R2(R2,1 ...R2,n) at the input of each multiplexer M, each second register having the inputs of each of its n cells connected to the outputs of the first registers, respectively, and having outputs connected to the inputs of the respective multiplexer M; and a third register R3(R3,1 ...R3,n), which is connected to an output unit UU, at the output of each multiplexer M.

The first, second and third registers are controlled by a timing signal t, which also controls the cyclic memories MC. The input units Ul are synchronized with one another in a known way, so that at the same instant a bit is available at the output of all the input units, each bit being part of the octets which form the channels of the PCM systems connected to each input unit Ul and which has been subjected to a first time switching by way of the input unit Ul.

The bits available at the outputs of the input units Ul are stored in the first register R1 at any clock pulse t, the clock pulses having the same frequency as the bit rate, whereas at the following clock pulse they are stored in the second register R2which transfer them to the multiplexer M. Therefore, the bits available at the input of the multiplexer are perfectly synchronous with one another, no matter from which input unit Ul they come and without any difference in the propagation times. The only restriction on the circuit arrangement is that the propagation time of a bit from the first to the second register must be shorter than or, at most, equal to the period of the clock t.By means of the cyclic memories MC1, the multiplexers MC are synchronized by the clock twhich, according to Figure 2, is enabled to reach the memory itself, modifying the address available at its output and therefore the input-output connection realized by the associated multiplexer, by a signal T, having a period TO equal to the duration of an octet and a duration such as to ensure the transit of a single clock pulse t, the signal T defining the initial bit of each octet and having, in a preferred embodiment, a duration equal to the clock period t. the bits available at the output of the multiplexer are simultaneously loaded in the third registers by the clock signal t irrespective of the length of the multiplexer-third register connection) and are thus perfectly synchronous at the input of the output units Ul, where they are subjected to a second time switching.

Various modifications may bne made within the scope of the invention. For instance, the first and /or third registers may be replaced by elastic bit storage to compensate for the effects of possible faults in synchronism of the input and/or output units.

Claims

1. A switching network for PCM channels, comprising n multiplexers each having n inputs and an output, n cyclic memories each arranged to control the respective multiplexer to which it is connected, n input units for the PCM channels each connected to the corresponding inputs of all the multiplexers, n output units each connected to the output of a respective multiplexer, n first registers each connected to the output of a respective one of the input units, n second registers each having n cells and being provided at the input of a respective one of the multiplexers with the outputs of then cells being connected to the corresponding inputs of the multiplexer, and n third registers each connected to the input of a respective one of the output units, the first second and third registers being arranged to be controlled by a common sequence of pulses having a period not shorter than the maximum propagation time of a signal from any of the first registers to any of the second registers.

2. A switching network as claimed in claim 1, in which the cyclic memories are arranged to be actuated by the logic product of the sequence of pulses and a signal having a period equial tithe duration of an octet and a duration equal to the period of the pulses of the sequence, the said signal defining the initial bit of each octet.

3. A switching network substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.