GB2080586A - Dynamic memory system with error correction - Google Patents

Abstract

Refresh and initialize counter circuits included within a dynamic memory system are supplemented with additional counter control circuits for synchronizing them from the same timing source which drives the refresh and initialize counter circuits. The counter control circuits count in accordance with modulus one less than a maximum count so as to enable the information stored in each location of the memory system to be read out, corrected for single bit errors and rewritten back thereby rendering the system less susceptible to soil errors such as those produced by alpha particles. Diagnostic apparatus enables testing and verifying the operation of the soil error control apparatus. Also, the diagnostic apparatus can drive the soil error control apparatus in a high speed mode enabling the read out correction and rewriting of each location to take place within a minimum amount of time. By monitoring the status of the information being corrected, the diagnostic apparatus is able to signal whether or not the soil error control apparatus is operating properly. <IMAGE>

Description

SPECIFICATION Dynamic memory system with error correction This invention relates to dynamic memory systems and more particularly to improving the reliability of such systems.

It has become well known to construct memory systems comprising a plurality of memory modules from arrays of metaloxide semiconductor (MOS) chips. Such chips require periodic refreshing of the charges stored therein to prevent the loss of information. Similarly, read or write operations involve alterations of the stored changes representative of information. In order to increase the reliability of such memory systems, it is well known to include in such systems error detection and correction apparatus for detecting and correcting errors within such semiconductor modules.

Recently, manufacturers of such MOS dynamic random access memory chips have noted that high density memory chips lack immunity to soft errors resulting from ionizing alpha particles. To overcome this problem, some manufacturers have improved the structures of the chips so as to provide a high degree of immunity to soft errors.

Recently, manufacturers of dynamic random access memory chips have noted that high density memory chips lack immunity to soft errors resulting from ionizing alpha particles. To overcome this problem, some manufacturers have improved the structures of the chips so as to provide a high degree of immunity to soft errors. While this approach reduces the likeliness of such soft errors, such errors still can occur which can give rise to uncorrectable error conditions.

Other manufacturers have proposed certain systems design alternatives. These include error correction, rewriting the corrected word to prevent error accumulation, periodic memory purging and systems redundancy. The soft error problems and the design alternatives are set forth in the publication "Memory Systems Design Seminar" by Intel Corporation, Copyright 1979.

It will be appreciated that while the above alternatives have been suggested, there appears to be no memory systems which have the ability to protect against soft errors.

Accordingly, it is a primary object of the present invention to provide a memory system with the capability of protecting against soft errors.

In memory systems, it becomes essential to ensure through the use of checking and diagnostic procedures that each portion of the memory system is operating properly. A very important aspect of such procedures involves the checking and verification of such error detection and correction apparatus in addition to any other apparatus included within the memory system for increased reliability.

Because of the increase in the complexity of the memory system that it has become desirable to include circuits within the system which facilitate the verification of the proper operation of the different portions of the memory system underthe control of a data processing unit. One such arrangement is described in U.S.

Patent No. 3,814,922. That arrangement includes a maintenance status register and associated apparatus for manipulation and storing of information involving errors detected in the memory module associated with a data processing unit. Errors detected in the memory module are entered in prescribed positions of the maintenance status register. The presence and nature of a detected error is signalled to the data processing unit, which responds in a manner appropriate to the nature of the error. The data processing unit has access to the contents of the maintenance status register in order to localize the malfunction and determine the availability of the memory module.

Another mode of operation is provided for checking the logic circuits associated with the apparatus for refreshing the volatile data contained in the memory elements. The operation of the logic circuit is verified under control of the data processing unit.

It is seen that the above arrangement enables verification of logic circuits which control the operations of a memory module during different modes of operation. However, there is no provision for directly verifying apparatus which is used for enhancing the reliability of memory module operations.

Accordingly, it is a further object of the present invention to provide apparatus for verifying the operation of soft error hardware apparatus associated with the memory modules of a memory system.

Accordingly the present invention provides a semiconductor memory system comprising: a dynamic memory including a number of addressable arrays of memory cells arranged in a number of rows and columns; error detection and correction means coupled to the memory for detecting and correcting errors in the contents of the cells read out from said memory during a memory cycle of operation; timing means which provide sequences of timing signals for performing memory cycles of operation; refresh and write control means, including row and column address counter means, which periodically generate refresh command signals under the control of the timing means; and rewrite control means including rewrite counter means which cyclically count the refresh command signals, the timing means generating, on each cycle of the rewrite counter means, a sequence of signals during a rewrite cycle for performing read and write cycles of operation upon the cells within the rows and columns specified by the row and column address counter means, the rewrite counter means having a count modulus which generates rewrite signals at such intervals, relative to the row and column addresses associated therewith, that rewrite cycles occur for all possible combinations of row and column addresses.

A dynamic memory system embodying the invention will now be described, by way of example, with reference to the drawings, in which: Figure 1 is a block diagram of the dynamic memory system.

Figure 2 discloses in greater detail the circuits of block 207 of Figure 1.

Figure 3 discloses in greater detail the timing circuits of block 204 of Figure 1.

Figure 4 discloses in greater detail the circuits of block 214.

Figure 5discloses in greater detail the read/write control circuits of block 208.

Figure 6 discloses in greater detail the circuits of block 212.

Figure 7discloses in greater detail the chips of blocks 210-20 and 210-40.

Figures 8a to 8c are timing diagrams used to explain the operation of the system.

Figures 9a and 9b illustrate the format of the memory addresses/commands applied to controller 200 as part of each memory read orwrite request.

Figure 10 discloses in greater detail the circuits of block 216.

Introductory summary The present system includes additional apparatus in a dynamic memory system which, in conjunction with the refresh initialization circuits and error detection and correction (EDAC) circuits of the dynamic memory system, initiates rewrite cycles of operation at a predetermined rate for writing corrected versions of the information read out from each location. The additional apparatus includes counter control circuits which are synchronized from the same timing source which synchronizes the operation of the refresh and initialize address counter circuits.The counter control circuits count with a modulus one less than a maximum count generated by such circuits enable the generation of a sequence of counts which select different combinations of row and column addresses for rewriting all of the locations with error free information during a corresponding number of cycles of operation at the predetermined rate.

The predetermined rate is selected to be much slower than the refresh rate so as to minimize interference with normal memory operations. By utilizing the existing refresh and initialize circuits and data paths, the amount of additional circuits is kept to a minimum.

In addition, diagnostic apparatus is included within the system which connects to the EDAC circuits and soft error rewrite control apparatus. The diagnostic apparatus includes means for placing the memory modules in a state for testing and verifying the operation of the soft error control apparatus. Additionally, the diagnostic apparatus includes mode control apparatus which connects to the soft error control apparatus for enabling operation in a high speed mode. This permits the read out, correction and rewriting operations performed upon locations under the control of the soft error rewrite control apparatus to take place within a minimum of time. In the preferred embodiment, the operations performed upon locations take place following each refresh cycle of operation.

By monitoring the status of the information being checked and corrected, the diagnostic apparatus utilizing the error signalling circuits included within the memory system is able to establish whether or not the soft error rewrite control apparatus is operating properly.

DETAILED DESCRIPTION Memory subsystem interface Before describing the controller of Figure 1, it is seen that there are a number of lines which constitute the interface between the controller and a bus. As shown, the interface lines include a number of address lines (BSAD00-23, BSAP00), two sets of data lines (BSDT00-15, BSDP00, BSDP08) and (BSDT16-31, BSDP16, BSDP24), a number of control lines (BSMREF-BSMCLR), a number of timing lines (BSREQT-BSNAKR), and a number of tie breaking network lines (BSAUOK-BSlUOK, BSMYOK).

The description of the above interface lines are given in greater detail in the section to follow.

Memory Subsystem Interface Lines Designation Description Address Lines BSAD00-BSAD23 The bus address lines constitute a 24-bit wide path used in conjunction with the bus memory reference line BSMREF to transfer a 24-bit address to controller 200 or a 16-bit identifier from controller 200 to the bus (for receipt by a slave unit). When used for memory addressing, the signals applied to lines BSAD00-BSAD03 select a particular 512K word module, the signals applied to lines BSAD04-OBBSAD22 select one of the 512K words in the module while the signal applied to line BSAD23 selects one of the bytes within the selected word (i.e., BSAD23=1 right byte; BSAD23=0=left byte).

When used for identification, lines BSAD00-BSAD07 are not used, The lines BSAD08-BSAD23 carry the identification of the receiving unit as transmitted to controller 200 during the previous memory read request.

Memory Subsystem Interface Lines Designation Description BSAP00 The bus address parity line is a bidirectional line which provides an odd parity signal for the address signals applied to lines BSAD00-BSAD07.

Data Lines BSDT00-BSDT15, The sets of bus data lines constitute a 32-bit or 2-word wide bidirectional path BSDT16-BSDT31 for transferring data or identification information between controller 200 and the bus as a function of the cycle of operation being performed.

During a write cycle of operation, the bus data lines transfer information to be written into memory at the location specified by the address signals applied to lines BSAD00-BSAD23. During the first half of a read cycle of operation, the data lines BSDT00-BSDT15 transfer identification information (channel number) to the controller 200. During the second half of the read cycle, the data lines transfer the information read from memory.

BSDP00, BSDP08, The bus data parity lines are two sets of bidirectional lines which provide odd BSDP16, BSDP24 parity signals coded as follows: BSDP00=odd parity for signals applied to lines BSDT00-BSDT07 (left byte); BSDP08=odd parity for signals applied to lines BSDT08-BSDT1 5 (right byte); BSDP16=odd parity for signals applied to lines BSDT16-BSDT23; and BSDP24=odd parity signals applied to lines BSDT24-BSDT31.

Control Lines BSMREF The bus memory reference lines extends from the bus to the memory controller 200. When set to a true state, this line signals the controller 200 that the lines BSAD00-BSAD23 contain a complete memory controller address and that it is performing a write or read operation upon the specified location.

When reset to a false state, the line signals controller 200 that the lines BSAD00-BSAD23 contain information directed to another unit and not controller 200.

BSWRIT The bus write line extends from the bus to the memory controller 200. This line when set to a true state, in conjunction with line BSMREF being true, signals controller 200 to perform a write cycle of operation. When reset to a false state, this line, in conjunction with line BSMREF being true, signals controller 200 to perform a read cycle of operation.

BSBYTE The bus byte line extends from the bus to controller 200. This line, when set to a true state, signals controller 200 that it is to perform a byte operation rather than a word operation.

BSLOCK The bus lock line extends from the bus to controller 200. When set to a true state, this line signals to controller 200 a request to perform a test or change the status of a memory lock flip-flop included within the controller 200.

BSSHBC The bus second half bus cycle line is used to signal a unit that the current information applied to the bus by controller 200 is the information requested by a previous read request. In this case, both controller 200 and the unit receiving the information are busy to all units from the start of the initiation cycle until controller 200 completes the transfer.

This line is used in conjunction with the BSLOCK line to set or reset its memory lock flip-flop. When a unit is requesting to read or write and line BSLOCK is true, the line BSSHBC, when true, signals controller 200 to reset its lock flip-flop.

When in a false state, it signals controller 200 to test and set its lock flip-flop.

BSMCLR The bus master clear line extends from the bus to controller 200. When this line is set to a true state, it causes the controller 200 to clear to zeros certain bus circuits within controller 200.

Memory Subsystem Interface Lines Designation Description BSREDD The red left line extends from controller 200 to the bus. When set to a true state in response to a read command, this line signals that an uncorrectable error is contained in the leftmost word of the pair of word being returned. if only one word is being returned, it is considered the leftmost word.

BSREDR The bus red right line extends from controller 200 to the bus. When set to a true state in response to a read command, this line signals that an uncorrectable error is contained in the rightmost word of the pair of words being returned.

BSYELO The bus yellow line is a bidirectional line which designates a soft error condition. When set to a true state during the second half of a bus cycle in response to a read command, it indicates that the accompanied transferred information has been successfully corrected.

When set to a true state during a memory read request, this line indicates that the read request is to be interpreted as a diagnostic command.

Bus Handshakel Timing Lines BSREQT The bus request line is a bidirectional line which extends between the bus and controller 200. When set to a true state, it signals the controller 200 that another unit is requesting a bus cycle. When reset to a false state, it signals controller 200 that there is no bus pending bus request. This line is forced to a true state by controller 200 to request a read second half bus cycle.

BSDCNN The data cycle line is a bidirectional line which extends between the bus and controller 200. When forced to a true state, the line signals the controller 200 that a unit was granted a requested bus cycle and placed information on the bus for another unit.

The controller 200 forces the line to a true state to signal that it is transmitting requested data back to a unit. Prior to this, controller 200 had requested and been granted a bus cycle.

BSACKR The bus acknowledge line is a bidirectional line which extends between the bus and controller 200. When set to a binary ONE by controller 200, the line signals that it is accepting a bus transfer during a read first half bus cycle or write cycle.

During a read second half bus cycle, this line when set to a binary ONE by the unit which originated the request signals the controller 200 of its acceptance of a transfer.

BSWAIT The bus wait line is a bidirectional line which extends between the bus and controller 200. When set to a true or binary ONE state by controller 200, it signals a requesting unit that the controller cannot accept a transfer at this time.

Thereafter, the unit will initiate successive retries until the controller 200 acknowledges the transfer. The controller 200 sets the BSWAIT line true under the following conditions: 1. It is busy performing an internal read orwrite cycle of operation.

2. It is requesting a read second half bus cycle.

3. It is anticipating a refresh operation.

4. It is performing a refresh operation.

5. It is busy when placed in an initialized mode.

6. It is busy performing a soft error rewrite cycle.

When the BSWAIT line is set to a true or binary ONE state by a unit, this signals the controller 200 that the data is not being accepted by the requesting unit and to terminate its present bus cycle of operation.

Memory Subsystem Interface Lines Designation Description BSNAKR The bus negative acknowledge line is a bidirectional line which extends between the bus and controller 200. When this line is set to a true or binary ONE state by controller 200, it signals that it is refusing a specified transfer. The controller 200 sets line BSNAKR to a true state as follows: 1. Memory lock flip-flop is set to a binary ONE, and 2. The request is to test and set the lock flip-flop (BSLOCK true and BSSHBC false).

In all other cases, when the memory lock flip-flop is set, controller 200 generates a response via the BSACKR line or the BSWAIT line or generates no response.

When the BSNAKR line is forced true by a unit, this signals controller 200 that the data is not accepted by the unit and to terminate its cycle of operation.

Tie Breaking Control Lines BSAUOK-BSIUOK The tie breaking network lines extend from the bus to controller 200. These lines signal controller 200 whether units of higher priority have made bus requests.

When all the signals on these lines are binary ONES, this signals controller 200 that it has been granted a bus cycle at which time it is able to force the BSDCNN line to a binary ONE. When any one of the signals on the lines is a binary ZERO, this signals controller 200 that it has not been granted a bus cycle and is inhibited from forcing line BSDCNN to a binary ONE.

BSMYOK The tie breaking network line extends from controller 200 to the bus. Controller 200 forces this line to a false or binary ZERO state to signal other units of lower priority of a bus request.

General description of the system of Figure 1 Figure 1 shows a preferred embodiment of a memory controller 200. Referring to Figure 1, it is seen that the controller 200 controls the two 256K word memory module units 210-2 and 210-4 of memory section 210.

The module units of blocks 210-2 and 210-4 include high speed MOS random access memory integrated circuits, blocks 210-20 and 210-40, and address buffer circuits, blocks 210-22 to 210-26 and 210-42 to 210-46.

Each 256K memory unit is constructed from 64K word by 1-bit dynamic MOS RAM chips illustrated in greater detail in Figure 7. More specifically, referring to Figure 7, it is seen that each 256K by 22-bit memory module includes 88 chips, each 65,534 (64K) word by 1-bit. Within each chip there are a number of storage arrays organized in a matrix of 256 rows by 256 columns of storage cells.

The controller 200 includes those circuits required to generate memory timing signals, perform refresh operation, soft error rewrite control operations, data transfer operations, address distribution and decoding operations and bus interface operations. Such circuits are included as part of the different sections of Figure 1.

The sections include a timing section 204, a refresh control section 205, a soft error rewrite control section 214, a data control section 206, an address section 207, a read/write control section 208, a data in section 209, a bus control circuit section 211, a memory initialize circuit section 212, bus driver/receiver circuit section 213, and a diagnostic mode control section 216.

The bus control section 211 includes the logic circuits which generate signals for generating and accepting bus cycle request for single and double word operation. As seen from Figure 1, these circuits as well as the circuits of the other sections are connected to the bus via the driver/receiver circuits of section 213 which are conventional in design. The section 211 includes the tie breaking network circuits which resolve request priority on the basis of a unit's physical position on the bus. The memory controller, located at the left most or bottom position of the bus, is assigned the highest priority while a central processing unit (CPU), located at the highest most or top position of the bus is assigned the lowest priority.

The timing section 204, shown in detail in Figure 3, includes circuits which generate the required sequence of timing signals from memory read and write cycles of operation. As seen from Figure 1, this section transmits and receives signals to and from sections 205,206,207,208,211 to 214, and 216.

The address section 207, shown in greater detail in Figures 2a to 2c, includes circuits which decode, generate and distribute address signals required for refresh operations, initialization and read/write selection. The section 207 receives address signals from lines BSAD08-BSAD23 and address lines BSAD00-BSAD07 and BSAP00 in addition to the memory reference control signal from the BSMREF line.

Additionally, section 207 receives control and timing signals from sections 204, 212 and 205.

The memory initialization section 212 includes circuits, conventional in design, for clearing the memory subsystem circuits to initial or predetermined state.

The read/write control section 208 includes register and control logic circuits, conventional in design. The register circuits receive and store signals corresponding to the states of the BSWRIT, BSBYTE and the address line BSAD23. The control circuits decode the signals from the register circuits and generate signals which are applied to sections 204, 207 and 210 for establishing whether the subsystem is to perform the read, write or read followed by a write cycle of operation (i.e., for a byte command).

The refresh section 205 includes the circuits for periodically refreshing the contents of the memory.

Section 205 receives timing and control signals from section 204 and provides refresh command control signals to sections 204, 207, 208 and 212.

The data in section 209 circuits of block 209-4 include a pair of multiplexer circuits and an address register which is connected to receive signals from section 206.

The multiplexer circuits, conventional in design, receive data words from the two sets of bus lines BSDT00-15 and BSDT15-31 and apply the appropriate words via the sets of output lines MDIE000-015 and MDlO000-01 5 to the correct memory modules during a write cycle of operation. That is, multiplexer circuits are selectively enabled by signal MOWTES000 generated by an AND gate 209-10 when initialize signal lNlTTM31 0 from 212 is a binary ZERO (i.e., not in an initialize mode).The AND gate 209-10 generates signal MOWTES000 as a function of bus address bit 22 (i.e., signal BSAD22) and whether the memory subsystem is doing a write operation (i.e., signal BSWRlT). During a write operation, signal MOWTES000 selects the correct data word (i.e., the word applied to bus lines BSDT00-15 or BSDT16-31) to be applied to the correct memory unit. This enables a write operation to start on any word boundary.

During a read operation, the multiplexer circuits are conditioned to apply the module identifieation information received from the bus lines BSDT00-15 back to the address bus lines BSAD08-23. This is done by loading the signals applied to lines BSDT00-15 into the even data registers 206-8 of section 206. This, in turn, causes the address register latches of block 209-4 to be set to the module identification information transmitted via the bus line BSDT00-15.

The data control section 206 includes tristate operated data registers 206-8 and 206-10 and multiplexer circuits 206-16 and 206-18 with associated control circuits which enable data to be written into and/or read from the even and odd memory units 210-20 and 210-40 of section 210 and red and yellow generator circuits of block 206-20. For example, during a double width read cycle operation, operand or instruction signals are read out from the units 210-20 and 210-40 into the even and odd output registers 206-8 and 206-10. During a write cycle of operation, the byte operand signals are loaded into the leftmost section of the pair of registers 206-8 and 206-10 from the bus via section 209-4 and written into the odd or even unit of section 210.

The controller 200 includes error detection and correction (EDAC) apparatus wherein each word contains 16 data bits and 6 check bits used to detect and correct single bit errors in the data words and detect and signal without correction, double bit errors in the data word. The EDAC apparatus includes two sets of EDAC encodeddecoder circuits 206-12 and 206-14. Additionally, the section 206 enables a return of identification information received from the data lines BSDT00-15 and stored in register 209-4 via the address lines BSAD08-23.

Additionally, the circuits of block 206-20, in response to the syndrome bit signals from EDAC circuits 206-12 and 206-14, generate signals indicating whether the information being transferred to the bus is in error and whether or not the error is correctable. That is, when signal MYYEL0110 is forced to a binary ONE, this indicates that the accompanying transferred information is correct but that a correction operation was performed (i.e., a hard or soft error condition). However, when signal MYREDDO10 or MYREDRO10 is forced to a binary ONE, this indicates that the accompanying transferred information is in error (i.e., an uncorrectable error condition). These signals, in turn, are used to generate the signals applied to bus lines BSREDD, BSREDR and BSYELO. For further details concerning the generation of these signals, reference may be made to U.S.Patent No. 4,072,853.

The soft error rewrite control section 214 includes circuits for periodically accessing each of the locations within the memory section 210 for reading out and rewriting back into these locations corrected information so as to render the memory 210 less susceptible to soft errors produced by alpha particles or other system disturbances. As seen from Figure 1, section 214 receives control signals from sections 205,212, 213, and 216. The section provides control signals to sections 204,206, and 207, as shown.

The diagnostic mode control section 216 includes circuitry for conditioning sections 206 and 214to enable rapid testing and verification of the operation of the soft error rewrite control apparatus of section 214. As seen from Figure 1, section 216 receives control signals from sections 204,208,211, and 213.

Pertinent portions of the above sections will be now discussed in greater detail with reference to Figures 2 through 7.

DETAILED DESCRIPTION OF CONTROLLER SECTIONS Section 204 and Section 206 Figure 3 illustrates in greater detail the timing circuits of section 204. The circuits receive input timing pulse signals TTAP01010 and TTAP02010 from delay line timing generator circuits, not shown. The timing generator circuits generate a series of timing pulses via a pair of series connected 200 ns delay lines in response to the signal MYACKR10 being switched to a binary ONE. These pulses in conjunction with the circuits of block 204 establish the timing for the remaining sections during a memory cycle of operation.

Additionally, the circuits of block 204 receive a boundary signal MYBNDY010, address signals LSAD22200 and LSAD2221 0 from section 207 and soft error rewrite control signal ALPCNT010 from section 214. Also, section 212 applies an initialize signal INITMM100 to section 204. The signals MYBNDY010 and ALPCNT010 are applied to a NOR gate 204-5 each of which force signal RASlNH010 to a binary ZERO when forced to a binary ONE. The series connected AND gate 204-7 logically combines initialize signal INITMM100, refresh command signal REFCOM100 generated by circuits within section 204, not shown, to produce signal RASINH000.A NAND gate 204-8 combines signals RASINH000 and address signal LSAD22210to produce an even row strobe inhibit signal ERASIH000. The signal is applied to an AND gate 204-10 for combining with a timing signal MRASTT010 derived from signal TTAP01010 via an AND gate 204-1. The result output signal MRASTE010 is applied to the RAS timing input of the even stack units 210-20.

A NAND gate 204-14 combines signals RASINHOlO and LSAD22200 to produce an odd row inhibit signal ORASIH000. This signal is combined in an AND gate 204-17 with timing signal MRASTT010 to generate row timing signal MRAST0010. This signal is applied to the RAS timing input of the odd stack units 210-40.

As seen from Figure 3, an AND gate 204-11 applies a timing signal MDECT0010 to a G input terminal of the middle section of even data register 206-8 in the absence of a refresh command (i.e., signal REFCOM000= 1).

Similarly, an AND gate 204-15 applies a timing signal MDOCT0010 to a G input terminal of the middle section of odd data register 206-10. The delay network 204-19 which connects in series with AND gates 204-3, 204-18 and 204-20 generates timing signal MCASTS010. The signal MCASTS010 is applied to the CAS timing input of the even and odd stack units 210-20 and 210-40.

The even and odd data registers 206-8 and 206-10 are tristate operated. The register circuits are transparent meaning that while the signal applied to the G input terminal is a binary ONE, the signals at the Q output terminals follow the signals applied to the D input terminals. That is, where the signal applied to the G input terminal goes low, the signal at Q output terminal latches.

The output terminals of registers 206-8 and 206-10 are connected in common in a wired OR arrangement for enabling the multiplexing of the pair of data word signals. Such multiplexing is accomplished by controlling the states of the signals MDOTSC000, MDOTSC010 and MDRELB000 applied to the output control (OC) input terminals of the different sections of registers 206-8 and 20610 shown in Figure 1. This operation is independent of the latching action of the register flip-flops which takes place in response to the signals applied to the G input terminals.

The series connected group of gates 204-22 to 204-28 control the states of signals MDOTSC1 00 and MDOTSC010. The AND gate 204-22 receives timing signals DLYINN010 and DLY020100 at the beginning of a read or write cycle for enabling the storage of identification information from the bus. Since this is not pertinent to present purposes, signal PULS2021 0 can be considered to be at a binary ZERO state. During a read operation, read command signal READCM000 is forced to a binary ZERO which causes AND gate 204-26 to force signal MDOTSC1 00 to a binary ZERO and NAND gate 204-28 to force signal MDOTSC010 to a binary ONE.

The signal MDOTSC100, when a binary ZERO, enables the middle sections of registers 206-8 and 206-10 to apply their contents to their output terminals. The signal MDOTSC010 when a binary ONE, inhibits the right most sections of registers 206-8 and 206-10 from applying their contents to their output terminals. During a write cycle, when read command signal READCM000 is forced to a binary ONE, AND gate 204-26 forces signal MDOTSC100 to a binary ONE while NAND gate 204-28 forces signal MDOTSC010 to a binary ZERO when signal ALPCNT000 is a binary ONE. This produces the opposite result to that described. That is, signal MDOTSC100 inhibits the middle sections of registers 206-8 and 206-10 from applying their contents to their output terminals.At the same time, signal MDOTSC010 enables the right most section of registers 206-8 and 206-10 to apply their contents to their output terminals. If signal ALPCNT000 is a binary ZERO, this inhibits NAND gate 204-28 from forcing signal MDOTSC010 to a binary ZERO in response to signal READCM000.

Accordingly, the right most sections of registers 206-8 and 206-10 are also inhibited from applying their contents to their output terminals.

Lastly, the section 204 further includes an AND gate 204-30. This AND gate in response to the timing signals DLY400010 and DLY220010 generated by the delay line timing circuits provides a reset signal RESET010 which is used to reset the soft error rewrite control circuits of section 214.

Section 207 Figure 2 illustrates the different sections of address section 207. As shown, section 207 includes an input address section 207-1, an address decode section 207-2, an address register section 207-4 and a refresh and initialize address register input section 207-6.

Sections 207-1 and 207-2 The input address section 207-1 includes a set of manuallyselectable switches of block 207-10 which receive bus address signals BSAD04110 and BSAD061 10. These switches select the high order bus address bit which selects the upper/lower 256K of memory when the system includes the full complement of 128K memory modules. When the memory modules are constructed using 64K chips, the top switch is placed in the closed position. This selects address bit 4 (signal BSAD04110) as the high order bus address bit. For 16K chips, the other switch is placed in the closed position which selects address bit 6.

Since it is assumed that the memory modules use 64K chips, the top switch is closed while the other switch is opened. The resulting high order bit signaliSADX6010 in addition to its complement along with the least significant bus address bits 22 and 21 are stored in a register 207-12. The three signals are loaded into register 207-12 when address strobe signal ADDSTR000 is forced to a binary ZERO. This occurs when the memory becomes busy (i.e., accepts a bus cycle/a memory request).

The outputs of register 207-12 are applied as inputs to a 2 to 1 MUX 207-14, conventional in design. As shown, signal APLCNT000 from section 214is inverted via inverter circuit 207-16 and applied as signal ALPCNT010 to the select input terminal (G0/G1) of circuit 207-14. When signal ALPCNT010 is a binary ZERO, signals BSAD2221 0 to BSADX621 0 register 207-12 are selected to be applied at theY output terminals of circuit 207-14. When signal ALPCNT010 is a binary ONE, signals ARAD21010 and ARADX6010 from section 207-6 are selected to be applied to the Y2 and Y3 output terminals while Y1 output terminal is forced to a binary ZERO.

As shown, the least significant address bit signals LSAD22210 and LSAD21 210 are applied to the input terminals of a binary decoder circuit 207-20. The least significant bit address signal LSAD22210 and its complement signal LSAD22200 generated by an inverter circuit 207-22 are applied to sections 204 and 206.

The high order bit signal LSADX6210 is applied to the enable/gate input terminal of decoder circuit 207-20.

The complement signal LSADX6200 generated by an inverter circuit 207-15 is applied to the enabie/gate input of decoder circuit 207-31, together with address signals LSAD2221 0 and LSAD21 210. When high order address signal LSADX6210 is a binary ZERO, decoder circuit 207-20 is enabled for operation. Similarly, when signal LSADX6210 is a binary ONE, decoder circuit 207-31 is enabled for operation.

Each of the four decode outputs DECOD0000 to DECOD3000 connects to a different pair of the NAND gates 207-24 to 207-30. It will be noted that the zero decode signal DECOD0000 connects to the inputs of NAND gates 207-24 and 207-26 which generate the 0 and 1 row address strobe signals. Similarly, the 1 decode signal DECOD1000 connects to the inputs of NAND gates 207-26 and 207-28 which generate the 1 and 2 row address strobe signals. The next sequential decode signal DECOD2000 connects to the two NAND gates which generate the next pair of sequential row address strobe signals. Lastly, the last decode signal DECOD3000 connects to NAND gates 207-30 and 207-24 which generate the 3 and 0 row address strobe signals. In a similar fashion, each of the four decode outputs DECOD4000 to DECOD7000 connects to a different pair of the NAND gates 207-32 to 207-38.

As seen from Figure 2, all of the NAND gates 207-24 to 207-30 and 207-32 to 207-38 receive a further input signal OVRDEC000 generated by a NAND gate 207-39. When either initialize signal INITMM100 or refresh command signal REFCOM100 is forced to a binary ZERO by the circuits of section 212 or section 204. AND gate 207-39 forces signal OVRDEC000 to a binary ZERO. This turns on all the decode signals (i.e., signals DRAST0010 to DRAST7010 are forced to binary ONES) enabling eight memory locations to be written simultaneously during an initialize mode of operation, or "refreshed" during a refresh mode. As shown, the even row address strobe signals DRAST0010 and DRAST2010 are applied to the RAM chips of the even stack units 210-20. The odd row address strobe signals DRAST1010 and DRAST3010 are applied to the RAM chips of the odd stack units 210-40.

Section 207-4 The address register section 207-4 as shown in Figure 2 receives the bus address signals BSAD05210 to BSAD20210 applied via the bus receiver circuits of block 213 of Figure 1 as inputs to different stages qf a row address register 207-40 and a column address register 207-41. Also, as seen from Figure 2, this section receives inputs from the circuits of block 207-6 which are applied to different stages of a refresh address register 207-42 and a column address register 207-43. The enabling gate input terminals of registers 207-40 and 207-41 are connected to receive a memory busy signal MEMBUZ010 from section 204. The enabling gate input terminals of registers 207-42 and 207-43 are connected to a +5 volts source.The OC input terminal of row address register 207-40 is connected to receive a timing signal MRASCT000 generated by AND gate 207-44, inverter circuit 207-46 and NAND gate 207-47 in response to signals lNlTMM000, REFCOM000 and MCASTT010. The OC input terminal of column address register 207-41 is connected to receive a timing signal MCASCT000 generated by NAND gate 207-48 and NAND gate 207-50 in response to signals lNTREF000 and MCASTT010. The signal INTREF000 is generated by series connected AND gates 20744 and 207-48 which receive signals INITMM000, REFCOM000 and ALPCNT000.The OC input terminal of refresh address register 207-42 is connected to receive a control signal MREFCT000 generated by NAND gate 207-49, NAND gate 207-51 and inverter circuit 20745, in response to signals INTREF000, MCASTT010, MCASTT010 and lNlTAL110.

Each of the address registers 207-40 to 207-43 is constructed from D type transparent latch circuits. As seen from Figure 2, the different address output terminals of the registers of each set are connected in common in a wired OR arrangement for enabling the multiplexing of these address signals. As previously described, such multiplexing is accomplished by controlling the state of the signals applied to the output control (OC) input terminals of the registers 207-40 through 20743.

More specifically, the output control (OC) terminals enable so-called tristate operation which are controlled by the circuits 207-44 to 207-51. When each of the signals MRASCT000, MCASCT000, MREFCT000 and MWRTCT000 is in a binary ONE state, this inhibits any address signals from being applied at the Q output terminals of that register. As mentioned, this operation is independent of the latching action of the register flip-flops.

Additionally, section 207-4 includes a 4-bit binary full adder circuit 207-54, conventional in design. The adder circuit 207-54 is connected to increment by one the low order address bits 20 to 17. In greater detail, the input terminal A1-A8 receive signals MADD00010 to MADD03010. Binary ZERO signals are applied to input terminals B1-B8. An AND gate 207-56 generates a carry in signal MADDUC010 as a function of the states of the least significant address signals LSAD22210 and LSAD21210, signal lNTREF000 and timing signal DLY060010.

The incremented output signals MADD00111 to MADD03111 appearing at adder sum terminals S1-S8 are applied via address buffer circuits 210-26 to the even stack RAM chips of Figure 7. The same is true of signals MADD0410 to MADD07010. The odd stack RAM chips of Figure 7 are connected to receive the address signals MADD0010 to MADD07010 via address buffer circuits 210-46.

Section 207-6 The refresh and initialize address register input section 207-6 includes the refresh counter and write address counter circuits which generate the address values applied to the refresh and write address registers of section 207-4. As shown, the refresh counter circuits include two series connected binary counters 207-60 and 207-61.

Counter 207-60 is connected to receive a clocking signal RADDUC000 which is generated by an inverter circuit 207-67, NOR gate 207-66 and AND gates 207-65 and 207-68 in response to signals ALPH Us010, lNlTMM100, REFCOM000 and MCASTT010. Both counters receive a clearing signal MYCLRR010from section 212.

The write counter circuits also include two series connected binary counters 207-62 and 207-63 which are driven by signal REFAD801 0 from the refresh counter circuits. Both counters receive a clearing signal MYCLRR1 10 generated by a NAND gate 207-69 in response to signals MYCLRR000 and PWONLL010.

The circuits further include a D-type flip-flop 207-71 which serves as an extra stage of counter 207-63. The flip-flop 207-71 is connected to receive the complement signal WRITA7100 of most significant write address bit signal WRITA701 0 from an inverter circuit 207-72. Initially, when signal WRITS7010 is a binary ZERO, signal WRITA7100 is a binary ONE. Upon power-up, the D-type flip-flop 207-71 is cleared by signal MYCLRR1 00. When signal WRITA7010 switches to a binary ONE at the end of a first pass, signal WRlTA71 00 switches from a binary ONE to a binary ZERO which has no effect on the state of flip-flop 207-71.Upon completion of a second pass, signal WRITA7010 switches back to a binary ZERO which causes signal WRITS7100 to switch flip-flop 207-71 from a binary ZERO to a binary ONE. At this time, signal MADROL000 switches from a binary ONE to a binary ZERO. The signal MADROL000 is applied to section 212 and is used to signal the completion of the initialization operation. The flip-flop 207-71 is enabled for operation by PWONLL010 and a +5 volt signal which are applied to the preset and D input terminals, respectively. Also, an NAND gate 207-70 applies a signal MYCLRR100 to the clear input terminal which is generated in response to signal PWONLL300 and PWONLL01 0 from section 212.

As seen from Figure 2, section 207-6 includes a further binary counter 207-64. This counter also receives signal WRlTA7010 from write address counter 207-63. It receives clearing signal MYCLRR110 from NAND gate 207-69. As explained herein, this counter supplements the existing refresh and initialization circuits and forms a part of the soft error rewrite control circuits 214.

Read/Write Contrnl Section 203 A portion of the circuits of section 208 is shown in greater detail in Figure 5. As mentioned, the section 208 includes a register 208-10 and circuits 208-1 2 to 208-45. The register 208-10 is a two-stage D-type flip-flop register for storing signal BSWRIT110 which is representative of a read/write command and signal BSYELO1 10 which is representative of a bus single bit error condition. These signals are latched when signal MYACKR010 from section 211 switches to a binary ONE. When any one of the signals REFCOM000, INITMM00 or BSMCLR000 switches to a binary ZERO, an AND gate 208-12 forces signal CLRMOD000 to a binary ONE which clears register 208-10 to a binary ZERO state.

The write mode signal LSWRIT010 and error condition signal LSYEL0010 are applied to section 211. The read mode signal READMM010 is applied to an AND gate 208-14 which also receives an initialize signal INITAL000 from section 214.

The AND gate 208-14 in response to a read command (i.e., signal READMM010 is a binary ONE) when the system is not being initialized or is carrying out a soft error rewrite cycle operation (i.e., signal INITIAL000 is a binary ONE) forces signal READMMl010 to a binary ONE. When signal READMl010 is a binary ONE, this causes a NOR gate 208-40 to force a read command signal READCM000 to a binary ZERO. An AND gate 208-42 in response to signal READCM000 forces signal READCM100 to a binary ZERO. A pair of AND gates 208-23 and 208-25 force signals MEREAD010 and MOREAD010 to binary ZEROS. These signals are applied to the read/write control lines of the even and odd stack units 210-20 and 210-40. However, the signals are inverted by circuits included with units 210-20 and 210-40 as shown in Figure 7 before being applied to the chips which comprise such units.

Another one of the input signals to NOR gate 208-40 is partial write signal PARTWT010. There are certain types of memory operations such as byte write and initialize operations which require two cycles of operation. The same is true for soft error rewrite cycles of operation. As mentioned, in the case of an initialize or a soft error rewrite operation, signal INITAL000 is forced to a binary ZERO. This is effective to override the command applied to the bus. The read/write command signals MEREAD010 and MOREADOlO applied to the stack units 210-20 and 210-40 are generated as a function of signal PARTWT010.Signal PARTWT010 when forced to a binary ONE remains a binary ONE until the end of the first cycle and initiates a second cycle of operation during which another set of timing signals identical to the first are generated by the circuits of section 204. During the first cycle, the read/write command signals are forced to binary ZEROS and during the second cycle, the signals are forced to binary ONES. The signal PARTWT010 is generated by a D-type flip-flop 208-16 with associated input circuits 208-17 to 208-26.The flip-flop 208-16 is enabled for switching when signal PWTSET000 applied to preset input terminal is forced to a binary ZERO by AND gates 208-17, 208-26,208-27 and 208-28, in addition to NAND gates 208-18, 208-19 and 208-20 in response to refresh command signal REFCOM1 10, initialize signal lNlTMM010, timing signal MPULSE010, byte write signals BYWRIT100 and BYWRIT200 and rewrite phase 2 signal ALPHA2000. This enables flip-flop 208-16 to switch to a binary ONE. The flip-flop 208-16 switches to a binary ZERO state in response to signal DLYW02000 being applied to the clock input terminal via an inverter circuit 208-21. The +5 volts signal applied to the clear input terminal of flip-flop 206-18 inhibits resetting.In the same manner, as described above, partial write signal PARTWT010 when forced to a binary ONE initiates a read cycle of operation prior to initiating the'write cycle of operation required for the execution of the above mentioned operations in addition to each soft error rewrite control operation. As seen from Figure 1, partial write signal PARTWT010 is applied to the G input terminals of the right most sections of registers 206-8 and 206-10. Signal PARTWT010 when a binary ONE enables the storage of the output signals from EDAC circuits 206-12 and 206-14.

The other signals MEMBUZ000 and REFCOM110 applied to NOR gate 208-40 are forced to binary ONES prior to the start of a memory cycle of operation and during a refresh cycle respectively. It will be noted from Figure 5 that during a write cycle of operation when signal WRITCT000 is forced to a binary ZERO by the circuits of section 204, signal WRITCT1 10 generated by an inverter circuit 208-15 causes AND gate 20842 to switch signal READCM100 to a binary ONE. This in turn causes AND gates 208-23 and 208-24 to force signals MEREAD010 and MOREAD010 to binary ONES indicating that the stack units 210-20 and 210-40 are to perform a write cycle of operation.At this time, a power on signal PW5ASD000 from section 212 is normally a binary ONE while abort write signal EWRITA000 and OWRlTA000 in the absence of error conditions are binary ONES.

As seen from Figure 5, the signals EWRlTA000 and OWRITA000 are received from flip-flops 208-44 and 208-45. These flip-flops receive as inputs signals MDlEWE01 0 and MDlOWE01 0 from EDAC circuits 206-12 and 206-14. The states of these signals are stored in the flip-flops 208-44 and 208-45 when signal PARTWT010 switches from a binary ONE to a binary ZERO. The flip-flops 208-44 and 208A5 are cleared to ZEROS via a NOR gate 208-46 when the memory is not busy (i.e., signal MEMBUZ000 is a binary ONE) or is cleared (i.e., signal BSMCLR210 is a binary ONE).

Memory Units 210-20 and 10-40 - Figure 7 As previously discussed, the even word and odd word stacks of blocks 210-20 and 210-40 are shown in greater detail in Figure 7. These stacks include four rows of 22 64K X 1-bit RAM chips as shown. Each 64K chip includes two 32,768 bit storage arrays. Each array is organized into a 128 row by 256 column matrix and connects to a set of 256 sense amplifiers. It will be appreciated that other 64K chip orgnizations may also be utilized. The chips and associated gating circuits are mounted on a daughter board.Each daughter board includes 2 inverters (e.g. 210-203,210-207) which are connected to receive a corresponding one of the read/write command signals from section 208 and four, 2 input NAND gates (e.g. 210-200 through 210-206 and 210-400 through 210-406) which are connected to receive the row and column timing signals from section 204 and the row decode signals from section 207. Only those chip terminals pertinent to an understanding of the present invention are shown. The remaining terminals, not shown, are connected in a conventional manner.

INITIALIZE SECTION 212 Figure 6 shows in greater detail the initialize logic circuits of section 212. As shown, the circuits include a power on flip-flop 212-1, a power on register flip-flop 212-12, an initialize mode flip-flop 212-14 and a clear flip-flop 212-16. All of the flip-flops are D-type flip-flops. The power on flip-flop 212-1 receives a bus power on signal BSPWON010 at its clock input terminal via a series connected resistor 212-2. A +5 volt signal PWONRC010 is applied to clear input terminals of the flip-fiops 212-1 and 212-12 via a series connected resistor 212-4 when power is applied. A resistor-capacitor filter network including resistor 212-6 and capacitor 212-8 connect in parallel to the clear input terminal.

The binary ONE output signal PWONLL010 is applied to the input of a delay circuit 212-10 constructed of 6 series connected inverter circuits. The output signal PWONLL61 0 generated by delay circuit 212-10 is applied to the D input terminal of flip-flop 212-12. When signal PWONLL610 is forced to a binary ONE following the switching of signal PWONLL010 to a binary ONE, flip-flop 212-12 switches to a binary ONE state on the positive going edge of signal REFCOM210. The clear flip-flop 212-16 switches signal MYCLRR010 to a binary ONE in response to signals MYPWON010 and REFCOM210. The binary ONE output signal MYPWON010 of flip-flop 212-12 is applied to the clock input terminals of initialize mode flip-flop 212-14 and clearflip-flop 212-16. The change in state in signal MYPWON010 switches flip-flops 212-14 and 212-16 to binary ONE states. REFCOM210 resets flip-flop 212-16 to a binary ZERO.

The binary ONE and binary ZERO outputs from these flip-flops are applied to the circuits of sections 205, 207 and 209 via invertercircuits 212-18,212-20 and 212-22togetherwfth signal PWONLL300 generated by delay circuit ?12-1 0. The initialize mode flip-flop 212-16 switches to a binary ZERO when the circuits of section 207 force signal MADROL000 to a binary ZERO.

SOFT ERROR REWRITE CONTROL SECTION 214 Figure 4 shows in greater detail the soft error rewrite control circuits. The section 214 includes a counter section 214-1 and a cycle phase control circuit section 214-2. The section 214-1 establishes the cycle timing for performing a soft error rewrite cycle operation enabling every location in memory to be addressed.

Section 214-2 generates the required control signals which define the different phases of operation.

In greater detail, section 214-1 includes three series connected binary counters 214-10 to 214-14, a NAND gate 214-16 and an inverter circuit 214-18. The counters 214-10 to 214-14 are incremented by one at the end of each refresh cycle in response to signal REFCOM 100. This synchronizes the counter operations with the refresh counter circuits. The 11 outputs from the counter stages are applied to NAND gate 214-16. This gate monitors the counts generated by the counters and forces a command signal ALPCOM000 to a binary ZERO each time the counters reach a predetermined count. This predetermined count is selected to have a value which clears out soft errors from memory at a rate which provides a minimum of interference with normal memory operations. The rate is such that after every 2,047 refresh cycles or counts, a rewrite cycle is performed.Therefore, the 524288 memory locations can be cleared from the effects of alpha particle contamination or other noise signal disturbances within a 2 hour period.

Additionally, NAND gate 214-16 also receives signals ALPABY000 and ALPABY100 from section 216. When either signal ALPABY000 or signal ALPABY100 is forced to a binary ONE, this inhibits NAND gate 214-16 from forcing signal ALPCOM000 to a binary ZERO. As explained herein, this bypasses or renders the circuits of section 214 inoperative.

As seen from Figure 4, the inverter circuit 214-18 inverts the command signal ALPCOM000 to generate a set signal ALPSET110. This signal is applied to the clear input terminals of binary counters 214-1 through 214-14 and to an input NAND gate 214-21 of section 214-2. When signal ALPSET110 is forced to a binary ONE, it clears counters 214-10 through 214-14to ZEROS for starting a new count.

As seen from Figure 4, section 214-2 includes a pair of input NAND gates 214-20 and 214-21 which connect to an AND gate 214-22, three phase control D-type flip-flops 214-24 to 214-26 connected in series, a stop cycle D-type flip-flop 214-27 and associated input and output gate and inverter circuits 241-30 to 214-36 connected, as shown. Each of the flip-flops 214-24 to 214-26 are cleared to binary ZEROS in response to a power on signal PWONLL010 generated by the circuits of section 212 (i.e., when signal PWONLL010 is a binary ZERO).

The stop cycle flip-flop 214-27 is reset to a binary ZERO state when a bus clear signal BSMCLR200 is forced to a binary ZERO.

The NAND gate 214-20 receives as one input, refresh command signal REFCOM110 from section 205 and as a second input, a test mode signal TESTMM010 from section 216. As explained later, the NAND gate 214-20 generates signal ALPCOM200 which enables the circuits of this section to operate in a high speed mode of operation. The NAND gate 214-12 receives as one input, signal ALPSET1 10 from inverter circuit 214-18 and as a second input, a complement test mode signal TESTMM100 from section 216.As explained later, NAND gate 214-21 generates signal ALPCOM100 during the normal operation of the circuits of section 214. Both NAND gates 214-20 and 214-21 receive as a third input, initialize signal INITMM100 from section 212.

During normal operation (i.e., TESTMM100 is a binary ONE), when an initialize operation is not being performed, (i.e., signal INITMM100 is a binary ONE), NAND gate 214-21 in response to signal ALPSET110 being forced to a binary ONE, forces a command signal ALPCOM100 to a binary ZERO. This causes AND gate 214-22 to force signal EALPST000 to a binary ZERO switching the phase 1 flip-flop 214-24 to a binary ONE. In a similar manner, during a high speed mode of operation (i.e., signal TESTMM010 is a binary ONE) when an initialize operation is not being performed, NAND gate 214-20, in response to refresh command signal REFCOM110 being forced to a binary ONE, forces command signal ALPCOM200 to a binary ZERO. The flip-flop 214-24 when in a binary ONE state defines the refresh portion of the rewrite cycle.The binary ZERO output signal ALPHA1000 is applied to the preset terminal of stop cycle flip-flop 214-27. This switches flip-flop 214-27 to a binary ONE state.

The memory busy signal MEMBUZ000 is switched to a binary ZERO in response to a refresh command (i.e., when signal REFCOM 110 switches to a binary ONE). At the end of the refresh cycle when the memory busy signal switches from a binary ZERO to a binary ONE, signal ALPHA1010 causes the phase 2 flip-flop 214-25 to switch to a binary ZERO which, in turn, resets the phase 1 flip-flop 214-24 to a binary ZERO state via AND gate 214-30. The flip-flop 214-25 when in a binary ONE state defines the read portion of the rewrite cycle sequence.

The binary ONE output signal ALPHA2010 is applied to the D input terminal of the phase 3 flip-flop 214-26.

When the RRESET010 pulse signal is generated by the circuits of section 204 at the end of the read cycle of operation, the trailing edge of the pulse signal switches flip-flop 214-26 to a binary ONE state. The binary ZERO output signal ALPHA3000 upon being switched to a binary ZERO resets phase 2 flip-flop 214-25 to a binary ZERO via AND gate 214-31. The binary ONE state ofthe phase 3flip-flop 214-26 defines the write portion of the rewrite cycle. At the end of the write cycle of operation, RRESET010 pulse signal switches the phase 3 flip-flop 214-26 to a binary ZERO state since the signal ALPHA2010 is a binary ZERO at this time.

When either the phase 2flip-flop 214-25 or phase 3 flip-flop 214-26 is a binary ONE, the signal ALPHA2000 or signal ALPHA3000 applied to AND gate 214-32 forces signal ALPCNT000 to a binary ZERO. The signal ALPCNT000 when forced to a binary ZERO conditions the circuits of section 207 to select the address signals from the rewrite counter circuitfor decoding during these portions of the rewrite cycle sequence.

Additionally, signal ALPCNT000 causes AND gate 214-33 to force signal INITIAL000 to a binary ZERO which conditions the circuits of section 208 so as to override bus commands during the read and write portions of a rewrite cycle.

Additionally, signals lNlTMM1 00 and READCM000 when binary ONES cause an AND gate 210-38 to force signal INITOR00 to a binary ONE. This signal together with the complement signal ALPCNT01 0 generated by an inverter circuit 214-35 when forced to binary ONES, condition a NAND gate 214-39 to force signal MDRELB000 to a binary ZERO. As seen from Figure 1, signal MDRELB000 is applied to the OC terminals of the right sections of registers 206-8 and 206-10. When a binary ZERO, signal MDRELB000 enables the contents of these registers to be applied to their output terminals.

It will also be noted that when the phase 3 flip-flop 214-26 is reset to a binary ZERO, the switching of signal ALPHA3000 from a binary ZERO to a binary ONE resets the stop cycle flip-flop 214-27 to a binary ZERO. This causes a change in state of up count signal ALPHUC010 generated by OR gate 214-34 which, in turn, increments by one the counter circuits of section 207. OR gate 214-34 also generates an increment signal at the end of a refresh cycle in response to signal REFCOM110.

DIAGNOSTIC MODE CONTROL SECTION 216 Figure 10 shows in greater detail the diagnostic mode control circuits. These circuits generate signals which establish the required modes of operation for the system as Figure 1 which facilitate testing and verification of the soft error rewrite control section.

As shown, the circuits include a 3 to 8 binary decoder circuit 216-2, an EDAC mode flip-flop 21610 and manual diagnostic switch 216-12, a soft error rewrite control bypass mode flip-flop 216-20, and a test mode flip-flop 216-22 and manual switches 216-24 and 216-26.

The decoder circuit 216-2 is enabled for operation when signal LSYEL0010 is forced to a binary ONE and signal LSWRIT010 is forced to a binary ZERO. The circuit 216-2 in response to particular codings of the binary coded signals BSAD21210, BSAD20210, and BASD19210 applied to its terminals A, B and C forces a corresponding one of its output terminals to a binary ZERO. For example, when bits 19,20 and 21 have the value "010", signal SETEDA000 is forced to a binary ZERO. Similarly, the values "011" and "110" respectively force signals RESEDA000 and ALPRFC000 to binary ZEROS.

As shown, signal SETEDA000 is applied to the preset (PR) input terminal of the D-type flip-flop 216-10 via a series connected inverter circuit 216-4 and NAND gate 216-6. Similarly, signal RESEDA000 is applied to the clear (CLR) input terminal of flip-flop 216-10 via another series connected inverter circuit 216-5 and NAND gate 216-8.

Both NAND gates 216-6 and 216-8 receive timing signal PULS2021 0. This signal is generated by series connected inverter circuit 216-38, NAN D gate 216-36 and inverter circuit 216-34 in response to signal ALPHCT010 from section 214 and timing signal PULS20010 from section 208. The flip-flop 216-10 also receives signal BSMCLR31 0 from section 211 which is applied to its clock (C) input terminal, as shown. The binary ZERO output terminal of flip-flop 216-10 is applied to one of the input terminals of each of a pair of AND gates 216-14 and 216-16. The other input terminal of each AND gate receives signal DlAGTS000 from the output terminal of the push button switch 216-12.

When either the switch 216-12 is pressed or the flip-flop 216-10 is set to a binary ONE, AND gates 216-14 and 216-16 force signals EDACCK000 and EDACCK100 to binary ZEROS. As explained later, the signals EDACCK000 and EDACCK100 are applied to EDAC circuits 206-12 and 206-14, respectively, and when binary ZEROS cause the sets of check bit signals MDlEC0-C5 and MDIOCO-C5 to be forced to binary ZEROS.

The signal ALPREFC000 from decoder circuit 216-2 is applied to the clock (C) input terminal of D-type flip-flop 216-20 via series connected inverter circuit 216-18 and AND gate 216-19. The flip-flop preset input terminal is connected to receive a binary ONE (+5 V) signal while its clear (CLR) input terminal is connected to receive a power on signal PWON LL01 0 from section 212. The data (D) input terminal receives address bit 15 signal BSAD1 5210 from a receiver circuit of section 213. The output of flip-flop 216-20 which corresponds to signal ALPABY100 is applied to section 214.

As seen from Figure 10, the signal ARCCLK010 produced by AND gate 216-19 is also applied to the clock (C) input terminal of D-type flip-flop 216-22. The flip-flop's other input terminals receive the same signals as applied to flip-flop 216-20 except for the D input terminal receiving address bit 15 which is replaced with signal BSAD14210 from a receiver circuit section 213.

Both flip-flops 216-20 and 216-22 are conditioned during the positive going transition of clocking signal ARCCLK01 0 to switch state as a function of the states of address bits 15 and 14. Switching occurs when signal MYDCNN210 is forced to a binary ONE by the circuits of section 211.

The binary ONE output of flip-flop 216-22 is applied to one input terminal of an OR gate 216-30. The other input terminal of OR gate 216-30 is connected to the output of test mode switch 216-24 through an inverter circuit 216-28.

When either flip-flop 216-22 is set to a binary ONE or switch 216-24 is placed in the "on" (i.e., closed) position, OR gate 216-30 forces signal TESTMM010 to a binary ONE. The signal TESTMM0l0 and its complement signal TESTMM100 produced by an inverter circuit 216-32 are applied to section 214.

In a similar fashion, switch 216-26 when placed in the "on" (i.e., closed) position forces signal ALPABY000 to a binary ZERO. It will be noted that the output terminal of switch 216-26 connects to a +5 volt source through a termination resistor 216-27. Accordingly, switch 216-26 when placed in the "off" (i.e., open) position forces signal ALPABY000 to a binary ONE. Similarly, the output terminals of switches 216-24 and 216-12 connect to +5 volt sources through termination resistors 216-25 and 216-15, respectively. Therefore, when either switch 216-24 and 216-12 is placed in the "off" position, this results in signal TESTM M000 or signal DIAGTS000 being forced to a binary ONE.

DESCRIPTION OF OPERATION With reference to Figures 1-7, the operation of the present system will now be described with particular reference to the timing diagrams of Figures 8a to 8c. To appreciate the operation of the present system, it is helpful to describe how the refresh and initialize circuits carry out refresh and initialize operations.

Before discussing an example of operation, reference is first made to Figure 9a. Figure 9a illustrates the format of the memory addresses applied to the memory subsystem as part of each memory read or write request. The high order/most significant bit positions are coded to identify the memory module/controller to process the request. Address bit 4 is used to select which 256AK half (i.e., upper or lower half) of controller memory is being accessed. These address bits are processed by the circuits of controller 200 and are not provided to the RAM chips.

Address bits 5-20 specify the address of the 22-bit storage location within the RAM chips being addressed.

As explained in greater detail herein, these 16 address bits are multiplexed into 8 address inputs and applied via the address buffer circuits of blocks 210-26 and 210-46 to the address input terminals A0-A7 of the RAM chips of Figure 7.

The least significant address bits 21-22 are coded to select which row of RAM chips are being addressed.

As discussed herein, these bits are decoded and used to generate a pair of row address strobe (RAS) signals which latch the 8-bit row addresses into the desired row of RAM chips within each memory stack.

Figure 9b illustrates the format of the memory address applied to the controller as part of a diagnostic command. As in the case of a read or write, bits 0-4 are processed by the controller 200. Address bits 19, 20, and 21 define the type of diagnostic operation to be performed. As shown, the diagnostic code 010 causes the controller 200 to be placed in an EDAC test mode. As explained later, in response to this code, the controller 200 reads out the contents of the location being addressed and transfers the contents to the bus.

While in this mode, the controller 200 inhibits the generation of BSREDD and BSREDR signals during read cycles and forces the check bit signals to ZEROS during write cycles.

A diagnostic code of 011 causes the controller 200 to reset the EDAC mode. In response to this code, the controller 200 clears status and EDAC check bit indicators and reads the contents of the location being addressed and transfers the contents to the bus.

The last diagnostic code 110 which is the most pertinent defines different modes of operation for the soft error rewrite control section 214. When this code is received, bits 14 and 15 are interpreted as defining the operating speed of the soft error rewrite control section and its operational status, respectively. As explained herein, when this diagnostic code is received, controller 200 reads the contents of the location being addressed and transfers the contents to the bus during the second half of a bus cycle. It also modifies the operation of the soft error rewrite control section in the manner specified by bits 14 and 15.

Figure 8a illustrates diagrammatically the different timing signals involved during the execution of a refresh cycle of operation by the refresh circuits of section 205 of Figure 1. The circuits 205 provide a means of substituting a refresh cycle of operation. This occurs when the controller 200 is not in the process of executing a memory cycle, not anticipating any memory cycle or not requesting a cycle. It will be appreciated that refresh cycles are distributed over a 4 ms interval specified for refreshing the total number of rows/columns of the memory system. In the case of a 64K MOS chip, 256 cycles are required to refresh all of the cells of the entire chip. In the present system, a refresh cycle of operation is started every 15,us by the 30 ns width pulse signal CORREF000.This signal, in turn, causes the generation of a 150 nanosecond fine refresh timing pulse signal FINREF000. The signal FlNREF000 causes the switching of a refresh command flip-flop to a binary ONE. As seen from Figure 8a, this results in signal REFCOM010 being forced to a binary ONE. Thus, the complement of the refresh command signal REFCOM000 switches to a binary ZERO.

Referring to Figure 2, it is seen that signal REFCOM000 causes NAND gate 207-49 to force refresh signal MREFCT000 to a binary ZERO. When the binary ZERO signal is applied to the output control (OC) terminal of the refresh address register 207-42, this causes the register 207-42 to apply the refresh address contents to the odd and even stack units 210-20 and 210-40 of Figure 7. Simultaneously, refresh command signal REFCOM100 conditions the timing circuits 204 of Figure 3 for generating row address timing signals MRASTE010 and MRASTOO 10. At this time, signal REFCOM100 effectively overrides the state of least significant address bit LSAD22. Also, from Figure 2, it is seen that signal REFCOM100 while a binary ZERO causes AND gate 207-39 to force signal OCRDEC000 to a binary ZERO. This overrides all of the decoded row strobe signals so that all of the row address strobe signals DRAST0010 through DRAST7010 are forced to binary ONES. This loads the refresh address contents into each of the rows of RAM chips of Figure 7.

The result is that a row within each row of RAM chips included within the units 210-20 and 210-40 of Figure 7 are refreshed as a consequence of a read operation being performed on the addressed 8 rows of RAM chip locations. That is, the signals MEREAD010 and MOREAD010 from section 208 are binary ZEROS which cause the RAM chips of Figure 7 to perform a read cycle of operation. That is, refresh command signal REFCOM110 caused the circuits of Figure 5 to maintain signals MEREAD010 and MOREAD010 at binary ZEROS. Prior to that, signal MEMBUZ000 was a binary ONE which forced signals MEREAD010 and MOREADOlO to binary ZEROS.

It will also be noted from Figure 3 that refresh command signal REFCOM1 00 inhibits the generation of the CAS timing signal and signals MDOECT000 and MDOOCT000. This prevents information to be written into locations within the stack units 210-20 and 210-40 as well as the read out of information to the output registers 206-8 and 206-10 of Figure 1.

The end of the refresh cycle of operation is signalled by the leading edge of pulse signal REFRES000 which resets the refresh command flip-flop to a binary ZERO. This, in turn, forces signal REFCOM010 to a binary ZERO. At the trailing edge of signal REFCOM01 0, the AND gate 207-68 of Figure 2 forces signal RADDUC000 from a binary ZERO to a binary ONE which, in turn, increments by one, the address contents of refresh counter 207-60. This address change is transferred to refresh address register 207-42 as shown in Figure 8a by the change in signal MADDXX.

The 8-bit counter 207-62 is added to refresh counter 207-60 which enables controller 200 to operate in an initialize mode. The counter 207-62 furnishes the CAS addresses required for writing ZEROS into the addressed storage locations when the controller 200 is in an initialize mode of operation (i.e., signal INITMM010 is a binary ONE).

Figure 8b illustrates the different signals involved during the execution of an initialize cycle of operation by the circuits of section 212 and write address counter circuits of Figure 2. As shown, when power is turned on, this produces a bus power on transition which results in signal BSPWON010 switching to a binary ONE.

From Figure 6, it is seen that this change of state is latched in flip-flop 212-1. That is, flip-flop 212-1 switches signal PWONLL010 to a binary ONE. The signal PWONLL010 is delayed by circuit 212-10 and then switches flip-flop 212-10 to a binary ONE. As seen from Figure 8b, the initialize mode flip-flop 212-14 switchies to a binary ONE in response to refresh command signal REFCOM1 10. Prior to that, signal MADROL000 from flip-flop 207-71 of Figure 2 was switched to a binary ONE by signal PWONLL300. This cleared the initialize mode flip-flop 212-14 to a binary ZERO state.

The refresh command signal REFCOM1 is generated in the manner previously described. It will also be noted that the circuits of section 208 of Figure 5 switch partial write signal PARTWT010 to a binary ONE. That is, AND gate 208-18 is conditioned by signals REFCOM1 lOand lNlTMM010 to force signal PWTSET200 to a binary ONE. This enables flip-flop 208-16 to switch to a binary ONE upon the occurrence of timing signal DLYW02000.

Signal PARTWT010 when a binary ONE causes AND gate 208-42 to hold signals MEREAD010 and MOREADO10 at binary ZEROS enabling a refresh operation to be performed upon the eight rows of storage locations during the first (1) of two cycles shown in Figure 8b generated by the timing generator circuits (not shown) of section 208. That is, refresh command signal REFCOM 110 when switched to a binary ONE causes the timing generator circuits to initiate a series of timing pulses of a first cycle. This results in signal DLYINN0010 being switched to a binary ONE. Signal PARTWT010 remains a binary ONE and at the end of the first cycle, signal DLYIN N010 is switched to a binary ONE. This causes another set of timing signals identical to the first to be generated.Prior to the switching of signal PARTWT010 to a binary ONE, the signals MEREAD010 and MOREAD010 were at binary ZEROS as a consequence of signals MEMBUZ000 and REFCOM010 being forced to binary ONES.

As described above, during the refresh cycle of operation, the refresh command signal causes the refresh address register 207-42 to apply the refresh address contents to the odd and even stack units 210-20 and 210-40, the timing circuits 204 to generate row address timing signals MRASTE010 and MRASTO0l 0 and force all of the decoded row strobe signals to binary ONES. The result, as mentioned above, causes the refreshing of eight rows of storage locations within the RAM chips of Figure 7.

Since the controller 200 is in an initialize mode, signal INITMM100 inhibits AND gate 207-68 of Figure 2 from forcing refresh increment signal RADDUC000 to a binary ONE at the end of the refresh cycle.

Accordingly, the contents of the refresh address counter 207-60 and 207-61 remain unchanged.

As seen from Figure 8b, a next cycle is entered during which both RAS and CAS timing signals are generated which enables binary ZERO information to be written into a storage location within each of the eight rows of the RAM chips of Figure 7. That is, from Figure 3, it is seen that when initialize signal lNlTMMl00 is forced to a binary ZERO, this enables the generation of timing signals MRASTE010 and M RASTOO 1 O. As seen from Figures 8b and 3, the timing circuits 204 follow this with the generation of signal MCASTS010 since at this time signal REFCOM100 is a binary ONE. In the manner previously described, the refresh contents of refresh address register 42 are applied to the odd and even stack units 210-20 and 21090 as a consequence of signal INITMM000 forcing signal MREFCT000 to a binary ZERO state. The row address signals are stored in each of the rows of RAM chips of Figure 7 in response to signals MRASTE010 and MRAST0010.

From Figure 2, it is seen that the power on signal PWONLL010 was forced to a binary ONE, which caused the clearing of the write counter 207-62 and 207-63 to binary ZEROS. The contents of the write counter are, in turn, loaded into the write address register 207-43. The NAND gate 207-51 of Figure 2, in response to signals MCASTT010 and INITALl 10, forces signal MWRTCT000 to a binary ZERO. This causes the write address register 207-43 to apply its column address contents to the stack units 210-20 and 210-40. Since signal INTREFOOO was forced to a binary ZERO by signal INITMM000, the adder 207-54 applies the column address contents without modification to even stack unit 210-20.

It is seen from Figure 8b that when partial write signal PARTWT010 switches to a binary ZERO, this, in turn, switches the read command signal READCM000 to a binary ONE. As seen from Figure 5, the flip-flop 208-16 switches to a binary ZERO in response to timing signal DLY400010 following the switching of read command signal REFCOM M 110 to a binary ZERO. The signal READCM000 conditions AND gate 208-42 to force signal READCM 100 to a binary ZERO in response to write timing signal WRITCT000 from the timing generator circuits 204. This, in turn, causes AND gates 208-23 and 208-25 to force signals MEREAD010 and MOREAD010 to binary ZEROS.Accordingly, the RAM chips of Figure 7 are conditioned to perform a write cycle of operation upon the eight simultaneously selected chip locations during which binary ZEROS, loaded into the even and odd data registers 206-8 and 206-10, are written therein. That is, the initialize signal INITMM310 from section 212, when forced to a binary ONE upon the setting of the initialize mode flip-flop 212-14 of Figure 6, inhibits the enabling of data-in MUXs 209-4. The result is that binary ZEROS loaded into the leftmost sections of registers 206-8 and 206-10 are applied as inputs to stack units 210-20 and 210-40 in response to signal MDOTSC01O. At this time, signals MDOTSC000 and MDRELB000 are binary ONES which inhibit the middle and rightmost sections of registers 206-8 and 206-10 from applying signals to their output terminals.

At the end of the write cycle, as shown in Figure 8b, signal MCASTT010 switches to a binary ZERO. This causes AND gate 207-68 of Figure 2 to force signal WTCAST01 0 to a binary ZERO which, in turn, forces signal RADDUC000 from a binary ONE to a binary ZERO. This causes the series connected refresh and write counter circuits 207-60 through 207-63 to be incremented by a count of one. At the beginning of the next 15 microsecond interval signalled by pulse CORREF000, the sequence of operations illustrated in Figure 8b is repeated using the next address signals specified by the contents of the refresh and write counter circuits of Figure 2.

By repeating the above operations, every decoded location of the units 210-20 and 210-40 is initialized to ZEROS. Since the decodes are overridden, binary ZEROS are written into an addressed location in each of the eight rows of 64K RAM chips simultaneously which reduces the amount of time required for initializing the memory subsystem.

The completion of the initialize operation is signalled by the switching of flip-flop 207-71 of Figure 2 to a binary ONE. This forces signal MADROL000 to a binary ZERO which, in turn, clears initialize mode flip-flop 21 2-14 to a bi na ry ZERO state. As seen from Figure 2, the flip-flop 207-71 switches to a binary ONE when the write address bit signal WRITAT100 switches from a binary ZERO to a binary ONE state (i.e., positive going transition). This occurs when bit signal WRlTA7010 switches from a binary ONE to a binary ZERO indicating that the last address location has been written.

From the above, it is seen how every decoded location is addressed and initialized to ZEROS. In order to be able to address every location, instead of overriding the decode signals derived from the address signals applied thereto, counter 207-64 is connected in series with the refresh and write address counters 207-60 to 207-63 of Figure 2. This counter generates the address bits LSAD21 and LSADX6 which are used to address the same location within both units 210-20 and 210-40.

Figure 8c illustrates the operation of the soft error rewrite control section 214 in carrying a normal cycle of operation. This operation is provided by extending the refresh and initialize cycles of operation so as to minimize the amount of logic circuits added to the controller 200.

Whereas the initialize mode occurs only during powering up the controller, a soft error rewrite cycle occurs in synchronism with a refresh cycle of operation. The frequency of occurrence of the cycle is established by signal ALPCOMOOO. When this signal is forced to a binary ZERO by all ONES input from counters 214-10, 214-12, and 214-14, two things occur. One is that the counters 214-10, 214-12, and 214-14 are reset to start counting from ZERO by signal ALPSET1 10 being forced to a binary ONE. The other is that the phase 1 flip-flop 214-24 is set to a binary ONE.

As seen from Figure 8c, the setting of the phase 1 flip4lop 214-24 to a binary ONE causes the stop cycle flip-flop 214-27 to switch to a binary ONE. For the purposes of the present invention, this signal indicates the occurrence of a soft error rewrite cycle and its duration.

The phase 1 flip-flop 214-24 defines the period or interval during which a normal refresh cycle takes place.

This cycle is carried out in the manner discussed with reference to Figure 8a. Upon the completion of the refresh cycle, the memory busy signal MEMBUZO0O is forced to a binary ONE. This switches the phase 2 flip-flop 214-25 to a binary ONE. This causes signal ALPHA2000 to reset phase 1 flip-flop 214-24 to a binary ZERO. Normally, as seen from Figure 8c, the refresh and write counter circuits are incremented at the end of a refresh cycle. However, since a soft error rewrite cycle is being performed at this time, the setting of the stop cycle flip-flop 214-27 forces up count signal ALPHUC010 to a binary ONE. This, in turn, causes the AND gate 207-65 of Figure 2 to force signal I N ITU C000 to a binary ONE causing signal RADDUCOOO to be forced to a binary ONE. This prevents the incrementing of the refresh and write counters at this time.

As seen from Figure 8c, the setting of phase 2 flip-flop 214-24 causes partial write flip-flop 208-16 of Figure 5 to switch to a binary ONE. That is, signal ALPHA2000, when switched to a binary ZERO, forces signal BYWRIT010 to a binary ONE. NAND gate 208-19 forces signal PWTSET100 to a binary ZERO upon the occurrence of signal IMPULSE010. This forces signal PWTSET0OO to a binary ZERO which enables flip-flop 208-16 to switch to a binary ONE state. The setting of the partial write flip-flop 208-16 signifies that the timing generator circuits 204 will generate two sequences of timing signals, one for a read cycle followed by a write cycle. When the flip-flop 208-16 switches to a binary ONE, it causes read command signals MEREAD010 and MOREAD10 to be forced to binary ZEROS.

As seen from Figure 4, signal ALPCNT000 is switched to a binary ZERO when the phase 2 flip-flop 214-25 switches to a binary ONE. This signal causes the multiplexer circuit 207-14 of Figure 2 to select as a source of address signals, the signals ARAD21 010 and ARADX601 0 from the counter 207-64. As seen from Figure 2, least significant address bit LSAD22 is forced to a binary ZERO. This effectively eliminates bit LSAD22 causing a double word operation beginning with the even stack units 210-20 so as to take advantage of the address decode arrangement of Figure 2. Bits 21 and X6 specify the contents of which word locations in stack units 210-20 and 21040 are to be read out to data registers 206-8 and 206-10.These bits together with bit 22 are decoded by decoder circuits 207-20 and 207-31 and force the appropriate decode row address strobe signals to binary ONES.

Also, signal ALPCNT010 is switched to a binary ONE when phase 2 flip-flop 214-25 is switched to a binary ONE. This signal conditions the timing circuits 204 of Figure 3 so as to enable the generation of timing signals for cycling both stack units 210-20 and 210-40 during a read cycle of operation. That is, signal ALPCNT01 0 forces signal RASI N H01 O to a binary ZERO. This, in turn, causes NAND gates 204-8 end 204-14 to force signals ERASIH000 and ORASIH000 to binary ONES which enables timing signals MRASTEO1 0 and MRAST001 0 to be applied to the even and odd stack units 210-20 and 21040. Also, the AND gates 204-11 and 204-15 are conditioned to apply subsequently timing signals MDOECTO1O and MDOOCTO1O to the even and odd registers 206-8 and 206-10.

The read operation is performed upon the pair of locations specified by the refresh and write address counters, in addition to counter 207-64. That is, in the manner previously described, the address contents of the refresh and write address counters 207-60 through 207-63 are fed into the refresh address and write address registers 207-42 and 207-43, respectively. As seen from Figure 8b, signal MEMBUZ010 remains a binary ONE during the entire rewrite cycle of operation.

As seen from Figure 2, signal ALPCNT000 enables the storage of the row address signals by causing AND gate 207-48 to force signal INTREF200 to a binary ZERO. This, in turn, causes NAND gate 20749 to force signal MREFCT000 to a binary ZERO which enables the address contents of refresh address register 207-42 to be applied to the odd and even stack units 210-20 and 210-40. The row address signals are stored in the RAM chips of Figure 7 in the pair of rows specified by the outputs from decoder circuits 207-20 and 207-31.

These row address signals are stored in response to even and odd row address strobe signals MF;ASTE010 and MRASTO010 generated in response to row address timing signal MRASTTO1 0.

In a similar fashion, the column address signals which correspond to the address contents of the write address register 207-43 are stored in all of the RAM chips. More specifically, signal MCASTT010 from timing generator 204 and signal INITIAL110 cause NAND gate 207-51 of Figure 2 to force signal MWRTCT000 to a binary ZERO. This conditions the write address register 20743 to apply its address contents to the stack units 210-20 and 210-40. These signals are stored in the RAM chips of Figure 7 in response to column address signal MCASTS010.

The switching of phase 2 flip-flop 214-25 causes the switching of the partial write flip-flop 208-16 to a binary ONE state. This defines the read operation of the cycle by forcing the signal READCM000 to a binary ZERO. Signal READCM000 is a binary ZERO at this time which, in turn, causes signals MEREAD010 and MOREADOl 0 to be binary ZEROS. Therefore, the RAM chips of the selected pair of rows are conditioned to perform a read operation wherein their contents are read out into the even and odd data registers 206-8 and 206-10 which have been enabled by signals MDOECT0010 and MDOOCT0010, respectively. At this time, read command signal READCM000 holds signal MDRELB000 at a binary ONE.This inhibits the contents of the right most sections of registers 206-8 and 206-10 from being applied at the outputs thereof. Also, read command signal READCM000 causes the circuits 204 to force signal MDOTSC100to a binary ZERO and signal MDOTSC010 to a binary ONE. This inhibits the contents of the left most sections of registers 206-8 and 206-10 from being applied to the inputs thereof. At the same time, the read out word contents, stored in the middle sections of registers 206-8 and 206-10, are applied to EDAC circuits 106-12 and 206-14.

During the read cycle of operation, the words read out from the pair of locations are checked for errors by the error detection circuits included within the EDAC circuits 210-12 and 210-14. Any single bit errors located within the words are corrected by the error correction circuits included with the EDAC circuits 210-12 and 210-14. Since signal PARTWT010 is a binary ONE, the corrected words are loaded into the rightmost sections of registers 206-8 and 206-10 and rewritten back into stack units 210-20 and 210-40 during the interval defined by the next occurrence of signal MCASTT010 of Figure 8c.

Where more than one error is detected to have occurred within a word, this causes one of the EDAC circuits 206-12 and 206-14 to force signal MDIEWE010 or signal MDlOWE010 to a binary ONE state. This, in turn, sets the even abort write flip-flop 208-44 or odd abort write flip-flop 208-45 of Figure 5 to a binary ONE state when partial write signal switches from a binary ZERO to a binary ONE state. As explained herein, this aborts the write operation thereby preserving the error status of the original information.

When the timing generator 204 generates signal RESET010, the phase 3 flip-flop 214-26 is conditioned by the binary ONE state of signal ALPHA2010 to switch to a binary ONE. As seen from Figure 8b,the phase 2 flip-flop 214-25 is reset to a binary ZERO by AND gate 214-31 of Figure 4. The switching of the phase 3 flip-flop 214-26 initiates a second sequence of timing signals required for performing a write cycle of operation. Since signal ALPUC010 is still a binary ONE (i.e., the stop cycle flip-flop 21427 is still a binary ONE), this inhibited the incrementing of the refresh, write and decode address counters 207-60 through 207-64 by signal RADDUC000. Hence, the write operation is performed upon the same pair of locations within the stack units 210-20 and 210-40.In the manner just described, the same row and column address signals are caused to be stored in the RAM chips of the two rows specified by the address bit signals ARAD21010 and ARADX6010.

Briefly, as seen from Figure 4, the states of signals ALPCNT000 and ALPCNT010 remain the same as a consequence of the phase 3 flip-flop 214-26 being switched to a binary ONE. Accordingly, the row address contents of the refresh address register 207-42 are applied to the stack units 210-20 and 210-40 and stored in the RAM chips of the same two rows addressed during the prior read cycle of operation in response to signal MRASTT010.

In a similar fashion, the column address contents of write address register 207-43 are applied to the stack units 210-20 and 210-40 and stored in the RAM chips of Figure 7, in response to signal MCASTT010.

As seen from Figure 8c, during the write cycle, the timing generator circuits 204 repeat the generation of the same sequence of timing signals which cause the contents of the addressed pair of storage locations to be read out into registers 206-8 and 206-10. At this time, partial write signal PARTWT010 is a binary ZERO.

That is, the partial write flip-flop 208-16 is reset to a binary ZERO in response to timing signal DLYW0200 since at that time signal ALPHA2000 is a binary ONE.

Since read command signal READCM000 and signal ALPCNT010 are binary ONES, this causes NAND gate 214-39 of Figure 4 to force signal MDRELB000 to a binary ZERO. This enables the right most sections of registers 206-8 and 206-10 containing the corrected word pair to apply its contents to the outputs thereof. At the same time, signals READCM000 and ALPCNT000 force signals MDOTSC100 and MDOTSC010 to binary ONES. This inhibits the left most and middle sections of registers 206-8 and 206-10 from applying signals at the outputs thereof during this interval.

Accordingly, the contents of the pair of addressed storage locations previously read out into the right most sections of registers 206-8 and 206-10 are written back into the addressed storage locations.

Accordingly, any single bit errors occurring within either one or both of the words read out will have been corrected utilizing the error detection and error correction circuits included within the system. Thus, any soft errors are eliminated from the pair of words accessed which, in turn, prevents such errors from turning into double errors which are not correctable.

However, when a double error condition is detected, the occurrence of the condition is stored and causes the write operation to be aborted. That is, in such instances, either signal EWRITA000 or signal OWRITA000 or both are forced to a binary ZERO. This, in turn, causes AND gate 208-23 or AND gate 208-25 to force a corresponding one of the signals MEREAD010 or MOREAD010 to a binary ZERO. This, in turn, inhibits the writing of the uncorrectable words into the corresponding one(s) of the addressed pair of locations. As mentioned, this preserves the error condition within the uncorrectable word.

As seen from Figure 8c, the resetting of the phase 3 flip-flop 214-26 to a binary ZERO state causes the stop cycle flip-flop 214-27 to reset to a binary ZERO. This signifies the end of the soft error rewrite cycle of operation. As previously discussed, the phase 3 flip-flop 214-26 is reset to a binary ZERO in response to signal RRESET010 from the timing circuits 204.

When the stop cycle flip-flop 214-27 resets, this causes OR gate 214-34 to switch the up count signal ALPHUC010 from a binary ONE to a binary ZERO. As seen from Figure 8c, this causes the read address and write address counters 207-60 through 207-63 in addition to the decode address counter 207-64 to be incremented by one. That is, signal ALPHUC010 causes increment signal RADDUC000 to switch from a binary ONE to a binary ZERO. This results in updating the counters at the end of the soft error rewrite cycle.

The counters 214-10,214-12 and 214-14 continue to operate in synchronism with refresh cycles. Following the occurrence of another 2047 refresh cycles, NAND gate 214-16 again forces command signal ALPCOM000 to a binary ZERO signalling the start of another soft error rewrite cycle. By synchronizing the counters on an odd cou nt which is one less than the maximum count of 2048 (i.e., 2''-1 ), this selects a sequence of address values stored in the refresh, write and decode address counters 207-60 through 207-64 which select every location within stack units 210-20 and 210-40.

The above can be seen by considering an arrangement in which a 4-bit binary counter is used in place of counters 214-10, 214-12 and 214-14. In this arrangement, rewrite command signal is forced to a binary ZERO, every 15 counts (24- 1) rather than 16 which is the maximum count (24).

By way of example, assume that the word size of the memory is 32 and all counters are set to ZERO. To provide a 32 binary addressing capability, the refresh address counter is a 5-bit binary counter. It would generate the following sequence of address values: 0,1,2 12,13,14 4,................28,29,30,31, 0,1 ,2...1 0,11,12,13,1 4,..25,26,27,28,29,...etc.

The count sequence defining the addresses of the locations defined by the 4-bit binary counter at which soft error rewrite cycles are initiated is as follows: 0,15,30,13,28,11,26,9,24,7,22,5,20,3,18, 1,16,31,14,29,1 2,27,8,23,6,21,4,19,2,1 7,0.

From the above, it is seen that during a first pass of refresh counter addresses, a soft error rewrite cycle takes place at the location having address value 15. In a second pass (i.e., after the next 15 counts), a soft error rewrite cycle takes place at the location having address value 30. This continues as shown. By letting the counters free run and detecting each occurrence of a count of 15, a soft error rewrite cycle will be performed on every location in a non-sequential fashion.

It can be seen that during normal operation, the soft error rewrite control circuits of section 214 operate over a long period of time to read out check/correct and rewrite the contents of all of the pairs of locations of the stack units 210-20 and 210-40. This is desirable in orderto minimize interference with normal memory operations. However, in the case of diagnostic operations, it becomes desirable to be able to carry out such operations within a minimum of time and with a minimum of additional apparatus. Utilizing the diagnostic mode control circuits of section 216, test and verification operations can be performed within a minimum of time upon the soft error rewrite control circuits of section 214 in response to several diagnostic commands received from an external source (e.g. CPU) via the bus.

It will be assumed that the operation of the different portions of the controller 200 have been tested and verified. For example, these include the stack units 210-20 and 210-40, the data paths and EDAC circuits 206-12 and 206-14. Such testing can for present purposes be considered to have been carried out in a conventional manner.

Following such testing, a sequence of diagnostic command codes are forwarded to the controller 200 which enable testing and verification of section 214. A first diagnostic command code received has the value "110" and bit 15 set to a binary ONE. At the time of transfer of the diagnostic command code, as well as other diagnostic command codes, the signal applied to line BSYELO is forced to a binary ONE while line BSWRIT remains a binary ZERO. The line BSYELO is used to signal memory controller 200 that the memory address being applied to lines BSAD00-23 includes a diagnostic command code.

As seen from Figure 5, the binary ONE signal BSYEL010 upon being stored in register 208-10, in response to signal MYACKR010, forces signal LSYEL0010 to a binary ONE. This enables decoder circuit 216-2, since it will be assumed that signal LSWRlT010 is a binary ZERO (i.e., the signal applied to line BSWRlTwas a binary ZERO indicative of a read operation).

In response to a code of 110, decoder circuit 216-2 forces signal ALPREFC000 to a binary ZERO. This results in bypass flip-flop 216-20 being switched to a binary ONE state in response to signal BSAD15210. The flip-flop 216-20 forces signal ALPABY100 to a binary ZERO which switches the soft error rewrite control circuits of Figure 4 to an inoperative state. That is, referring to Figure 4, it is seen that signal ALPABY100 when a binary ZERO holds NAND gate 214-16 in a binary ONE state. This, in turn, maintains signal ALPSET i 10 in a binary ZERO state. Since the controller 200 is not in a test mode, signal TESTMM010 is a binary ZERO while signal TESTMM100 is a binary ONE. Therefore, signals TESTMM010 and ALPSET1 10 cause NAND gates 214-20 and 214-21 to force signals ALPCOM200 and ALPCOM100 to binary ONES.This, in turn, inhibits AND gate 214-22 from forcing signal EALPST000 to a binary ZERO thereby inhibiting a soft error rewrite cycle.

In response to the read command, the circuits of section 208 force signals MEREAD01 0 and MOREADOl 0 to binary ZEROS which enable the contents of the pair of locations specified by the address signals loaded into registers 207-40 and 207-41 of Figure 2 to be read out into registers 206-8 and 206-10 and transferred via the sets of lines MUXD00-15 and MUXD16-31 to the bus.

The second diagnostic command code transferred to controller 200 has the value "010". At the time of transfer, again the signal applied to the BSYELO line is forced to a binary ONE while the line BSWRIT is forced to a binary ZERO.

As seen from Figure 5, the signals applied to lines BSYELO and BSWRIT are stored in register 208-10 in response to signal MYACKR010. The decoder circuit 216-2 of Figure 6 in response to the value "010" is operative to force signal SETEDA000 to a binary ZERO. This causes the EDAC mode flip-flop 216-10 to be switched to a binary ONE upon the occurrence of timing signal PULS20210.

As seen from Figure 10, flip-flop 216-10 switches signal EDACM0000 to a binary ZERO. This causes AND gates 216-14 and 216-16 to force signals EDACCK000 and EDACCK100 to binary ZEROS. The signals EDACCK000 and EDACCK1 00 inhibit output AND gates within each of the EDAC circuits 206-12 and 206-14 from transferring the generated check bit signals. This results in the sets of check bit signals MDIECO-05 and MDIOCO-C5 being forced to binary ZEROS. Additionally, signal EDACCK100 is applied to output AND gates within the red and yellow generator circuits 206-20. This inhibits the transfer of error signals MYREDD010 and MYREDR010 to the lines BSREDD and BSREDR.

The memory controller 200 in response to the read command is operative to read out the contents of a pair of locations being addressed to registers 206-8 and 206-10. Thereafter, the register contents are transferred via the sets of lines MUXD00-15 and MUXD1 6-31 to the bus.

The above command is followed by a series of memory write commands at which time line BSWRIT is forced to a binary ONE. The write commands specify successive memory addresses beginning with a starting address (i.e., an all ZERO address) within the memory controller 200. Each of the series of data patterns applied to the lines BSDT00-BSDT31 is coded so as to contain the same single bit error data bit pattern for each word of the word pair being written into memory at the specified addresses.

For example, one of the following series of data patterns 9-40 may be selected to verify the operation of rewrite control section 214. The following series of data patterns, coded in hexidecimal, are used to verify the operation of the EDAC circuits 206-12 and 206-14.

Pattern Read # Write (Corn) ) Y R Remarks 1 02C8 02C8 0 0 NORMAL 2 0420 0420 0 0 NORMAL 3 0548 0548 0 0 NORMAL 4 0810 0810 0 0 NORMAL 5 1008 1008 0 0 NORMAL 6 2004 2004 0 0 NORMAL 7 4002 4002 0 0 NORMAL 8 8001 8001 0 0 NORMAL 9 C002 4002 1 0 BITO 10 0001 8001 1 0 BITO 11 6004 2004 1 0 BIT 1 12 0002 4002 1 0 BIT 1 13 3008 1008 1 0 BIT 2 14 0004 2004 1 0 BIT 2 15 1810 0810 1 0 BIT3 16 0008 1008 1 0 BIT 3 17 0C20 0420 1 0 BIT 4 18 0010 0810 1 0 BIT4 19 06C8 02C8 1 0 BIT 5 20 0020 0420 1 0 BIT 5 21 0748 0548 1 0 BIT 6 22 00C8 02C8 1 0 BIT 6 23 03C8 02C8 1 0 BIT 7 24 0448 0548 1 0 BIT 7 25 05C8 0548 1 0 BIT 8 26 0248 02C8 1 0 BIT 8 27 0460 0420 1 0 BIT 9 28 0508 0548 1 0 BIT 9 29 0830 0810 1 0 BIT 10 Pattern Read # Write(Corr.) Y R Remarks 30 0400 0420 1 0 BIT 10 31 1018 1008 1 0 BIT 11 32 0800 0810 1 0 BIT 11 33 200C 2004 1 0 BIT 12 34 1000 1008 1 0 BIT 12 35 4006 4002 1 0 BIT 13 36 2000 2004 1 0 BIT 13 37 8003 8001 1 0 BIT 14 38 4000 4002 1 0 BIT 14 39 4003 4002 1 0 BIT 15 40 8000 8001 1 0 BIT 15 41 0000 0000 0 1 BITS 0 + 15

DATA PATTERN &num;1 ; 0 12 |C 18 3 &verbar; 4-7 &verbar; 8-11 &verbar; 12-15 DATA BITS It will be noted that the first eight data patterns contain no errors. This series of patterns are followed by pairs of patterns nos. 9-40 each of which contain single bit ZERO and ONE errors in the bit positions indicated. Each pair produces a "yellow" error condition. The last all ZERO pattern is used to generate a "red" error condition.

It will be appreciated that during the verification of the EDAC circuits, the operation of the soft error rewrite control circuits is inhibited. The operation of the EDAC circuits 206-12 and 206-14 is verified by issuing a series of read commands. This reads out the memory locations previously written normal data patterns and then error patterns. However, the error patterns remain in memory since the EDAC circuits 206-12 and 206-14 only correct the data as it is being read out. It is seen that if this were done when the soft error rewrite control circuits were not inhibited, erroneous test results would be obtained (i.e., soft error rewrite control circuits would correct any single bit error). Therefore, when EDAC testing is being performed, the soft error rewrite control circuits operation is inhibited.

Continuing on with the discussion of rewrite control section 214 testing, the memory controller 200 in response to a first write command is operative to write a selected single bit error bit data pattern together with the all ZERO check bit signals into the pair of locations specified by the memory address applied to the address lines BSAD00-23. In a similar fashion, the memory controller 200 in response to a next write command writes the same error bit pattern into the next pair of locations. This continues until all of the memory locations contain the same single bit error pattern and all ZERO check bit signals.

Upon the completion of the writing operation, a third diagnostic code having the value "011" is transferred to controller 200. Again the line BSYELO is forced to a binary ONE while line BSWRIT is forced to a binary ZERO. This diagnostic code conditions decoder circuit 216-2 to force signal RESEDA000 to a binary ZERO.

The result is that the EDAC mode flip-flop 216-10 is reset to a binary ZERO.

As seen from Figure 10, the flip-flop 216-10 switches signal EDACM0000 to a binary ONE. This, in turn, causes AND gates 216-14 and 21 6-1 6 to switch signals EDACCK000 and EDACCK1 00 to binary ONES. At this time, EDAC circuits 206-12 and 206-14, in addition to the red and yellow generation circuits 206-20, are again enabled for normal operation. Additionally, status and indicators are cleared at this time. Also, the contents of the addressed pair of locations are read out to registers 206-8 and 206-10 and transferred to the bus.

Since it is assumed that EDAC circuits have been tested and are operating properly, a last diagnostic command code in the sequence forwarded to controller 200 has the value "110". Also, address bits 15 and 14 have the value "01". Again, the lines BSYELO and BSWRIT are forced to a binary ONE and a binary ZERO, respectively. The decoder circuit 216-2 of Figure 6, in response to the code "110", is operative to force signal ALPRFC000 to a binary ZERO. This causes AND gate 216-19 to force signal ARCCLK010 to a binary ONE in response to timing signal MYDCN N210. Signal ARCCLK010 conditions bypass flip-flop 216-20 and test mode flip-flop 216-22 to switch to a binary ZERO and a binary ONE, respectively, in response to signals BSAD15210 and BSAD14210.

As seen from Figure 4, signal ALPABY100 which is switched to a binary ONE now enables NAND gate 214-16 for operation. Additionally, flip-flop 216-22 forces signal TESTMM010 to a binary ONE and complement signal TESTM M100 to a binary ZERO. This places the section in a test mode of operation wherein the soft error control circuits of section 214 are conditioned to operate in a high speed mode of operation. That is, signal TESTMM010 enables NAND gate 214-20 while signal TESTMM100 disables NAND 214-21.

This means that in response to each refresh command signal REFCOM110, NAND gate 214-20 forces signal ALPCOM200 to a binary ZERO. Thereafter, AND gate 214-22 forces signal EALPST000 to a binary ZERO. This causes phase 1 flip-flop 214-24 to switch to a binary ONE state which initiates a soft error rewrite cycle identical to that shown in Figure 8c.

During the above mentioned cycle of operation, the single bit error pattern is read out from the pair of addressed locations into the registers 206-8 and 206-10. In the manner previously described, the error patterns are corrected by the EDAC circuits 206-12 and 206-14, stored in the right most sections of the registers 206-8 and 206-10 and thereafter written back into the addressed pair of locations. As in normal operation, the addresses for the addressed pair of locations are specified by the address contents of 207-64 of Figure 2.

Following the completion of the rewrite cycle, the counter 207-60 to 207-64 are incremented by 1. Thus, while in the test mode of operation, the soft error rewrite control circuits of section 214 are conditioned to operate in exact synchronism with the refresh circuits of section 205. After a predetermined period of time, the contents of all of the pairs of locations should have been rewritten with the corrected information. Of course, this is true only when the soft error rewrite control circuits are operating properly.

The operation of the soft error rewrite control circuits is verified by a further sequence of diagnostic and read commands. In greater detail, another diagnostic code of 110 is transferred to controller 200. This time bits 15 and 14 are set to the value 00. As previously discussed, the value "110" causes decoder circuit 216-2 to switch signal ALPREFC000 to a binary ZERO. This results in bypass mode flip-flop 216-20 being switched to a binary ZERO while test mode flip-flop 216-22 is switched to a binary ZERO. Accordingly, signal ALPABY100 switches to a binary ONE which enables NAND gate 214-16 of Figure 4. Therefore, the soft error rewrite control circuits are set to normal mode. This readies the memory controller 200 for normal operation.

Next, a series of read memory commands are transferred to controller 200. This causes the contents of each pair of locations to be read out to registers 206-8 206-10. At this time, EDAC circuits 206-12 and 206-14 are operative to check the data patterns for errors.

When soft error rewrite control circuits are operating properly, the EDAC circuits 206-12 and 206-14 operate to detect the absence of single bit errors within the data pattern read out to the registers 206-8 and 206-10. Therefore, signal MYYEL0110 remains a binary ZERO. Accordingly, by monitoring the state of the BSYELO line, the operation of the circuits of section 214 can be verified for this pattern. This is in contrast to the above EDAC testing sequence wherein the EDAC circuits detect the presence of a single bit error which results in signal MYYELO1 10 being forced to a ONE.

Thereafter, the all ZERO pattern is written into all of the memory locations in the same manner as described above. By monitoring the state of the BSREDD line, the operation of the circuits of section 214 are further verified. This is done by checking that no modification of the all ZERO data pattern has taken place and that an uncorrectable error condition is signalled in each case (i.e., the abort circuits 208-44 and 208-45 of Figure 5 preserve the original data pattern).

In response to each such read command, the read out data pattern is transferred to the bus via the multiplexer circuits 206-16 and 206-18. Thereafter, any further checking of the corrected data patterns may be performed by the processor. As shown, any single bit error data pattern and a double bit error data pattern may be written into the stack units 210-20 and 210-40 for verifying the operation of the soft error rewrite control circuits of section 214. It will be obvious that the sequence of data patterns and similar sequence of diagnostic commands can be used to verify the operation of the EDAC circuits.

Many changes may be made to the illustrated embodiment. For example, while the various dåta j~aterns were shown as being supplied via the bus 10, such data patterns could be provided by apparatus includable within the controller 200. Similarly, the checking operation could be performed within the controller 200.

Additionally, the diagnostic apparatus of the invention may be used with different memory organizations, chips, refresh circuits, etc. It will be also obvious that different types of commands, types of command coding or fewer commands may also be used.

The present size for the rewrite counters 214-10,214-12 and 214-l4was selected in order to minimize the interference with normal memory operations and still provide the necessary error protection. The number of stages of the rewrite control section counter may be expanded or reduced as required to minimize interference with normal memory operations. If desired, the counter may be connected to receive programmed counts via the bus 10. That is, the counter could be loaded with a predetermined count which is decremented by one in response to each refresh command signal until a count is reached at which time a rewrite cycle is initiated and the counter is reset to the predetermined count.

Other changes may also be made to the rewrite control section such as omitting the performance of a refresh cycle during each rewrite cycle. However, for simplicity, the refresh cycle was included.

Claims (14)

1. A semiconductor memory system comprising: a dynamic memory including a number of addressable arrays of memory cells arranged in a number of rows and columns; error detection and correction means coupled to the memory for detecting and correcting erros in the contents of the cells read out from said memory during a memory cycle of operation; timing means which provide sequence of timing signals for performing memory cycles of operation; refresh and write control means, including row and column address counter means, which periodically generate refresh command signals under the control of the timing means; and rewrite control means including rewrite counter means which cyclically count the refresh command signals, the timing means generating, on each cycle of the rewrite counter means, a sequence of signals during a rewrite cycle for performing read and write cycles of operations upon the cells within the rows and columns specified by the row and column address counter means, the rewrite counter means having a count modulus which generates rewrite signals at such intervals, relative to the row and column addresses associated therewith, that rewrite cycles occur for all possible combinations of row and column addresses.

2. A system according to Claim 1, wherein the rewrite control means includes decode circuit means which, when the rewrite counter means reaches a predetermined count, generates a rewrite command signal for resetting the rewrite counter means and initiating a rewrite cycle of operation.

3. A system according to either previous claim, wherein the rewrite counter means has a count modulus of 2no 1, where n is the number of stages of the rewrite counter means.

4. A system according to any previous claim, wherein the read/write command control means further includes write abort control means responsive to a signal from the error detection and correction means indicative of an uncorrectable error to inhibit the performance of the write cycle of operation, so as to prevent the writing of uncorrectable errors into the cells within the rows and columns specified by said refresh and write control and thereby preserve original uncorrectable error conditions within those cells.

5. A system according to any previous claim further including initialize control means responsive to a signal indicative of power being applied to the said memory to cause the timing means in response to each refresh command signal to generate signals for applying to the arrays to perform a refresh cycle followed by a write cycle upon the cells having the row and column addresses specified by the refresh and write control means until all the cells of all the arrays have predetermined data written therein.

6. A system according to any previous claim including diagnostic mode control means, and wherein the rewrite control means includes test control means, the diagnostic control means causing, in response to a predetermined type of memory command, the test control means to cause the rewrite control means to perform rewrite cycles of operation at the operating rate of the refresh and write control means, so as to effect rapid verification of the proper operation of the rewrite control means.

7. A system according to Claim 6, wherein the diagnostic mode control means includes a plurality of flip-flops each set in response to a respective diagnostic code memory command, a first of the flip-flops when set defining a high speed test and verification mode, and the test control means including first and second gates one being fed with refresh command signals from the refresh and write control means and the other being fed by the rewrite counter means, the two gates being enabled by the set and reset states respectively of the first flip-flop, and the two gates having their outputs combined to generate signals for initiating rewrite cycles of operation.

8. A system according to Claim 7, wherein a second of the flip-flops is settable for a second diagnostic mode of operation and is connected in series with the rewrite counter means and the test control means to inhibit the operation of the rewrite control means and thereby enable the performance of other diagnostic operations.

9. A system according to Claim 8, wherein the error detection and correction means includes encoder circuit means for generating a group of check code bit signals from the group of data pattern signals to be written into the memory during a memory cycle of operation and wherein a third of the flip-flops is settable to cause the error detection and correction means to force the group of check code bit signals to ZEROS during the writing of the data pattern signals into the memory.

10. A system according to Claim 9, wherein the system receives the data pattern signals coded to include a correctable error pattern for writing into all memory storage locations along with the group of all ZERO check bit signals during successive memory write cycles of operation when the third flip-flop is set, for verifying the operation of the rewrite control means.

11. A system according to Claim 10, wherein the system further includes error generator circuit means, coupled to the error detection and correction means and to the bus, which generate a first predetermined signal on the bus for indicating whether the rewrite control means is operating properly during the read out of the corrected data pattern signals from the memory storage locations during subsequent memory read cycles of operation.

12. A system according to either of Claims 10 and 11, wherein the system receives the data pattern signals coded to include an uncorrectable error pattern for writing into all storage locations along with the group of all ZERO check bit signals during successive memory write cycles of operation when the third flip-flop is set.

13. A system according to any one of Claims 7 to 12 including a plurality of switches, one for each of the flip-flops, each manually settable to simulate the effect of the setting of the corresponding flip-flop.

14. A dynamic memory system substantially as herein described.