GB2071912A - Static induction transistors with improved gate structures - Google Patents

Static induction transistors with improved gate structures Download PDF

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Publication number
GB2071912A
GB2071912A GB8108222A GB8108222A GB2071912A GB 2071912 A GB2071912 A GB 2071912A GB 8108222 A GB8108222 A GB 8108222A GB 8108222 A GB8108222 A GB 8108222A GB 2071912 A GB2071912 A GB 2071912A
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high resistivity
field effect
resistivity layer
semiconductor device
gate
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Verizon Laboratories Inc
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GTE Laboratories Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/7722—Field effect transistors using static field induced regions, e.g. SIT, PBT

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Vertical geometry static induction transistors have gate structures which improve high frequency performance and which simplify device fabrication. Ohmic source (56) and drain (58) contacts are formed on opposite sides of a layer of high resistivity semiconductor material (40) of one conductivity type. Grooves (50), typically V-shaped, are formed in the surface of the high resistivity layer on opposite sides of the source (56). According to one embodiment, the gate junctions (50) are formed by diffusing semiconductor material of the opposite conductivity type into the surfaces of the V-shaped grooves (56). According to another embodiment, the gate junctions are Schottky contacts formed by applying a metallization directly to the surfaces of the V-shaped grooves. <IMAGE>

Description

SPECIFICATION Static induction transistors with improved gate structures This invention relates to gate structures for static induction transistors, and, more particularly, to gate structures which improve device performance and which simplify device fabrication.
The static induction transistor is a field effect semiconductor device which exhibits excellent high power and high frequency capabilities. These devices are characterized by relatively short, high resistivity channels and operate with the channel depleted of carriers. The current-voltage characteristics of the static induction transistor are similar to those of an unsaturated triode. Static induction transistors are disclosed by Nishizawa et al in U.S.
Patent No 3,828,230 issued August 6, 1974.
The static induction transistor (SIT) typically utilizes a vertical geometry. Source and drain contacts are placed on opposite sides of a thin, high resistivity layer of one conductivity type. Gate regions of the opposite conductivity type are diffused into the high resistivity layer on opposite sides of the source.
When a reverse bias is applied to the gate junctions, the depletion region associated therewith extends underneath the source and pinches off the channel between the source and drain.
In order to achieve good control of the drain current, relatively deep gate diffusions are required.
However, the deep gate diffusions have various disadvantages. First, the deeply diffused gate region has an appreciable series resistance which adversely affects high frequency operation. Second, the deep gate diffusions require the entire device to be maintained during the diffusion process at a high temperature for a relatively long period. During this high temperature process, impurities migrate by diffusion from the substrate on which the high resistivity layer is grown into the high resistivity layer, thus reducing the effective thickness of the high resistivity layer. Due to this redistribution of charges, the initial thickness of the high resistivity layer must be increased by increasing the deposition time of the high resistivity layer.
It is a general object of the present invention to provide improved gate structures for static induction transistors.
The present invention provides a field effect semiconductor device comprising: a low resitivity ohmic drain contact; a low resitivity ohmic source contact; a high resistivity layer of semiconductor material of one conductivity type, said high resistivity layer including a first surface with said source contact formed thereon and a second surface with said drain contact formed thereon such that said high resistivity layer between said source and drain contacts defines a channel for conducting a current therebetween and said high resistivity layer further including first and second grooves formed in the first surface of said high resistivity layer on opposite sides of said source contact, said grooves including recessed surfaces in said high resistivity layer; and first and second rectifying gate junctions in re gions proximate the surfaces of said first and second grooves, respectively, whereby said gate junctions have associated de pletion regions which extend into said high resistiv ity layer and which, in response to a reverse bias voltage applied to said gate junctions, control said current by expanding into said channel and estab lishing an associated threshold drain voltage which increases in magnitude as said reverse bias voltage applied to said gate junctions increases in magnitude, whereby said current is cut off when a voltage, lower in magnitude than said threshold voltage, is applied to said drain contact and whereby said current increases without saturating when an increasing voltage, grater in magnitude than said threshold voltage, is applied to said drain contact.
The grooves formed in the high resistivity layer can be V-shaped. The first and second gate junctions can each include a gate region of semiconductor material of the opposite conductivity type. Alternatively, the first and second gate junctions can each include metal adhered to the surfaces of the grooves to form in the grooves metal to semiconductor rectifying contacts.
The invention is illustrated by way of example in the accompanying drawings, in which: Figure 1 is a cross-sectional view of a static induction transistor according to the prior art; Figure2 is a graph illustrating the drain current versus drain voltage characteristics of a static induction transistor; Figure 3 is a cross-sectional view of a semiconductor crystal after formation of V-shaped grooves; Figure 4 is a cross-sectional view of a static induction transistor wherein the gate regions are formed as shallow diffusions in V-shaped grooves; Figure 5 is a perspective view of the static induction transistor shown in Figure 4; Figure 6 is a cross-sectional view of a static induction transistor utilizing planar Schottky gate contacts; and Figure 7 is a cross-sectional view of a static induction transistor wherein Schottky gate contacts are formed in V-shaped grooves.
In the figures, the various elements are not drawn to scale. Certain dimensions are exaggerated in relation to other dimensions in order to present a clearer understanding of the invention.
A static induction transistor with vertical geometry according to the prior art is shown in Figure 1. A high resistivity expitaxial layer 10 is grown on a highly doped substrated 12 of one conductivity type. An ohmic drain contact 14 is applied to the lower surface of the substrate 12. A low resistivity source diffusion 16 of the one conductivity type, is formed in the upper surface of the high resistivity layer 10.
Low resistivity gate diffusions 18 of the opposite conductivity type are formed in the upper surface of the high resistivity layer 10 on opposite sides of the source diffusion 16. An ohmic source contact 20 is made to the source diffusion 16. Ohmic gate contacts 22 are made to the gate diffusions 18. The high resistivity layer 10 provides a channel 24 for current flow between the source and the drain. When a high power device is desired, the structure shown in Figure 1 is repeated many times on a single wafer of semiconductor material, thus providing multiple channels for current flow between the source and drain.
For operation in the one gigahertz frequency range, the high resistivity layer 10 is typically less than 15 microns in thickness and has a resistivity of at least 30 ohm centimeters. In normal operation, a reverse bias voltage is applied to the gate contacts 22. The reverse biased gate junctions have an associated depletion layer which extends into the channel 24 underneath the source diffusion 16 and pinches off the channel 24. Static induction transistors such as the one shown in Figure 1, because of their high resistivity short channels and operation with the channel depleted, exhibit non-saturating triode-like characteristics such as those shown in Figure 2. Drain current is plotted on the vertical axis in Figure 2 as a function of drain voltage on the horizontal axis for various values of gate voltage.
Curve 30 represents a low value of reverse bias gate voltage while curves 32 and 34 represent successively higher values of reverse bias gate voltage. It can be seen that increasing the value of the reverse bias gate voltage has the general effect of increasing the drain voltage which must be applied to the device in orderto cause it to conduct. Further details regarding the construction and operation of static induction transistors are disclosed by Nishizawa et al in U. S.
Patent No 3,828,230; by Nishizawa et al in "Field Effect Transistor Versus Analog Transistor (Static Induction Transistor)", IEEE Transactions on Electron Devices, Vol. ED-22, No.4, April 1975; and by Nishizawa et al in "High Frequency High Power Static Induction Transistor", IEEE Transaction on Electron Devices, Vol. ED-25, No.3, March 1978.
As noted hereinabove, prior art static induction transistors required relatively deep gate diffusions (typically about 4 microns in depth) which had relatively high series gate resistance. Furthermore, during the deep gate diffusions, impurities migrated from the substrate 12 into the high resistivity layer 10, thus reducing the effective thickness of the high resistivity layer 10.
In fabricating a field effect semiconductor device or static induction transistor (SIT) according to the present invention, a slice, or substrate, of single crystal semiconductor material of one conductivity type is provided as a supporting structure. In the following description, silicon is employed as the semiconductor material, although the teachings are obviously applicable to other semiconductor materials. Also, by way of example, the substrate is of N-type conductivity, has a thickness of 250 microns, and has a resistivity of .01 ohm centimeters.
Referring now to Figure 3, there is shown a fragment of a semiconductor wafer during processing of a static induction transistor according to a preferred embodiment of the present invention. A thin, high resistivity epitaxial layer 40 of N-type conductivity is grown on the upper surface of a highly doped substrate 42 of the same conductivity type. For operation in the one gigahertz range, the high resistivity layer 40 should be less than 15 microns in thickness, preferably, about 12 microns.
The high resistivity layer 40 should have a resistivity of at least 30 ohm centimeters, preferably, about 40 ohm centimeters. Grooves 44 are formed in the upper surface of the high resistivity layer 40 at the gate locations. While the objects of the invention can be achieved with grooves of any shape, V-shaped grooves are typically utilized. As shown by D. B. Lee in "Anisotropic Etching of Silicon",dournalofAp- plied Physics, Vol.40, No. 11, 1969, pp.4569-4574, V-shaped grooves can be conveniently etched in silicon monocrystals through a silicon dioxide layer 48 when the wafer has a surface orientation of (100).
The mask is oriented in reference to the (110) wafer flat which is indicative of the (110) crystal direction.
When an equimolar mixture of N2H4 and H2O is used, the etching process will produce self-stopping grooves with an angle of 54.7 from the surface. The depth of the groove depends only on the etching window dimension. The depth of the V-shaped grooves 44 in the SIT of the present invention is typically in the range of 20 to 40 percent of the thickness of the high resistivity layer 40. For one gigahertz operation, the grooves 44 are typically spaced about 5 microns from the source.
A cross-sectional view of a completed SIT according to the present invention is shown in Figure 4.
After the formation of the V-shaped grooves 44, gate junctions are formed by a shallow gate diffusion 50 (P-type conductivity in the present example). The diffusion produces a region of graded resistivity in the high resistivity layer 40. Typically, the gate diffusions 50 are approximately one micron thickness and are confined to the regions near the recessed surfaces of the V-grooves 44. A shallow N-type source diffusion 52 is formed in the region between the V-shaped grooves 54 on the upper surface of the high resistivity layer 40. The source diffusion 52 facilitates the making of a low resistance contact to layer 40. As an alternative to gate and source diffusions, known techniques of ion implantation can be used to form gate and source regions.
Gate metallizations 54 are applied to the surface of the gate diffusions 50 to form ohmic gate contacts.
Source metallization 56 is applied to the surface of source diffusion 52 to form an ohmic source contact.
Drain metallization 58 is applied to the lower surface of the substrate 42 to form an ohmic drain contact.
The high resistivity layer 40 provides a channel 60 for current flow between the source 56 and the drain 58.
A three dimensional view, partly in section, of the SIT of Figure 4 is shown in Figure 5. In the portion of the semiconductor wafer shown in Figure 5, the gate metallization 54 and the associated gate diffusion 50 partially surround the source metallization 56 and the source diffusion 52. This configuration provides good control by the gate of the current flowing between the source and drain. To obtain higher power capability, multiple vertical channels, each controlled by gates located on opposite sides of the channel, can be formed by utilizing known patterns of interlocking source and gate regions.
The operation of the SIT shown in Figure 4 is generally the same as that described hereinabove in connection with the SIT shown in Figure 1. The gate junctions which are formed at the interface between the gate diffusions 50 and the high resistivity layer 40 have an associated depletion region which extends into the high resistivity layer 40. When a reverse bias voltage is applied to the gate junction, the depletion regions expand into the channel 60 and control the current between the source 56 and the drain 58. As illustrated in Figure 2, the bias voltage applied to the gate junctions establishes an associated threshold drain voltage. When the applied drain voltage is greater than the threshold value, drain current flows. Conversely, when the applied drain voltage is less than the threshold value, current does not flow.The magnitude of the threshold drain voltage increases as the magnitude of the applied gate voltage increases. The drain current increases without saturating when an increasing drain voltage, greater in magnitude than the threshold drain voltage, is applied to the drain contact.
The SIT shown in Figure 4 has a gate structure which achieves good current control while avoiding the problems associated with deep gate diffusions.
The shallow gate diffusions 50, typically one micron in thickness, have very small series resistances, thus improving the high frequency response of the device. Also, the shallow gate diffusions 50 require a relatively short processing time, thus avoiding migration of impurities from the substrate 42 into the high resistivity layer 40 during the gate diffusion process.
Another SIT having an improved gate structure is shown in Figure 6. The SIT of Figure 6 includes a high resistivity layer 62, a substrate 64, a source diffusion 66, a source metallization 68, a drain metallization 70, and a silicon dioxide layer 72 which correspond to the high resistivity layer 40, the substrate 42, the source diffusion 52, the source metallization 56, the drain metallization 58, and the silicon dioxide layer 48, respectively, of the SIT shown in Figure 4 and are fabricated in the manner described hereinabove. Openings are made in the silicon dioxide layer on opposite sides of the source metallization 68 by known masking techniques and metal-to-semiconductor rectifying contacts are formed in the openings by applying gate metallizations 74 directly to the high resistivity layer 62.By way of example, the gate metallizations 74 can be aluminum, chromium, nickel, or tungsten. At the interface between the gate metallizations 74 and the high resistivity layer 62, metai-to-semiconductor rectifying contacts or Schottky contacts are formed.
The rectifying contacts, in effect, form gate junctions as in the case of P-type gate diffusions. The high resistivity layer 62 provides a channel 76 for current flow between the source 68 and the drain 70. When a reverse bias voltage is applied to gate metallizations 74, depletion regions 78 extend into the high resistivity layer 62. When the reverse bias voltage has sufficient magnitude, the depletion regions 78 extend into the channel 76 underneath the source diffusion 66 and control the drain current between the source 68 and the drain 70.
The Schottky gate contact has a very low series resistance, thus resulting in an SIT with good high frequency response. Furthermore, the elimination of the deep gate diffusion eliminates the impurity migration from the substrate 64 into the high resistivity layer 62 during the gate diffusion process.
However, the location of the gate junctions on the upper surface of the high resistivity layer 62 results in a reduced degree of drain current control.
A cross-sectional view of a preferred embodiment of the present invention is illustrated in Figure 7. An SIT has a gate structure wherein metal-tosemiconductor rectifying gate contacts are formed in grooves. The SIT of Figure 7 includes a high resistivity layer 80, a substrate 82, a source diffusion 84, a source metallization 86, a drain metallization 88, and a silicon dioxide layer 90 which correspond to the high resistivity layer 40, the substrate 42, the source diffusion 52, the source metallization 56, the drain metallization 58, and the silicon dioxide layer 48, respectively, of the SIT illustrated in Figure 4 and described hereinabove. V-shaped grooves 92 are formed in gate locations on opposite sides of the source diffusion 84 as described hereinabove in connection with the SIT shown in Figure 4.Gate metallizations 94 are formed in grooves 92 so as to form a metal-to-semiconductor rectifying gate contacts or Schottky contacts. The high resistivity layer 80 provides a channel 96 for current flow between the source 86 and the drain 88.
The gate junctions have an associated depletion region 98 which extends into the high resistivity layer 80. When a reverse bias voltage of sufficient magnitude is applied to the gate junctions, the depletion regions 98 expand into the channel 96 underneath the source diffusion 84 and control the drain current passing between the source 86 and the drain 88 as described hereinabove. The SIT shown in Figure 7 has drain current-drain voltage characteristics similar to those shown in Figure 2.
For one gigahertz operation, the high resistivity layer 80 has a thickness of less than 15 microns, typically, about 12 microns, and has a resistivity greater than 30 ohm centimeters, typically, about 40 ohm centimeters. The grooves 92 have a depth which is in the range of 20 to 40 percent of the thickness of the high resistivity layer 80. The gate structure shown in Figure 7 has sufficient depth into the high resistivity layer 80 to provide good control of the drain current. The Schottky gate contacts have extremely low series resistance, thus improving the high frequency response of the SIT. Also, since no gate diffusions are utilized, the problem of impurity migration from the substrate 82 into the high resistivity layer 80 during the gate diffusion process is eliminated.
The static induction transistors described hereinabove, with high resistivity layers having a thickness of about 12 microns and a resistivity of about 40 ohm centimeters, are capable of operation at one gigahertz with a supply voltage of 100 volts. These SITS's have a cutoff frequency in the range of 2 to 3 gigahertz. It is to be understood that thicker high resistivity layers can be used and produce devices having higher voltage capability. However, the maximum operating frequency is lower when the high resistivity layer is thicker. Similarly, thinner high resistivity layers produce devices having lower voltage but higher frequency capabilities. Furthermore, while resistivities in the range of 30 to 40 ohm centimeters are preferred, high resistivity layers having resistivities in the range of 15 to 100 ohm centimeters can be used in static induction transistors.
While there has been shown and described what is at present considered the preferred embodiments of the invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the scope of the invention as defined by the appended claims.

Claims (16)

1. A field effect semiconductor device comprising: a low resistivity ohmic drain contact; a low resistivity ohmic source contact; a high resistivity layer of semiconductor material of one conductivity type, said high resistivity layer including a first surface with said source contact formed thereon and a second surface with said drain contact formed thereon such that said high resistivity layer between said source and drain contacts defines a channel for conducting a current therebetween and said high resistivity layer further including first and second grooves formed in the first surface of said high resistivity layer on opposite sides of said source contact, said grooves including recessed surfaces in said high resistivity layer; and first and second rectifying gate junctions in regions proximate the surfaces of said first and second grooves, respectively, whereby said gate junctions have associated de pletion regions which extend into said high resistiv ity layer and which, in response to a reverse bias voltage applied to said gate junctions, control said current by expanding into said channel and estab lishing an associated threshold drain voltage which increases in magnitude as said reverse bias voltage applied to said gate junctions increases in magnitude, whereby said current is cut off when a voltage, lower in magnitude than said threshold voltage, is applied to said drain contact and whereby said current increases without saturating when an in creasing voltage, greater in magnitude than said threshold voltage, is applied to said drain contact.
2. The field effect semiconductor device as de fined in claim 1 wherein said first and second gate regions each include semiconductor material of the opposite conductivity type with ohmic contacts thereto.
3. The field effect semiconductor device as de fined in claim 2 wherein said low resistivity drain contact includes a substrate of semiconductor mate rial of the one conductivity type contiguous said second surface of said high resistivity layer, said substrate having sufficient thickness to provide mechanical support for said device.
4. The field effect semicondutor device as de fined in claim 3 wherein said grooves are V-shaped.
5. The field effect semiconductor device as defined in claim 4 wherein said high resistivity layer has a thickness and wherein said V-shaped grooves have a depth which is 20 to 40 percent of the thickness of said high resistivity layer.
6. The field effect semiconductor device as defined in claim 5 wherein said gate regions are regions of graded resistivity.
7. The field effect semiconductor device as defined in claim 6 wherein said high resistivity layer is an epitaxial layer.
8. The field effect semiconductor device as defined in claim 7 wherein said high resistivity layer has a resistivity of at least 30 ohm centimeters.
9. The field effect semiconductor device as defined in claim 8 wherein said high resistivity layer has a thickness of less than 15 microns.
10. The field effect semiconductor device as defined in claim 1 wherein said first and second gate junctions each include metal adhered to said surfaces of said grooves, thereby forming metal-tosemiconductor rectifying contacts in said grooves.
11. The field effect semiconductor device as defined in claim 10 wherein said low resistivity drain contact includes a substrate of semiconductor material of said one conductivity type contiguous said second surface of said high resistivity layer, said substrate having sufficient thickness to provide mechanical support for said device.
12. The field effect semiconductor device as defined in claim 11 wherein said grooves are V-shaped.
13. The field effect semiconductor device as defined in claim 12 wherein said high resistivity layer has a thickness and wherein said V-shaped grooves have a depth which is 20 to 40 percent of said thickness of said high resistivity layer.
14. The field effect semiconductor device as defined in claim 13 wherein said high resistivity layer is an epitaxial layer.
15. The field effect semiconductor device as defined in claim 14wherein said high resistivity layer has a resistivity of at least 30 ohm centimeters.
16. The field effect semiconductor device as defined in claim 15 wherein said high resistivity layer has a thickness of less than 15 microns.
GB8108222A 1980-03-17 1981-03-16 Static induction transistors with improved gate structures Withdrawn GB2071912A (en)

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IT (1) IT1138998B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2125621A (en) * 1982-08-20 1984-03-07 Telefunken Electronic Gmbh Method for the manufacture of a field effect transistor
EP0243684A1 (en) * 1986-04-30 1987-11-04 BBC Aktiengesellschaft Brown, Boveri & Cie. Turn-off power semiconductor device and method of making the same
US4870469A (en) * 1984-08-08 1989-09-26 Research Development Corp. Tunnel injection type static transistor and its integrated circuit
CH676402A5 (en) * 1988-11-29 1991-01-15 Asea Brown Boveri Solid state pinch diode - has three zone structure with channel form and schottky electrode regions
US5705830A (en) * 1996-09-05 1998-01-06 Northrop Grumman Corporation Static induction transistors
EP2577735A2 (en) * 2010-05-25 2013-04-10 Ss Sc Ip, Llc Self-aligned semiconductor devices with reduced gate-source leakage under reverse bias and methods of making

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2125621A (en) * 1982-08-20 1984-03-07 Telefunken Electronic Gmbh Method for the manufacture of a field effect transistor
US4870469A (en) * 1984-08-08 1989-09-26 Research Development Corp. Tunnel injection type static transistor and its integrated circuit
EP0243684A1 (en) * 1986-04-30 1987-11-04 BBC Aktiengesellschaft Brown, Boveri & Cie. Turn-off power semiconductor device and method of making the same
CH670333A5 (en) * 1986-04-30 1989-05-31 Bbc Brown Boveri & Cie
US5153695A (en) * 1986-04-30 1992-10-06 Bbc Brown, Boveri Ag Semiconductor gate-controlled high-power capability bipolar device
CH676402A5 (en) * 1988-11-29 1991-01-15 Asea Brown Boveri Solid state pinch diode - has three zone structure with channel form and schottky electrode regions
US5705830A (en) * 1996-09-05 1998-01-06 Northrop Grumman Corporation Static induction transistors
WO1998010468A1 (en) * 1996-09-05 1998-03-12 Northrop Grumman Corporation Static induction transistors
EP2577735A2 (en) * 2010-05-25 2013-04-10 Ss Sc Ip, Llc Self-aligned semiconductor devices with reduced gate-source leakage under reverse bias and methods of making
EP2577735A4 (en) * 2010-05-25 2014-07-02 Power Integrations Inc Self-aligned semiconductor devices with reduced gate-source leakage under reverse bias and methods of making

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Publication number Publication date
CA1149083A (en) 1983-06-28
IT1138998B (en) 1986-09-17
IT8120238A0 (en) 1981-03-10
DE3110123A1 (en) 1982-02-18
JPS56146282A (en) 1981-11-13

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