GB2071370A - PCM Signal Processing - Google Patents

Abstract

A method of preventing errors in a PCM error-correction decoder of the type supplied with successive transmission blocks, each comprising time-interleaved PCM, error- correction and error detection words, wherein the transmission blocks are selectively supplied from first and second data sources such that an error interval is produced as a function of the transition period during which the selection of the data sources is changed over from one to the other. According to this method, the presence of an error in a supplied transmission block is detected, and each of the time-interleaved words included in that transmission block is identified as being erroneous. The transmission block is time de- interleaved to recover a de-interleaved block comprising de-interleaved PCM and error-correction words. An erroneous PCM word in the de- interleaved block is corrected as a function of the remaining non- erroneous PCM and error-correction words in that de-interleaved block. However, the correction of a PCM word is inhibited if the block in which that word is disposed contains at least one word derived from the first data source and another word derived from the second data source.

Description

SPECIFICATION PCM Signal Processing This invention relates to PCM (pulse code modulated) signal processing, and more particularly to such methods and apparatuses particularly suited for use with PCM signal processing apparatus which receives PCM signals in a time-interleaved error-correction code from either of two different data sources.

Recently, digital techniques have been used for the transmission and recording of audio signals.

For example, a rotary-head type video tape recorder (VTR), having a high recording density, can be used to record PCM signals representing audio information. However, when a PCMencoded signal is recorded and subsequently reproduced, the possibility exists that noise, interference, signal drop-out, and the like may be present so as to corrupt some of the reproduced PCM signals. Such loss of data may result in serious errors in the reproduced signal so as to interfere with satisfactory audio reproduction.

In order to minimize this problem of signal loss, error-correction codes have been proposed for use in encoding the PCM signals prior to recording or transmission. By using such errorcorrection codes, erroneous PCM signals which are reproduced or received may be corrected or compensated so as to avoid the aforenoted interference in audio reproduction.

One advantageous error-correction code which has been proposed for such PCM signals is the so-called time-interleaved code. Generally, in the time-interleaved error-correction code, a plurality of channels of PCM signals are produced, each channel carrying a sequence, or series, of successive PCM words which may be derived from an analog-to-digital converter which is used to digitize an input analog audio signal, such as a stereophonic signal. A data block is formed of one word in each channel, which words, typically, appear in parallel-by-word format. These parallel appearing words are used to derive one or more error-correction words, such as parity words.

Then, each PCM word in the data block, as well as the error-correction word (or words) is delayed by a respectively different time delay so as effectively to time-interleave the PCM and error correction words. These time-interleaved words, which are present in parallel-by-word form, are supplied, concurrently, to an error-detection word generator, such as a cyclic redundancy code (CRC) generator so as to produce an error detection word. This error detection word is combined with the time-interleaved PCM and error-correction words so as to form a timeinterleaved transmission block. The timeinterleaved transmission block then may be recorded, transmitted, or otherwise utilized.

When the time-interleaved transmission block is reproduced, or received, the various interleaved words, together with the error-detection word, are examined to determine if an error is present in this particular transmission block. Error detection codes, such as the CRC code, are well-known for providing this error-detection feature. If an error is detected in this transmission block, all of the interleaved PCM and error-correction words are identified as being erroneous, irrespective of whether each such word is, in fact, in error or correct. Then, these time-interleaved, identified, PCM and error-correction words are time deinterleaved so as to reconstruct the original data block.If a de-interleaved PCM word is identified as being erroneous, it can be corrected, by conventional error-correction techniques, such as by parity decoding, provided that none of the other words included in the same block are erroneous. If the reconstructed, de-interleaved block includes two error-correction words, then two erroneous PCM words included in that deinterleaved block can be corrected.

By using the aforementioned time-interleaved encoding technique, effects due to a so-called burst error are minimized. The expression "burst error" generally refers to an error interval, wherein recorded or transmitted data is dropped out, that extends over a period of time sufficient to encompass a plurality of time-interleaved transmission blocks. However, even if all of the PCM and error-correction words included in a number of time-interleaved transmission blocks are distorted, upon reconstructing the original, deinterleaved transmission blocks, it is expected that, generally, only one word in the reconstructed block is distorted. That is, the timeinterleaved encoding technique serves to disperse a burst error throughout many reconstructed blocks.Then, since only a single word in a reconstructed, de-interleaved block is erroneous, such errors may be corrected or compensated by conventional error-correction or compensation techniques.

It is advantageous to utilize PCM signal processing apparatus including the aforementioned time-interleaved encoder/decoder as an adapter to be quickly and simply connected to a VTR such that a conventional VTR may be used to record PCMencoded audio signals. It also is advantageous to use this type of encoder/decoder to receive PCM signals from various sources. For example, the PCM decoder may be connected through a switching arrangement either to the playback section of a VTR or to the output of a PCM encoder. Depending upon the condition of the switch, time-interleaved transmission blocks are supplied to the decoder from one (the VTR) or the other (the PCM encoder) data source.Of course, since the time-interleaved transmission blocks supplied by both sources exhibit the same format, the decoder functions to decode the received transmission blocks, regardless of the particular source from which they are transmitted, and to reconstruct the original audio signals. In many instances, it may be desirable by the user of the apparatus to change over from one source (e.g.

the VTR) to the other. During the transition interval, which exists for a finite time, the decoder effectively is supplied with erroneous transmission blocks. When these erroneous transmission blocks are time de-interleaved, in accordance with the usual procedure, a number of de-interleaved blocks, commencing with the first de-interleaved block at the beginning of the transition interval, contain some PCM and/or error-correction words derived from one source and other PCM and/or error-correction words derived from the other. Furthermore, one or more of the words included in such de-interleaved blocks are erroneous because they have been deinterleaved from those transmission blocks which were supplied during the transition interval.

Nevertheless, if one of these PCM words in the de-interleaved block is erroneous, the errorcorrector of the decoder will attempt to operate in its usual manner to correct this erroneous PCM word. However, it is possible that the erroneous word may be derived from one source whereas other words included in this de-interleaved block are derived from the other source. Typically, the error-correction operation attempts to reconstruct the erroneous PCM word by utilizing the errorcorrection word in conjunction with the remaining non-erroneous PCM words. If all of these words are derived from the same data source, there is no difficulty in reconstructing the correct PCM word.

However, when some of the words are derived from one source and others are derived from the other source, there is no correlation therebetween, and the erroneous word cannot be reconstructed.

When the time-interleaved encoder/decoder of the aforementioned type is used in the example just described, the error-corrector therein attempts to "correct" the erroneous PCM word, even though such a "correction" cannot be carried out. As a result thereof, the "corrected" word is in error and, when converted back to analog form and reproduced by, for example, a loudspeaker, results in an undesired sound. This sound is disturbing and, preferably, should be avoided.

While the aforementioned undesired noise can be muted merely by carrying out a conventional muting operation whenever a change-over operation is carried out from one data source to another, this requires sensing the change-over operation. An additional, special connection must be made to, for example, the VTR, in order to derive a control signal therefrom which can be used to control the muting operation. Since such a control signal normally is not provided, this would require a special reconstruction of the VTR, which is not desired. Moreover, the production of a muting control signal frustrates the attempt to provide the PCM encoder/decoder as a mere "adapter", without special connections.

According to the present invention there is provided a method of preventing errors in a PCM error-correction decoder of the type supplied with successive transmission blocks, each comprising timeinterleaved PCM, error-correction and error detection words, wherein said transmission blocks are supplied from one data source and then from a different data source to produce an error interval determined by the transition period from said one source to said different source, said method comprising: detecting if a supplied transmission block contains an error:: identifying as being erroneous each of the time-interleaved words included in the supplied transmission block which has been detected as containing an error; time de-interleaving each supplied transmission block to recover a de-interleaved block comprising de-interleaved PCM and errorcorrection words; correcting an erroneous PCM word in said deinterleaved block as a function of the remaining non-erroneous PCM and error-correction words in that de-interleaved block: and inhibiting the correction of a PCM word in a deinterleaved block if said block contains at least one word derived from said one data source and another word derived from said different data source.

According to the present invention there is also provided a PCM signal processing apparatus for receiving successive transmission blocks, each comprising time-interleaved PCM, errorcorrection and error detection words, from either of first or second selectable data sources, wherein an error interval is established during the transition period that the selection of data sources is changed over from one to the other, said apparatus comprising:: detecting means responsive to said error detection words for detecting if a received transmission block contains an error; error identifying means for identifying as being erroneous each of the time-interleaved words included in the received transmission block which has been detected as containing an error; de-interleaving means for time de-interleaving each received transmission block to recover a deinterleaved block comprising de-interleaved PCM and error-correction words, erroneous ones of said de-interleaved words being respectively identified; error correcting means coupled to said deinterleaving means for correcting an erroneous PCM word in said de-interleaved block as a function of the remaining non-erroneous PCM and error-correction words in that de-interleaved block; and inhibit means for inhibiting said error correcting means if the de-interleaved block supplied thereto contains at least one word derived from said first data source and another word derived from said second data source.

According to the present invention there is also provided a PCM signal processing apparatus for receiving successive transmission blocks, each comprising time-interleaved PCM, errorcorrection and error detection words, from either of first or second selectable data sources, wherein an error interval is established during the transition period that the selection of data sources is changed over from one to the other, said apparatus comprising:: detecting means responsive to said error detection words for detecting if a received transmission block contains an error; error identifying means for identifying as being erroneous each of the time-interleaved words included in the received transmission block which has been detected as containing an error; de-interleaving means for time de-interleaving each received transmission block to recover a deinterleaved block comprising de-interleaved PCM and error-correct words, erroneous ones of said de-interleaved words being respectively identified; error correcting means coupled to said deinterleaving means and operative to correct an erroneous PCM word in said de-interleaved block as a function of the remaining PCM and errorcorrection words in that de-interleaved block, provided that the total number of erroneous words in that block is less than a predetermined number;; syndrome generating means for generating a syndrome from said PCM and error-correction words in said de-interleaved block; means for producing a syndrome signal if said syndrome differs from a predetermined value; means coupled to said de-interleaving means for producing a no-error signal if none of the words in said de-interleaved block are erroneous; means for supplying an inhibit signal of predetermined duration to said error correcting means in response to the concurrence of said syndrome and no-error signals, whereby the operation of said error correcting means is inhibited for the duration of said inhibit signal; counting means for counting the number of successive transmission blocks which contain errors; means for detecting if said count exceeds a predetermined value representing a predetermined duration of said error interval; and error designating means for designating an error-correction word in a predetermined number of the next received transmission blocks as being erroneous, whereby the number of words identified as erroneous in each de-interleaved block that contains words which are derived from said first and second data source is at least equal to said predetermined amount.

The invention will now be described by way of example with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of PCM signal processing apparatus in which an embodiment of the invention can be used; Fig. 2 is a block diagram of a typical time interleave encoder which can be used in the apparatus of Fig. 1; Fig. 3 is a block diagram of a typical deinterleave decoder which can be used with the apparatus of Fig. 1; Figs. 4A to 4C are schematic timing diagrams which are useful in understanding the operation of the time interleave encoder; Figs. 5A to 5E are timing diagrams which are useful in understanding the operation of the time de-interleave decoder; Fig. 6 is a partial block, partial logic diagram of a decoder which can be used with the apparatus of Fig. 1;; Figs. 7A to 7D are waveform diagrams of various signals produced by elements of the apparatus of Fig. 6; Figs. 8A to 8E are timing diagrams which are useful in understanding one mode of operation of the apparatus of Fig. 6; Fig. 9 is a block diagram of another encoder which can be used with the apparatus of Fig. 1; Fig. 10 is a block diagram of another time deinterleave decoder which can be used with the apparatus of Fig. 1; Figs. 1 1 A and 1 1 B are useful in understanding the operation of the encoder of Fig. 9; Figs. 1 2A to 1 2F are timing diagrams which are used to explain the operation of the decoder of Fig. 10; and Figs. 1 3A to 1 3C are timing diagrams which are used to explain another operation of the decoder of Fig. 10.

Referring now to the drawings, and in particular to Fig. 1, there is illustrated a PCM signal processing apparatus 2 which can be used in conjunction with, for example, a VTR 1 so as to supply PCM-encoded audio signals to the VTR 1 for recording and to receive reproduced PCMencoded signals so as to generate corresponding audio sounds therefrom. The VTR 1 may be of the helical scan type having, for example, two rotary heads (not shown) which record signals in parallel, skewed tracks along a magnetic tape, as is conventional. The VTR 1 includes a record section 4, having suitable recording electronics and servo control systems, for controlling the recording of signals in the aforementioned tracks.

The VTR 1 also includes a playback section 5, including playback electronics and servo control systems, which operate to reproduce the signals that are recorded in the aforementioned tracks.

The record section 4 is coupled to a record input terminal 3, the latter normally being supplied with typical video signals of the type which include periodic horizontal synchronizing signals, vertical synchronizing signals and video information signals. As is recognized, such a composite television signal includes high frequency components.

The playback section 5 is coupled to a playback output terminal 8 such that, when the VTR 1 is utilized in a video signal playback mode, composite television signals are reproduced from the magnetic tape and supplied to the output terminal 8. Usually, the output terminal 8 is coupled to a television receiver, or monitor, to display video pictures corresponding to the reproduced video signals.

The VTR 1 also is provided with a change-over switch 6 having fixed contacts 7a and 7b and a movable contact 7c selectively engageable with either of its fixed contacts. The movable contact 7c is coupled to the output terminal 8 so as to supply to the output terminal 8 the signals which are applied either to the fixed contact 7a or to the fixed contact 7b. As illustrated, the fixed contact 7a is coupled to the output of the playback section 5 and the fixed contact 7b is coupled to the input terminal 3. When the change-over switch 6 is disposed in the configuration illustrated in Fig. 1, the signals which are reproduced by the playback section 5 are supplied from the contact 7a through the movable contact 7c to the output terminal 8.When the switch 6 is changed over such that the contact 7c engages the fixed contact 7b, the signals normally supplied to the record section 4 also are supplied to the output terminal 8. Although illustrated herein as an electro-mechanical switch, it should be appreciated that the change-over switch 6 may be an electronic switch such that its transition interval, that is, the interval during which the movable contact 7c changes over between the fixed contacts 7a and 7b, is relatively brief.

The PCM signal processing apparatus 2 is coupled to the terminals 3 and 8 of the VTR 1 and functions as an adapter thereto. The PCM signal processing apparatus 2 includes an encoding section to produce an encoded PCM signal, the output of this encoding section being coupled to the input terminal 3 via a PCM output terminal 9.

The PCM signal processing apparatus 2 also includes a decoder section, this decoder section having a PCM input terminal 10 coupled to the VTR output terminal 8. The purpose of the PCM signal processing apparatus 2 is to encode an input analog signal, such as an audio signal, in PCM error-correction format, and to supply this PCM-encoded signal to the VTR 1 for recording.

As mentioned above, the VTR 1 is arranged to record video signals which exhibit relatively higher frequencies. Furthermore, as is known, VTR's generally exhibit favourably high recording densities. Consequently, the VTR 1 is particularly useful for recording PCM-encoded audio information.

When the playback section 5 of the VTR 1 reproduces the PCM-encoded audio information, the PCM-encoded signals are supplied via the VTR output terminal 8 to the PCM input terminal 10, such that the decoding section of the PCM signal processing apparatus 2 decodes these recovered PCM signals, and re-converts the decoded signals back to audio analog form.

The encoding section of the PCM signal processing apparatus 2 includes an input terminal 11, to receive an input analog signal, such as an audio signal, the input terminal 1 1 being coupled to an analog-to-digital (A/D) converter 13, an encoder 14 and an amplifier 15. all connected in series, as illustrated. The output of the amplifier 15 is coupled to the PCM output terminal 9. The A/D converter 13 samples the analog audio signal supplied to the input terminal 1 1 and produces a corresponding multi-bit digital word corresponding thereto. Typically, this multi-bit digital word is a PCM word. As one example thereof, each PCM word produced by A/D converter 13 comprises fourteen data bits.

If the input audio signal supplied to the audio input terminal 1 1 is a stereophonic signal comprising left-channel and right-channel signals, the A/D converter 13 generates PCM words representing each sample of the left-channel and the right-channel signals. Although the A/D converter 13 is shown in block form, it may comprise separate left-channel and right-channel filters, sample-and-hold circuits and analog-todigital converters. The output of the AID converter 13 is supplied to the encoder 14 which functions to convert the PCM data supplied thereto into an error-correction format and, moreover, to carry out a time-base compression operation so as to form "empty" or blank periods in the data stream into which are inserted various video synchronizing signals, such as periodic horizontal and vertical synchronizing signals.The encoder 14 thus serves to encode the PCM data in, for example, a time-interleaved error-correction format and, by inserting the aforementioned video synchronizing signals thereinto, to produce a simulated video signal. This simulated video signal is amplified by the amplifier 15 and supplied, via the PCM output terminal 9 and the VTR input terminal 3, to the record section 4 of the VTR 1.

The VTR 1 serves to record the PCM signals, which are encoded in error-correction format, and which include the various video synchronizing signals. It is appreciated that the VTR electronics interprets these encoded PCM signals as simulated video signals. Upon reproduction, these simulated video signals are supplied from the playback section 5 through the VTR output terminal 8 and the PCM input terminal 10 to the decoding section of the PCM signal processing apparatus 2. This decoding section comprises a synchronizing signal separator circuit 16. a decoder 17 and a digital-to-analog (D/A) converter 18, all connected in series, as illustrated. The synchronizing signal separator circuit 16 serves to separate the video synchronizing signals, i.e., the horizontal and vertical synchronizing signals, which had been inserted into the encoded PCM signals for recording. Thus, the decoder 17 is supplied with encoded PCM signals having "empty" or blank data periods therein, these blank periods corresponding to the separated synchronizing signals.

The decoder 17 is compatible with the encoder 14 and operates to time-base expand the encoded PCM signals back to their original time base; and, moreover, the decoder 17 serves to recover the original PCM signals from the errorcorrection code. As will be described herein, the encoder 14 functions to encode the PCM signals in the so-called time-interleaved format. Hence, the decoder 17 functions to time de-interleave these PCM signals. Furthermore, the decoder 17 includes error correction and error compensation circuitry so as to correct errors that might be present in the recovered PCM signals, such as errors which may be due to drop-out, noise or interference. If such errors cannot be corrected, then an approximation of the erroneous PCM signal is produced by the error compensation circuitry, and this approximation is used to replace the erroneous PCM signal.The decoder 17 thus serves to reconstruct the original PCM signals which had been supplied to the encoder 14 by the A/D converter 13.

These reconstructed PCM signals are supplied to the D/A converter 18 wherein they are reconverted back to their original analog audio signal level. For example, the D/A converter 18 may re-convert the corrected/compensated PCM signals back to the original stereophonic leftchannel and right-channel audio signals. These audio signals are supplied to an audio output terminal 12, from which they are amplified in an audio amplifier 19 and used to drive a loudspeaker 20 so as to reproduce audio sounds.

It may be seen that, by recording the original audio signals as digital signals, high fidelity and accurate reproduction of the original signals is obtained from the loudspeaker 20. Furthermore, since the PCM signal processing apparatus 2 is connected merely to the usual VTR input and output terminals 3 and 8, the PCM signal processing apparatus 2 is provided merely as a simple adapter for the VTR 1. Special connections need not be made to the VTR 1; nor need special control signals be obtained therefrom in order to control or synchronize the operations of the VTR 1 and the PCM signal processing apparatus 2.

When the VTR 1 is used to record the encoded PCM data, the reproduced PCM signals are supplied from the playback section 5 to the PCM input terminal 10 when the change-over switch 6 exhibits the configuration illustrated in Fig. 1.

When the change-over switch 6 is operated so as to engage the movable contact 7c with the fixed contact 7b, the encoded PCM signals produced at the PCM output terminal 9 are supplied to the PCM input terminal 10. In this manner the loudspeaker 20 may be used to monitor the PCMencoded audio information which is being recorded by the record section of the VTR 1.

Although the PCM signal processing apparatus 2 is illustrated as being used in conjunction with a VTR 1, it should be readily appreciated that, if desired, the PCM signal processing apparatus may be used with other devices, such as data transmitters, data receivers, and the like, Furthermore, and as will become apparent from the detailed discussion below, the change-over switch 6 may be used to supply encoded PCM signals to the decoding section of the PCM signal processing apparatus 2 either from a first or a second data source. In the application shown in Fig. 1, the first data source comprises the VTR playback section 5; and the second data source comprises the encoder section included in the PCM signal processing apparatus 2. However, and as will be seen, other data sources may be used to supply encoded PCM data to the decoder section of the PCM signal processing apparatus 2.

One example of a portion of the encoder 14 is illustrated in Fig. 2. This illustrated example is arranged to encode the PCM signals supplied from the A/D converter 13 into the timeinterleaved, error-correction format. That portion of the encoder 14 which serves to time-compress the encoded PCM signals and to insert video synchronizing signals into blank periods produced thereby, is not shown. Nevertheless, the example illustrated in Fig. 2 is referred to herein merely as the encoder.

The encoder shown in Fig. 2 comprises a -distributor 22, an error-correction word generator 23. time-delay circuits 24a and 24b, a mixer 25 and an error detection code generator 26. The distributor 22 is coupled to an input terminal 21 and is arranged to receive successive PCM words which may, for example, be supplied thereto by the A/D converter 13 in serial-by-word form. Each word may comprise a plurality of serial or parallel bits, such as fourteen bits. The distributor 22 functions as a demultiplexer to separate, or distribute, the single channel of successive PCM words supplied thereto into separate parallel channels referred to as the left-channel and the right-channel. Each channel thus is provided with a sequence, or series, of PCM words associated with left-channel and right-channel audio information, respectively.In Fig. 2, the sequence, or series, of left-channel PCM words is shown as left-channel SL, and the sequence, or series, of right-channeí PCM words is shown as the rightchannel SR. It will be explained below that successive data blocks are produced at the output of the distributor 22 in successive time periods, these periods being referred to as transmission block periods, each being equal to the time period occupied by a transmission block. A transmission block, for the encoder shown in Fig. 2, comprises a left-channel word Ll and a right-channel word R,, both words being produced concurrently at the output of the distributor 22.

The left-channel SL and the right-channel SR are coupled to the error-correction word generator 23. As one example thereof, the errorcorrection word generator 23 is a parity word generator and is arranged to sum the left-channel and right-channel PCM words L, and R, provided in a data block at the output of distributor 22 in modulo-2 form. Thus, the parity word generator 23 may comprise a conventional modulo-2 adder.

The function of the parity word generator 23 is to generate a sequence, or series, of parity words SP, each parity word P, being produced in response to the modulo-2 addition of the leftchannel and right-channel PCM words such that P=L,(3 R,. The resultant parity word P, is seen to have the same number of bits (e.g. fourteen bits) as each of the left-channel and right-channel PCM words, and each parity word P is particularly related to the PCM words Li and Rl from which it is derived. The parity word Pl may be used to reconstruct an erroneous PCM word, provided that the parity word and the other PCM word are correct.For example, if, during transmission, recording, reproduction and reception of the data block comprising the PCM words Ll and Rl and the parity word Pi, an error is present in the PCM word Ll, the correct version of the PCM word Ll may, nevertheless, be recovered as a function of the non-erroneous PCM word R, and the nonerroneous parity word P, in the recovered data block. Such error correction techniques are known are not further described.

The PCM and parity words which constitute each data block are selectively time-delayed by the time-delay circuits 24a and 24b. In particular, the right-channel series SR and the parity series SP are supplied to the time-delay circuits 24a and 24b, respectively. The left-channel series SL is not supplied to a delay circuit in the example shown in Fig. 2. Stated otherwise, this leftchannel series is delayed by an amount corresponding to zero time delay. The time-delay circuit 24a delays the right-channel series SR by a predetermined amount D: and time-delay circuit 24b delays the parity series SP by a greater amount 2D. D is a time period equal to two transmission block intervals, wherein a transmission block interval is equal to the time interval occupied by a transmission block.A transmission block is similar to a data block, except that the particular words which constitute the transmission block are formed of the respectively-delayed PCM and parity words. That is, the transmission block comprises timeinterleaved PCM and parity words. It is appreciated that the time-delay circuits 24a and 24b serve to time-interleave the respective words. For example, and as will be described further below, if the fourth data block is supplied to the time-delay circuits 24a and 24b, this fourth data block comprising the PCM words L4 and R4 and the parity word P4, the transmission block then produced by the time delay circuits, that is, the time-interleaved transmission block comprising the time-interleaved words, may be represented as the PCM words L4 and R2 and the parity word PO.

In Fig. 2, the resultant time-interleaved transmission block comprises the sequence, or series, of non-delayed left-channel PCM words SL, the delayed sequence, or series, of rightchannel PCM words produced at the output of the time delay circuit 24a and identified as the delayed right-channel series SR1s, and the delayed sequence, or series, of parity words produced at the output of the time delay circuit 24b, this delayed parity series being identified as SP. Of course, in any given transmission block, the PCM and parity words included therein may be identified as L,, Rl-D and Pl#2D.

The interleaved PCM and parity words included in each transmission block are supplied to the error-detection code generator 26. In one example thereof, the error-detection code generator 26 is a CRC generator. The use of error detecting codes, and particularly the CRC code, to detect the presence of one or more errors in a block of data words is well known. For example, the PCM and parity words included in a transmission block, and supplied to the CRC generator 26, may be expressed as a polynomial over a Galois field, this polynomial being divided by a generation polynomial to obtain a remainder which is added to the transmission block as a CRC code word. That is, the CRC code word, together with the PCM and parity words, constitute the time-interleaved transmission block.During reproduction, when this transmission block is reproduced, a polynomial is formed of the reproduced PCM, parity and CRC words, and this polynomial is divided by the same generation polynomial which was used in the CRC generator.

If no remainder is obtained by this division, then it is concluded that the reproduced transmission block does not contain any error. However, if a remainder is produced, then the transmission block contains at least one error. As will be described below, when an error is detected in the reproduced transmission block, a "pointer" or error flag associated with each PCM and parity word is set, thereby identifying each such word in the reproduced transmission block as being erroneous.

The CRC generator 26 generates a sequence, or series, of error detection words, this errordetection series being identified as SC. It may be appreciated that a PCM word included in the leftchannel series SL, together with a PCM word included in the delayed right-channel series Sir", together with a parity word included in the delayed parity series SP,, together with a word included in the error-detection series SC all appear concurrently. As shown in Fig. 2, these words, which exhibit a time-interleaved relationship with each other, constitute a transmission block and are supplied to the mixer 25. The mixer 25 functions as a multiplexer to serialize the words which are supplied thereto in parallel form. The output of the mixer 25 is coupled to an output terminal 27 to supply successive transmission blocks thereto in serial form. If desired, the time occupied by a serialized time-interleaved transmission block produced by the mixer 25 may be equal to a transmission block interval. This is attained if the mixer 25 is supplied with a readout clock signal of a frequency four times the frequency at which each 4-word transmission block is applied thereto.

The serialized transmission blocks provided at the output terminal 27 may be supplied to a synchronizing mixer circuit (not shown) which serves to insert the usual video synchronizing signals into the stream of transmission blocks.

The mixer 25 may operate to carry out a timebase compression of the transmission blocks applied thereto so as to provide blank periods into which the video synchronizing signals are inserted. The circuitry which can be used to carry out such a time-base compression is well known.

Fig. 4A represents successive data blocks formed of the parallel PCM words Ll and Rl and the parity word P. For example, at time to, the data block formed of [ LoRoPo ] is produced, at time t, the data block [ L,R,P, ] is produced, at time t2 the data block [ L2R2P2j is produced, and so on.

The time-delay circuits 24a and 24b impart selective delays of D and 2D to the right-channel PCM word and to the parity word, respectively.

Fig. 4B represents the transmission block which is formed by this time-interleaving of the respective words. Fig. 4B also illustrates the CRC code word C, which is produced by the CRC generator 26 in response to the PCM and parity words of each transmission block. Thus, at time to, the timeinterleaved transmission block [ LoR 2P 4Co ] is produced, at time t the time-interleaved transmission block}L,R~,P~3C ] is produced, at time t2 the time-interleaved transmission block [ L2R0,P#2C2 ] is produced, and so on. It is seen that, in each transmission block, the respective words contained therein exhibit a time-interleaved relationship with respect to each other. In such a time-interleaved transmission block, there is little, if any, correlation between the words therein.

Fig. 4C represents the serialization of successive time-interleaved transmission blocks.

It is appreciated that a blank period is formed between adjacent transmission blocks so as to accommodate video synchronizing signals that may be inserted therein.

Turning now to Fig. 3, there is illustrated one example of a decoder which is compatible with the encoder shown in Fig. 2. It is appreciated that the encoder of Fig. 2 is a time-interleaved error correction encoder. Hence, the decoder shown in Fig. 3 will be recognized as a time-interleaved error correction decoder that is particularly compatible with the Fig. 2 encoder.

The decoder shown in Fig. 3 comprises a distributor 29, an error detector 30, time-delay circuits 31 a and 31 b, an error correction circuit 32, a compensation circuit 33 and a mixer 34.

The distributor 29 is coupled to an input terminal 28 to receive the serialized transmission blocks shown in Fig. 4C, which transmission blocks may be reproduced from a record medium or may be supplied thereto by any other suitable data source. It is appreciated that the serialized transmission blocks supplied to the distributor 29 are substantially free of video synchronizing signals which may have been inserted into the original transmission blocks, the synchronizing signals having been removed by, for example, the synchronizing signal separator circuit 16 (Fig. 1).

The distributor 29 is arranged to distribute the respective PCM, parity and error-detection words into separate, parallel channels. The distributor 29 thus may comprise a demultiplexer that operates in a manner which is inversely related to the operation of the multiplexer that may be included in mixer 25. Thus, the distributor 29 serves to recover successive time-interleaved transmission blocks comprised of the left-channel series SL, right-channel series Sir", the parity series SP, and the error-detection series SC. Such recovered transmission blocks may be represented by the timing diagram of Fig. 4D.

The error detector 30 may comprise a CRC check circuit which is supplied with all of the interleaved words included in a received transmission block. The CRC check circuit operates in the manner discussed broadly above to detect the presence of an error in a received transmission block. In the event an error is detected, the CRC check circuit 30 generates a "pointer" or error flag associated with each PCM and parity word contained in the received transmission block, thereby identifying, or designating, such words as being "erroneous". In one form, the CRC check circuit 30 does not determine which particular word (or words) is erroneous. For time-interleaved error correction purposes, it is sufficient merely to designate all of the words in an erroneous transmission block as being in error. In another form, the particular words which are erroneous are indicated.

The time-delay circuit 31 a is coupled to the distributor 29 so as to impart a time delay of 2D to the left-channel PCM words included in the left-channel series SL. As indicated by the broken line shown in Fig. 3, the "pointer" or error flag associated with these left-channel words likewise is delayed. The time-delay circuit 31 b is disposed to impart a time delay D to the right-channel PCM words included in the right-channel series Sir,1.

The "pointer" or error flag associated with each right-channel PCM word also is delayed. The parity words included in the parity series SP, are not delayed. It is appreciated that the time-delay circuits 31 a and 31 b provide time delays which are inversely related to the time delays imparted by the time-delay circuits 24a and 24b in the encoder of Fig. 2. The time-delay circuits 31 a and 31 b of the decoder serve to time deinterleave the respective words included in each received transmission block. Thus, at the output of the time-delay circuits 31a and 31 b, the original timing relationship of the PCM and parity words comprising each original data block is restored.The time de-interleaved data block comprises delayed left-channel series SL", delayed right-channel series SR111, and nondelayed parity series Sup,. The "pointers" or error flags associated with the time de-interleaved words also are provided at the outputs of the time-delay circuits 31 a and 31 b.

The error correction circuit 32 is coupled to receive each successive time de-interleaved transmission block. For example, the error correction circuit 32 may be a conventional parity decoder which is operable when the pointer or error flag associated with one PCM word supplied thereto is set. When operated, the error correction circuit 32 sums the PCM and parity words included in the time de-interleaved data block, as by modulo-2 addition, to obtain a syndrome. This syndrome then is used to correct the erroneous PCM word included in the time de-interleaved data block. When the erroneous word is corrected, its associated pointer, or error flag, is cleared. As is conventional, the error correction circuit 32 does not operate if the pointer, or error flag, associated with two of the words supplied thereto are set.Likewise, the error correction circuit 32 does not operate if the parity word supplied thereto is identified as being erroneous.

Of course, if the parity word is identified as being erroneous but the PCM words are not, there is no need to correct such PCM words.

The corrected PCM words are supplied from the error correction circuit 32 to the compensation circuit 33, together with their associated pointers, or error flags. If an erroneous PCM word is corrected, its error flag is cleared.

However, if an erroneous PCM word is not corrected, for example, if the error flags associated with two words supplied to the error correction circuit 32 are set, thus making the error correction process impossible, the error flags are not cleared. The compensation circuit 33 functions to approximate a correct value for the erroneous PCM word supplied thereto. As one example thereof, the compensation circuit 33 may be of the "last value hold" type which serves to replace the erroneous PCM word with the lastreceived proper PCM word. For example, if the PCM word LO was correct, but if the nextfollowing PCM word L, cannot be corrected, then the previous value LO is retained and used as a replacement for the incorrect value L,.Since the PCM words represent audio information, and since audio information varies at a relatively slow rate, satisfactory compensation is achieved by this type of approximation. In another example the compensation circuit 33 may be of the socalled "interpolation" type, wherein the correct value of a PCM word is approximated by interpolating, or averaging, those correct PCM words which precede and follow it. For example, if the PCM word L, is incorrect, but the PCM words LO and L2 are correct, then the interpolation-type compensation circuit obtains an average value from the PCM words LO and L2 to approximate the proper value of the PCM word L,.

The respective PCM words produced at the output of the compensation circuit 33 are supplied to the mixer 34 which serves to combine the left-channel and right-channel words supplied thereto into a single output channel. These serialized PCM words are supplied to an output terminal 35, from which they may be converted into analog form and used to drive a loudspeaker or other transducer.

Briefly, in operation, the decoder shown in Fig.

3 is supplied with serialized time-interleaved transmission blocks of the type shown in Fig. 4C.

The distributor 29 de-serializes these transmission blocks to provide, at its respective outputs, the PCM, parity and CRC words shown in Fig.4B. If any of the words included in the received transmission block is erroneous, the CRC check circuit 30 sets an error signal associated with each word in that block. The timeinterleaved PCM and parity words included in each received transmission block are time deinterleaved so as to restore the original timing relationship shown in Fig. 4A. If any of these deinterleaved words had been identified as being erroneous, such identifications remain.

Then, the error correction circuit 32 functions to correct an erroneous PCM word included in a de-interleaved data block. As mentioned above, if two words in a de-interleaved data block are identified as being erroneous, such words are not corrected. Rather, the compensation circuit 33 approximates the correct value of such "uncorrectable" PCM words. The resultant corrected/compensated left-channel and rightchannel PCM words then are mixed, or merged, into a single channel by the mixer 34 and supplied to the output terminal 35.

It may be appreciated that the time-interleaved error correction code which is implemented by the encoder and decoder shown in Figs. 2 and 3, respectively, is advantageous in that burst errors are dispersed. That is, errors of substantial length which might otherwise obliterate a sizable portion of the PCM data are minimized so as to permit error correction and compensation. The timeinterleave error correction code reduces the possibility of recovering a de-interleaved data block containing two or more erroneous PCM words. For example, let it be assumed that the transmission blocks containing the words [ LoR~2P~4 ] and [ L1R#1P#3 ] are detected, by using the CRC code words CO and C1, as being erroneous.Each word included in these transmission blocks thus is identified as being in error. Upon de-interleaving these words so as to recover the original data blocks, it will be seen that in the data block containing the words [ L#3R#3P#3 ] , only the parity word P~3 is erroneous.

In the de-interleaved data block [ L,R,P, ] , only the PCM word R#2 is erroneous. In the deinterleaved data block [ L~,R~,P~, ] , only the PCM word R~, is erroneous. In the data block iL0R0P0 ] only the PCM word LO is erroneous. In the data block [ L,R,P, ] , only the PCM word L, is erroneous.

In each of these five de-interleaved data blocks, only one word contained therein is erroneous.

Such single-error words are readily corrected in the error correction circuit 32. Hence, a burst error of length D is readily correctable. If the burst error exceeds this length, then the compensating circuit 33 functions to compensate erroneous PCM words which cannot be corrected by the error correction circuit 32.

As mentioned above, the PCM signals supplied to the decoder shown in Fig. 3 may be reproduced from, for example, a VTR, Suitable PCM signals may be supplied to the decoder by any other suitable data source. In Fig. 1 , the changeover switch 6 represents one switching arrangement for supplying the PCM signals to the decoder either from the playback section 5 of the VTR 1 or from the encoding section of the PCM signal processing apparatus 2. Stated generally, a change-over switching arrangement may be used to supply time-interleaved transmission blocks of PCM signals from either a first data source, referred to as source #1 , or a second data source, referred to as source #2.In Fig. 1 , the playback section 5 corresponds to the source #1, and the PCM encoding section of the PCM signal processing apparatus 2 corresponds to the source #2. Obviously, other suitable data sources may be used.

When the change-over switch 6 is operated so as to change the particular data source that is coupled to the PCM decoder, such as by changing over from the source #1 to the source #2, an error interval is produced, this error interval having a time duration determined by the transition period of the change-over switch 6.

That is, and as depicted in Fig. 5A, if commencement of the change-over operation occurs at time to, the error interval, or transition period, extends from time to to time t,. At time t1, the change-over switch 6 fully couples the source #2 to the PCM decoder. In Fig. 5A, this error interval, or transition period, is represented by the cross-hatched section. At the beginning of this error interval, transmission blocks derived from the source #1 are supplied to the decoder; and at the completion of this error interval, transmission blocks derived from the source #2 are supplied to the decoder.In the example shown in Fig. 1, the decoder 17 is supplied with transmission blocks from the playback section 5 prior to the error interval; and the decoder 17 is supplied with transmission blocks from the encoding section of the PCM signal processing apparatus 2 following the error interval.

Let it be assumed that the error interval is equal to or less than one transmission block interval. Fig. SB is a timing diagram representing successive time-interleaved transmission blocks that are produced at the outputs of the distributor 29. Those transmission blocks which are derived from the source #1 are represented in the absence of parentheses, and those transmission blocks which are derived from the source #2, that is, those transmission blocks which are reproduced at the outputs of the distributor 29 following the commencement of the transition period, are indicated with parentheses. If it is assumed that the error interval is equal to or less than a transmission block interval, then only one transmission block will be erroneous; i.e., the transmission block that is received immediately following the initiation of the transition period.

Fig. SB identifies those words in this transmission block, which are considered to be erroneous, by the superscript "x". More particularly, the CRC check circuit 30 sets the error flag associated with each of the words L4, R2 and PO. It may be appreciated that signal drop-out during this data error interval will result in the setting of such error flags.

Fig. SC is a timing diagram representing the recovered data blocks which are obtained by deinterleaving the transmission blocks shown in Fig.

5B. As shown, and as is understood, the interleave/de-interleave technique serves to disperse the erroneous words which are contained in each interleaved transmission block, whereby only a single word is identified as being erroneous in various ones of the de-interleaved data blocks. Thus, in the de-interleaved data block [ PoRoLoL only the parity word PO is identified as being erroneous. In the de-interleaved data block [ P, R,L, ] , no words are identified as being erroneous. In the de-interleaved data block [ P2R2L2 ] , only the PCM word R2 is identified as being erroneous. In the de-interleaved data block [ P3R3L3 ] , no words are identified as being erroneous. Finally, in the de-interleaved data block [ P4R4L4 ] , only the PCM word L4 is identified as being erroneous.Since, at most, only a single word in any de-interleaved data block is identified as being erroneous, it is recognized that the error correction circuit 32 functions so as to correct the erroneous PCM words.

However, it is recognized that, during the period 2D, four de-interleaved data blocks are provided with words which are derived from both the source #1 and the source #2. Let the block intervals during which such de-interleaved data blocks are provided be represented as block intervals TB1, TB2, TB3 and TB4, respectively. In the data blocks occupying the block intervals TB, and TB2, the PCM words are derived from the source #1, but the parity words are derived from the source #2. In the data blocks occupying the block intervals TB3 and TB4, only the left-channel PCM words are derived from the source #1. The remaining PCM and parity words are derived from the source #2.It will, therefore, be appreciated that, if the error correction circuit 32 operates during the block interval TB3 so as to "correct" the erroneous right-channel PCM word R2, a proper error correction cannot be achieved. This is because the error correction for the PCM word R2 will be based upon the parity word P2 and the PCM word L2 But, since the data source from which PCM word L2 is derived differs from the data source from which the parity word P2 and the PCM word R2 are derived, the lack of correlation therebetween will prevent the erroneous PCM word R2 from being corrected properly. Moreover, in the error-correction operation carried out by the error correction circuit 32, the resultant "corrected" word R2 may be so distorted that, when converted to an analog signal to drive the loudspeaker 20, a sharp or otherwise undesirable sound will be produced.

That is, because of the error interval caused by the operation of the change-over switch 6, errors will be dispersed throughout a number of deinterleaved data blocks. The error correction circuit 32 will operate in its normal manner in an attempt to correct individual erroneous PCM words. However, the normal operation of this error correction circuit during the block interval TB3 will produce an undesired result. It is a purpose of embodiments of the invention to prevent this result from occurring without requiring any special connections and without requiring special control signals which may be produced either by the change-over switching arrangement or by the VTR with which it is used.More particularly, it is intended to inhibit an improper error correction operation from being carried out on deinterleaved data blocks which contain words that are derived from both the source #1 and the source #2.

A decoder is illustrated in Fig. 6. Those elements in Fig. 6 which are the same as the elements described above with respect to Fig. 3 are identified by the same refernece numerals. In Fig. 6, the distributor 29 is not shown.

Nevertheless, it is appreciated that the distributor 29 is used to provide the time-interleaved leftchannel series SL, the right-channel series SR11, the parity series SP1 and the CRC series SC. In addition to those elements which have been described above, Fig. 6 includes a counter 37, a detector 38, a pulse generator 39, an OR gate 36, a NOR gate 40, a syndrome forming circuit 41, an AND gate 42 and a monostable multivibrator 48.

The counter 37 is coupled to the output of the CRC check circuit 30 to count each pointer, or error signal, that is produced by the CRC check circuit 30 whenever an error in a received transmission block is detected. Although not shown particularly herein, it should be recognized that the CRC check circuit 30 produces an error flag pulse at the end of each transmission block interval. This pulse is converted by suitable circuitry (not shown) so as to be present throughout substantially the entire transmission block interval with which it is associated. This may be obtained by, for example, triggering a one-shot circuit of suitable time constant with the error flag pulse and, moreover, supplying the respective series SL11,SR111 and SP1 through a one-block delay circuit.The output of the oneshot circuit thus will coincide with the outputs of each of these 1-block delayed series.

The output of the counter 37 is coupled to the detector 38, the latter being arranged to detect when the counter 37 attains a predetermined count. As one example thereof, when the count of the counter 37 exceeds a count of two, the detector 38 detects this condition and triggers the pulse generator 39. The pulse generator 39 may be similar to the aforementioned one-shot circuit and, when triggered, generates a simulated pointer, or error flag. The OR gate 36 includes one input coupled to the CRC check circuit 30 and another input connected to the pulse generator 39 to supply either the actual error flag produced by the CRC check circuit 30 or the simulated error flag produced by the pulse generator 39.

The NOR gate 40 is provided with one input connected to receive the pointer, or error flag, associated with each de-interleaved left-channel PCM word included in each de-interleaved data block, another input connected to receive the pointer, or error flag, associated with each deinterleaved right-channel PCM word included in each de-interleaved data block, and another input connected to receive the pointer, or error flag, associated with each de-interleaved parity word in each de-interleaved data block. This latter input is seen to be coupled to the output of the OR gate 36 and, thus, receives either the actual error flag produced by the CRC check circuit 30 or the simulated error flag produced by the pulse generator 39. It may be appreciated that the NOR gate 40 functions as a coincidence circuit to detect when all of these error flags are cleared.

The NOR gate 40 produces a no error signal SD, which is a binary "1" when no error flags are detected, and which is a binary "0" when one or more error flags are detected. The no-error signal SD is coupled to one input of the AND gate 42.

The other input of the AND gate 42 is coupled to the output of the syndrome forming circuit 41.

The syndrome forming circuit 41 is supplied with the PCM and parity words contained in each de-interleaved data block to produce a syndrome by the modulo-2 addition of such words. More particularly, the syndrome forming circuit 41 forms the syndrome P1Q+R1G+L1. In the absence of any errors in the de-interleaved data block, and if all of the words contained in that data block are derived from the same source, the generated syndrome corresponds to a predetermined value.

However, if an error is present in any of the deinterleaved words, or if the data block contains words which are derived from different data sources, then the resultant syndrome will not correspond to this predetermined value. The generated syndrome is supplied to the error correction circuit 32 and is used therein to correct an erroneous PCM word. Furthermore, the syndrome forming circuit 41 produces a syndrome signal SS which is a binary "1" whenever the generated syndrome differs from its predetermined value, and is a binary "0" whenever the generated syndrome corresponds to the predetermined value. This syndrome signal SS is supplied to the AND gate 42 wherein the coincidence between the syndrome signal SS and the no-error signal SD is detected.As is appreciated, the AND gate 42 produces an output when a de-interleaved data block contains no errors, but the generated syndrome for that deinterleaved data block differs from the aforementioned predetermined value.

The monostable multivibrator 48 is coupled to the AND gate 42 and is triggered in response to the output generated by the AND gate 42 to produce an inhibit signal PcE The inhibit signal Pc is supplied to the error correction circuit 32 and functions to inhibit the operation of the error correction circuit 32 for the duration of the inhibit signal. Preferably, the monostable multivibrator 48 exhibits a time constant such that inhibit signal Pc exhibits a duration corresponding to two data block intervals. When the error correction circuit 32 is inhibited, an error correction operation is not performed. Accordingly, if any of the PCM words then supplied to the error correction circuit 32 are identified as being erroneous, such words are not corrected.The compensating circuit 33 then carries out the aforementioned compensating, or approximating, operation so as to replace the erroneous PCM word with an approximated value thereof.

In operation, let it be assumed that the timeinterleaved transmission blocks supplied to the decoder shown in Fig. 6 are derived from the source #1 and then, following the data error interval shown in Fig. 5A, are derived from the source #2. The respective words contained in each time-interleaved transmission block will appear as shown in Fig. SB, with the erroneous data words being identified by the superscript "x".

The de-interleaved words constituting each deinterleaved data block will appear as shown in Fig.

5C. As before, those words which are derived from the source #1 are represented without parentheses, and those words which are derived from the source #2 are represented by parentheses. Fig. SD represents a signal SD which would be produced if the NOR gate 40 is replaced by an OR gate, and Fig. 7A represents the no-error signal SD produced at the output of the NOR gate 40. Figs. 5E and 7B represent the syndrome signal SS produced by the syndrome forming circuit 41 whenever the syndrome generated in response to the de-interleaved PCM and parity words differs from the predetermined value.It is seen that the generated syndrome differs from the predetermined value whenever a de-interleaved word contains an error, and whenever a deinterleaved data block is formed of some words which are derived from one data source and other words which are derived from the other data source. This is expected because, in these conditions, there is no correlation among all of the words in the de-interleaved data block.

In the absence of the present embodiment, the error correction circuit 32 would operate whenever the signals SD and SS (Figs. SD and 5E) coincide. Such an operation will result in the improper "correction" of the PCM word R2 during the block interval TB3. This improper correction is avoided by the embodiment shown in Fig. 6. In particular, the AND gate 42 produces the output signal shown in Fig. 7C. The trailing edge, or negative transition, of the first pulse produced by the AND gate 42 serves to trigger the monostable multivibrator 48 to produce the inhibit pulse Pc for a duration equal to two data block intervals.

Fig. 7D illustrates that the inhibit signal Pc is produced throughout the data block intervals TB3 and TB4. Thus, the error correction circuit 32 is inhibited from operation during the data block intervals TB3 and TB4. Thus, during the data block interval TB3, the PCM word R2 is not corrected and, moreover, during the next-following data block interval TB4, no correction is made, even although, during this data block interval TB4, the generated syndrome differs from its predetermined value. Hence, the undesired sound which would otherwise be produced by the erroneous "correction" of the PCM word R2 during the data block interval TB3 is avoided.

Rather, since the PCM word R2 is identified as being erroneous, and since it is not corrected by the error correction circuit 32, the compensating circuit 33 functions to replace this erroneous PCM word with an approximation thereof. For example, the preceding PCM word R1,which is indicated as being correct, is used again as an approximation for the PCM word R2.

In the foregoing example, it may be sufficient that the inhibit signal Pc exhibits a duration equal to only a single data block period TB3. However, it is preferred that the inhibit signal Pc extend over two data block intervals in order to inhibit the erroneous "correction" of, for example, the PCM word R3 in the event that the data error interval encompasses two transmission blocks. Thus, the NOR gate 40, the syndrome forming circuit 41, the AND gate 42 and the monostable multivibrator 42 serve to inhibit error correction circuit 32 in the event that the data error interval is equal to D/2 or D.

Now, let it be assumed that the data error interval is greater than D. As a particular example, it is assumed that this data error interval is sufficient to produce errors in three successive interleaved transmission blocks.

Fig. 8A is similar to Fig. 5C in that it illustrates the de-interleaved words contained in the deinterleaved data blocks which are produced immediately prior, during and following the aforementioned data error interval. As before, parentheses identify those words which are derived from the source #2, and the superscript "x" identifies those de-interleaved words which are erroneous. It is appreciated that all of the words included in the received transmission blocks [ P0R2L4J, [ PrR3L5 ] and [ P2R4L0j are identified as being erroneous because such transmission blocks are received during the data error interval.

Fig. 8B illustrates the pointers, or error flags, generated by the CRC check circuit 30. As mentioned above, these pointers are produced at the end of each transmission block interval that is detected as being erroneous. Fig. represents the waveform of the no-error signal SD. Since at least one word in each de-interleaved data block during the data block intervals TB1. . TB7 is erroneous the, NOR gate 40 remains at its binary "0" level during these intervals. This is because, during each such interval, at least one error flag is supplied to the NOR gate 40. Fig. 8D represents the syndrome signal SS produced by the syndrome forming circuit 41. During the data block intervals TB1.. TB7, the syndrome generated by the syndrome forming circuit 41 differs from its predetermined value either because at least one de-interleaved word during each interval is erroneous or because some deinterleaved words during these intervals are derived from one data source and other words are derived from the other source.

When the CRC check circuit 30 produces the third error flag at the end of the data block interval TB3, the count of the counter 37 is incremented so as to exceed the predetermined count of two.

The detector 38 detects that the counter 37 now exceeds this predetermined count and, therefore, triggers the pulse generator 39 to produce the simulated error flag shown in Fig. 8E. This simulated error flag is produced after the third error flag is generated and, thus, the simulated error flag extends throughout the data block interval TB4. This simulated error flag is supplied through the OR gate 36 and, thus, is associated with the parity word P3 included in the deinterleaved data block [ P3R3L3 ] .

From Fig. 8A. it is seen that, since the parity words included in the de-interleaved data blocks [ PGRoLo ] and [ P1R1L1 ] are identified as being erroneous, the error correction circuit 32 does not function to correct the PCM words in these blocks. Furthermore, in the data block [ P2R2L2 ] , since two words are identified as being erroneous, the error correction circuit does not operate.

However, in the data block [ P3R3L3j, only the PCM word R3 is identified as being erroneous, Hence, if the error correction circuit 32 is not inhibited, it would attempt to erroneously to "correct" the PCM word R3. Such a correction operation should be inhibited because, as is apparent, this deinterleaved data block contains the PCM word L3 derived from the source #1, and the remaining words derived from the source #2. Since there is no correlation therebetween, any "error correction" will be erroneous. However, by generating the simulated error flag during the data block interval TB4, as shown in Fig. 8E, the error correction circuit 32 interprets the parity word P3, which is associated with this simulated error flag, as being erroneous.Hence, the error correction circuit 32 interprets the de-interleaved data block [ P3R3L3 ] as containing two erroneous words and, therefore, the error correction circuit 32 does not operate to carry out an error correction operation.

The remaining de-interleaved data blocks which are supplied to the error correction circuit 32 a!l contain words which are derived from the same data source, that is, the source #2. Hence, for those data blocks which contain only a single erroneous word, the error correction circuit 32 functions in its normal manner to correct that word.

It is appreciated that, when the error correction circuit 32 is inhibited from operating, the compensating circuit 33 serves to replace uncorrectable PCM words with approximations thereof in the manner described above.

Thus, it is seen that, when the error interval encompasses three or more transmission blocks, an erroneous error correction operation, which might otherwise be carried out, it avoided. In the embodiment described above, the simulated error flag produced by the pulse generator 39 is associated with the de-interleaved parity word.

Although this simulated error flag may be associated with a de-interleaved PCM word, this may frustrate an error compensation operation in some instances and, therefore, is not preferred.

Another example of a time-interleaved encoder is illustrated in Fig. 9. This encoder is arranged to distribute the left-channel and right-channel PCM words into a plurality of left-channel and right channel series. Accordingly, the encoder includes a distributor 22a, which may be similar to aforedescribed distributor 22, to distribute a single channel of PCM words into separate left channel and right-channel sequences SL and SR, respectively. These sequences are supplied to a further distributor 22b which, in turn, produces the left-channel series SL1, SL, and S L3 in response to the sequence SL, and produces the right-channel series SR1, SR2 and SR3 in response to the sequence SR.For example, if the left channel sequence SL comprises the left-channel PCM words L-2x L#1, L#0, L1, L2, L3 L4 L5 and Let and if the right-channel sequence comprises the right-channel PCM words R#2, R#1, R#0, R1, R2, R3, R4, R5 and R,, the distributor 22b serves to distribute such sequential words into the following parallel-by-word data blocks [ L#2R#2L#1 R#1 L0R0 ] , [ L1R1L2R2L3R3j and [ L4R4L5R5L6R8 ] . It may be appreciated that each word in each of these data blocks is provided in a respective one of the series SL1, SR1, SL2, SR2, SL3 and SR3. Thus, each data block is formed of three left-channel words and three right-channel words.

The encoder shown in Fig. 9 also includes parity word generator 23 having a plurality of inputs, each coupled to receive a respective word included in each data block, this parity word generator including, for example, a modulo-2 adder, similar to aforedescribed parity word generator 23. Still further, another errorcorrection word generator 44 is connected to receive each of the words contained in a data block. The error-correction word generator 44 may be, for example, a b-adjacent encoder which generates a parity-type word related to the PCM words supplied thereto. For example, let it be assumed that the data block [ L1R1L2R2L3R3 ] is supplied by the distributor 22 to the encoder 44.

The encoder 44 generates a parity word Q1 which may be expressed as: Q1~~T5L1 (i3T5R1 G+T5R10T4L2Q+T3R2D+T2L30+TR3 wherein T is a matrix of a d-order generating polynomial G(x), d > 3. If d=3, the generating polynomial G(x) is a reduced polynomial on the Galois field GF(2), this reduced polynomial being expressed as G(x)=1 +x+x3, so that T may be expressed as:

T=t0$01011 010 In the expression representing the parity word Qj, T, T2, T3, T4 and T5 all differ from each other.

The respective PCM words, together with the P-parity word generated by the parity word generator 23 and the Parity word generated by the b-adjacent encoder 44, all are supplied to respective time delay circuits 24a. . .24g which impart respective time delays to the words supplied thereto so as to time-interleave the PCM and parity words. More particularly, the leftchannel series SL1 is delayed by OD (i.e., it is not delayed), the right-channel series SR1 is delayed by the amount D, the left-channel series SL2 is delayed by the amount 2D, the right-channel series SR2 is delayed by the amount 3D, the leftchannel series SL3 is delayed by the amount 4D, the right-channel series SR3 is delayed by the amount 5D, the P-parity series SP is delayed by the amount 6D and the Q-parity series SO is delayed by the amount 7D.In these time delay circuits, the delayed amount D is equal to the time occupied by two successive data blocks.

Furthermore, and as is appreciated, the minimum difference between any two time delays is seen to be equal to D.

The time-interleaved PCM and the parity words produced at the outputs of the delay circuits are supplied to the mixer 25 and, additionally, to the CRC generator 26. The CRC generator 26 may be similar to the aforedescribed CRC generator 26 to produce a CRC series SC. Each CRC word included in the series SC is derived from the timeinterleaved PCM and parity words supplied to the CRC generator 26. It will be recognized that these time-interleaved PCM and parity words, together with the generated CRC word, constitute a timeinterleaved transmission block. In the illustrated example, each such time-interleaved transmission block comprises n PCM words, two errorcorrection (or parity) words and one CRC code word. In this particular example n=6. However, and as will be appreciated, n may be any other desirable integer.

The mixer 25 is similar to the aforedescribed mixer 25 in that it serializes each time-interleaved transmission block supplied thereto. Successive, serialized transmission blocks are produced at the output terminal 27 and may be supplied to a time-base compression circuit for the formation of blank periods in the serialized transmission blocks, each blank period having a video synchronizing signal inserted thereinto.

If desired, the error-correction word generator 44 may be another conventional generator and need not be limited solely to a b-adjacent encoder. Regardless of the particular type of error-correction word generators which are used, it should be recognized that, by providing two parity words in each transmission block, the decoder has the capability of correcting two erroneous PCM words which may be contained in each received data block. This capability, coupled with the dispersal of burst errors due to the timeinterleaved code results in an enhanced error correction scheme.

In the examples shown in Fig. 9, the mixer 25 produces a serialized transmission block of the type detected in Fig. 11 A. If D is the time delay equal, effectively, to two data block intervals, then. at the time that the distributor 22b supplies the data block [ L1R1L2R2L3R3 ] , the timeinterleaved transmission block produced at the output of the mixer 25 is [ L1 R##L#14R#16L#21R#27P#35Q#1C1 ] . The The simulated video signal which is produced in response to this serialized transmission block appears as shown in Fig. 11 B.It is seen that each serialized transmission block corresponds to a "line interval" of video information, the transmission block itself being identified by reference numeral 46, being preceded by a data synchronizing signal 45, being followed by a white-level reference signal 47, and being included in the line interval defined by horizontal synchronizing signals HD.

PCM-encoded signals having the waveforms shown in Fig. 11 B are easily recorded by a conventional VTR.

One example of a decoder which is compatible with the encoder shown in Fig. 9 and which is readily arranged to decode each serially-received transmission block shown in Fig. 11 A is illustrated in Fig. 10. This decoder comprises a distributor 29, a CRC check circuit 30, time-delay circuits ..... .31g, an error correction circuit 32, an error compensation circuit 33 and a mixer 34. The distributor 29 is similar to the aforedescribed distributor shown in Fig. 3, except that the distributor 29 of Fig. 10 serves to demultiplex each received time-interleaved transmission block into n parallel PCM words, two parity words and one CRC word. In the example described herein, n=6.

Thus, the transmission block shown in Fig. 1 1A is supplied, in parallel-by-word format, at the multichannel outputs of the distributor 29, these outputs corresponding to the series SL" SR", So,2, Sir12, So,3, Sir,3, SPr, S01 and SC, respectively.

All of the time-interleaved words which are contained in the received transmission block are supplied to the CRC check circuit 30. The CRC check circuit 30 functions in a manner similar to that described hereinabove to designate, or identify, all of the words contained in the received time-interleaved transmission block as being erroneous. That is, the CRC check circuit 30 detects an error in a received transmission block and, when an error is detected, the pointer, or error flag, associated with each word contained in the received transmission block is set.

The time-delay circuits 31a. . 31g are arranged to impart time delays to the timeinterleaved words included in each received transmission block, which time delays are inversely related to the time delays which were imparted by the encoder shown in Fig. 9. Thus, each left-channel PCM word included in the series SL,, which words had not been subjected to any time delay in the encoder, now are subjected to a maximum time delay 7D by the time-delay circuit 31 a. The right-channel PCM words included in the series Sir", which had been subjected to an encoder time delay of D time units now are subjected to a time delay of 6D by the time-delay circuit 31 b. In similar fashion, the series SL12 is subjected to a time delay of 5D by the time-delay circuit 31 c, the series SR,2 is subjected to a time delay of 4D by the time-delay circuit 31 d, the series SL13 is subjected to a time delay of 3D by the time-delay circuit 31 e, the series SR,3 is subjected to a time delay of 2D by the time-delay circuit 31 f, the series SP, is subjected to a time delay of D by the time-delay circuit 319, and the series SQ, is subjected to a time delay of OD.

Thus, the original time-aligned data blocks, comprised of time de-interleaved PCM and parity words, are produced sequentially at the outputs of the time-delay circuits 31 a.. .31 g. Each time de-interleaved block comprises the delayed series SL", the delayed series SR111, the delayed series SL112, the delayed series SR112, the delayed series SL113, the delayed series Sir,3, the delayed series SP,1 and the non-delayed parity series SQ1, each time de-interleaved word in these series being accompanied by its respective pointer or error flag which also is provided at the output of each timedelay circuit, ..... .31 g.

The error correction circuit 32 is coupled to receive the de-interleaved PCM and parity words included in each data block, together with the error flags associated with such de-interleaved words. It will be appreciated that, since the error correction circuit 32 is supplied with two parity words P and Q~, two erroneous PCM words included in a de-interleaved data block may be corrected. For example, the error correction circuit 32 may form a first syndrome from the PCM words and the P-parity word included in the deinterleaved data block; and it may also form a second syndrome from the PCM words and the Qparity word included in that data block. These syndromes then can be used to correct two erroneous PCM words.Thus, a burst error having a maximum time-length of 2D, that is, a burst error which affects four successive transmission blocks, may be corrected.

If three or more PCM words in a de-interleaved data block are erroneous, or if the parity words in a data block are erroneous, the error correction circuit 32 does not operate to correct the PCM words. Accordingly, those PCM words which are erroneous and whose error flags are set are supplied to the error compensation circuit 33. The error compensation circuit 33 may be similar to the aforedescribed error compensation circuit which functions to approximate a correct value for an uncorrectable PCM word. The corrected/compensated PCM words then are supplied by the error compensation circuit 33 to the mixer 34 whereat they are multiplexed into a single PCM channel and supplied to the output terminal 35. This single channel of PCM words then may be converted into analog form and used, for example, to drive the loudspeaker 20.

The example of the invention, described hereinabove with respect to Fig. 6, is readily arranged for use with the time-interleaved encoder/decoder arrangement shown in Figs. 9 and 10. The example of Fig. 6 may be modified such that syndrome forming circuit 41 is constructed as two separate syndrome forming circuits, one for forming the syndrome in response to the P-parity words and the other for forming the syndrome in response to the Q-parity words.

The NOR gate 40 is supplied with the error flag associated with each PCM and parity word, and the monostable multivibrator 48 is provided with a time constant having a period of, for example, ten data block intervals. Also, the pulse generator 39 generates a simulated error flag having a duration of, for example, nine data block intervals.

The manner in which examples of the invention operate with the decoder shown in Fig. 10 now will be briefly described. Fig. 1 2A is a timing diagram representing successive de-interleaved data blocks. The series of de-interleaved parity and PCM words are shown as the series SQ1, SP11, SR113, SL113, SR112, So1,2, Sir"1 and SL111, each series having its associated time delay illustrated thereon. The solid lines represent those words which are derived from the source #1, and the broken lines represent those de-interleaved words which have been derived from the source #2.As before, it is assumed that time-interleaved transmission blocks first are supplied to the decoder from the source #1 and then, during a transition period which establishes the error interval represented by the cross-hatched areas in Fig. 1 2A, successive transmission blocks are supplied from the source #2. In the example shown in Fig. 1 2A, it is assumed that the data error interval affects only a single, received timeinterleaved transmission block. Fig. 1 2A illustrates the particular data blocks into which the errors due to this transition interval are dispersed. For convenience, the parity series S is used as a reference because this series is not delayed by the decoder shown in Fig. 10.

Fig. 128 illustrates the no-error signal SD produced by, for example, the NOR gate 40 in response to successive de-interleaved data blocks. Fig. 1 2C illustrates the syndrome signal SS, formed by the syndrome forming circuit in response to the de-interleaved P-parity series Sup". It is seen that this syndrome signal SS, commences at the beginning of the period TD2, that is, the syndrome signal SS, commences with the error in the delayed P-parity series. Fig. 1 2D illustrates the syndrome signal SS2 formed by the syndrome forming circuit in response to the Qparity series SQ,.It is seen that the syndrome signal SS2 commences at the beginning of the period TD1,th that is, this syndrome signal commences with the detected error in the deinterleaved Parity series 501. Both the syndrome signal SS, and the syndrome signal SS2 terminate when the last error in the deinterleaved data blocks is detected, that is, the syndrome signals terminate after the error in the delayed series SL111 is detected. It is assumed that the only errors which are present in the deinterleaved data blocks are those represented by the cross-hatched areas.

When the example shown in Fig. 6 is used with the decoder of Fig. 10, it is assumed that the AND gate 42 is supplied with the syndrome signal SS, (Fig. 1 2C) and with the no-error signal SD (Fig.

12A). The resultant output of the AND gate 42 thus appears as shown in Fig. 1 2E. The initial negative-going transition in the output of the AND gate 42 (Fig. 1 2A) is used to trigger the monostable multivibrator 48 which generates the inhibit pulse Pc shown in Fig. 1 2F. It is assumed that the time constant of the monostable multivibrator 48 is equal to five periods TD, that is, it is equal to the time interval occupied by ten successive data blocks. Thus, the error correction circuit 32 is inhibited by the inhibit pulse Pc from the time that the first de-interleaved erroneous PCM word is received in the series Sir"3 until the time that the last de-interleaved erroneous PCM word (included in series So",) is received.From Fig. 1 2A, it is seen that, during the duration of the inhibit pulse Pct each de-interleaved data block comprises at least one PCM word derived from the source #1 and the remaining PCM words derived from the source #2. It is recalled that, when a data block contains PCM words derived from different data sources, there is no correlation among all of such PCM words and, therefore, error correction thereof cannot be carried out properly. To avoid an erroneous "correction", the inhibit pulse Pc prevents the error correction circuit 32 from operating during the interval that such mixed PCM words are present.

From Figs. 1 2A and 1 2F, it is appreciated that, during the periods TD, and TD2, no error correction is needed because, during these periods, the only errors which are present are errors in the parity words. During the periods ..... .TD7, errors are present in one PCM word contained in those de-interleaved data blocks which are produced during the first half of each such period. During normal operation, the error correction circuit 32 operates to correct such erroneous PCM words. However, each deinterleaved data block which is produced during the intervals..... .TD, includes at least one PCM word derived from the source #1 and the remaining PCM words derived from the source #2. Since there is no correlation between the data sources, an erroneous PCM word in such data blocks cannot be corrected.Accordingly, to avoid an erroneous "correction" of such PCM words, the error correction circuit 32 is inhibited by the inhibit pulse Pc during these periods ..... .TD7. Nevertheless, even although an erroneous PCM word is not corrected by the error correction circuit 32, a close approximation of the correct PCM word is substituted therefor by the error compensation circuit 33.

During the period TD8, the PCM word included in the series SL111 is erroneous. However, in the de-interleaved data block which contains this PCM word, all of the remaining PCM and parity words are derived from the same data source, that is, all of the words included in this data block are derived from the source #2. Hence, the erroneous PCM word included in the series Sol", may be corrected by the error correction circuit 32 in accordance with the usual parity or badjacent error correction operation.

Although not shown herein, it will be recognized that, if the data error interval exhibits a length equal to D, for example, the no-error signal SD remains at its binary "0" level throughout the interval defined by the syndrome signal SS2.

Hence, the output of the AND gate 42, as shown in Fig. 1 2E, likewise remains at its binary "0" level. Consequently, the monostable multivibrator 48 is not triggered, and the inhibit pulse Pc is not produced.

Nevertheless, the occurrence of a data error interval equal to D or more is detected by the combination of the counter 37 and the detector 38 (Fig. 6), described above. For example, let it be assumed that the data error interval is equal to 2.5D, as represented in Fig. 1 3A. The CRC check circuit 30 thus detects errors in each of five successive received transmission blocks.

Now, if the error correction circuit 32 is not inhibited, it is seen that, in the de-interleaved data block produced during the latter half of the period Tod3, the PCM word included in the series Sir13 is in error and is derived from the source #2, but all of the remaining PCM words are correct and are derived from the source #1. The error correction circuit 32 would attempt to correct this erroneous PCM word in the series Sir13 during the latter half of the period TD3. However, this error correction operation would be improper because of the mixture of data sources from which the words included in this de-interleaved data block are derived.Likewise, in the de-interleaved data block received during the latter half of the period TD4, the PCM words included in the series SRr,3 and SL"3 both are erroneous, but none of the remaining words in this de-interleaved data block are in error. The error correction circuit 32 normally operates to correct these two erroneous PCM words in response to the P-parity and Qparity words as well as the remaining nonerroneous PCM words included in this data block.

However, such an operation will produce an erroneous "correction" of these PCM words because of the fact that these erroneous words are derived from the source #2, but the remaining PCM words included in this data block are derived from the source #1. The lack of correlation between the data sources prevents proper error correction. The foregoing erroneous errorcorrection operation will be carried out for the two PCM words which are identified as being erroneous in the de-interleaved data blocks which are produced during the latter half of each of the periods TD5, TD, and TD,.

Embodiments of the the invention can operate to prevent such erroneous error correction operations during these periods. Thus, when the CRC check circuit 30 detects the presence of an error in the fifth received transmission block, so as to increment the counter 37 to a count of five at a delayed time 2.5D following the reception of the first erroneous transmission block, the detector 38 detects this predetermined count to trigger the pulse generator 39. The pulse generator 39 generates a simulated error flag having a duration that terminates at the delayed time 7D. This simulated error flag is associated by a suitable OR gate, such as an OR gate analogous to aforedescribed OR gate 36, with the Parity words, as shown in Fig. 1 3B.Hence, during the latter half of each of the periods TD3, TD4,TD6, TD6 and TD7, the Q-parity words are identified as being erroneous. During the latter half of each of these periods, two PCM words in each deinterleaved data block also are identified as being erroneous. Now, since the Q-parity word also is erroneous for each of these data blocks, the error correction circuit 32 cannot operate to correct both erroneous PCM words. Hence, these PCM words are not corrected and, therefore, an otherwise improper correction operation is inhibited. The uncorrectable PCM words are, nevertheless, replaced by close approximations thereof as a result of the operation of the compensation circuit 33.Accordingly, each deinterleaved data block which contains some words derived from the source #1 and other words derived from the source #2 is not errorcorrected. This avoids an erroneous error correction operation and, therefore, prevents the generation of an undesired sound due to an erroneously-corrected PCM word.

Fig. 1 3C represents a modification when used with the decoder of Fig. 10, in that the simulated error flag generated by the pulse generator 39 is added to the error flag associated with each word contained in the sixth received transmission block. This has the effect of "enlarging" each error flag so as to extend for a duration of 3D rather than the actual duration of 2.5D. It is seen, from Fig. 1 3C, that each de-interleaved data block produced during the periods TD3,TD4,TD#, TD, and TD, contains three erroneous PCM words.

Although the error correction circuit 32 is capable of correcting two erroneous PCM words in each de-interleaved data block, the presence of three erroneous PCM words prevents the error correction circuit from operating.

In the example described hereinabove with respect to Fig. 1 3A, it may be stated, generally, that when the CRC check circuit 30 detects the presence of an error in each of five successive, received transmission blocks, the Q-parity word included in the next-following m transmission block is designated as being erroneous. In the example shown in Fig. 1 3A, the Q-parity word is designated as being erroneous in the nextfollowing nine transmission blocks. This results in "enlarging" the error flag associated with the 0parity words in the manner shown in Fig. 1 3B.

That is, the error flag associated with the Q-parity words is set during the reception of fourteen successive transmission blocks. Consequently, in each de-interleaved transmission block that contains some words derived from the source #1 and other words derived from the source #2, at least three words in each such block are identified as being erroneous. It is recalled that the error correction circuit 32 cannot operate to correct more than two erroneous PCM words in any deinterleaved data block.

Various modifications are of course possible.

For example, in the foregoing, the basic or minimum time delay untit D has been assumed to be equal to the time period occupied by two transmission or data blocks. That is, D has been assumed to be equal to two transmission block intervals. If desired, other suitable delays may be used so as to increase the correctable length of the burst error interval which might be produced as a result of the transition between data sources.

As another modification, in the examples shown in Figs. 9 and 10, the PCM series ..... SR3 and the parity series SP may be interleaved to produce an interleaved sub-block, and the respective PCM and parity words in each timeinterleaved sub-block may be further interleaved with the parity series SQ to produce the resultant time-interleaved transmission block. Furthermore, although parity words have been described as the error-correction words included in each transmission block, error correction words derived by other error-correction techniques may be used.

Claims (23)

Claims

1. A method of preventing errors in a PCM error-correction decoder of the type supplied with successive transmission blocks, each comprising time-interleaved PCM, error-correction and error detection words, wherein said transmission blocks are supplied from one data source and then from a different data source to produce an error interval determined by the transition period from said one source to said different source, said method comprising:: detecting if a supplied transmission block contains an error; identifying as being erroneous each of the time-interleaved words included in the supplied transmission block which has been detected as containing an error; time de-interleaving each supplied transmission block to recover a de-interleaved block comprising de-interleaved PCM and errorcorrection words; correcting an erroneous PCM word in said deinterleaved block as a function of the remaining non-erroneous PCM and error-correction words in that de-interleaved block; and inhibiting the correction of a PCM word in a deinterleaved block if said block contains at least one word derived from said one data source and another word derived from said different data source.

2. A method according to claim 1 wherein said step of correcting an erroneous PCM word includes generating a syndrome from said PCM and error-correction words in said de-interleaved block, and wherein said step of inhibiting the correction of a PCM word comprises sensing if said syndrome differs from a predetermined value, sensing the absence of an erroneous word in said de-interleaved block, and producing an inhibit signal of predetermined duration in response to the sensed absence of an erroneous word when said syndrome differs from said predetermined value to inhibit the correction of PCM words for the duration of said inhibit signal.

3. A method according to claim 2 wherein each de-interleaved block comprises two PCM words and one error-correction word, and wherein said predetermined duration of said inhibit signal is equal to the time interval occupied by two successive de-interleaved blocks.

4. A method according to claim 1 wherein each de-interleaved block comprises n PCM words and two error-correction words such that two erroneous PCM words in said de-interleaved block are correctable as a function of the remaining non-erroneous PCM words and the nonerroneous two errror-correction words.

5. A method according to claim 4 wherein said step of inhibiting the correction of a PCM word comprises generating a syndrome from said PCM words and a predetermined one of said errorcorrection words, and sensing if said syndrome differs from a predetermined value, sensing the absence of any erroneous words in said deinterleaved block, and producing an inhibit signal of a duration substantially equal to the time interval occupied by a predetermined number of successive de-interleaved blocks in response to the sensed absence of any erroneous words when said syndrome differs from said predetermined value.

6. A method according to claim 1 wherein said step of inhibiting the correction of a PCM word comprises counting the number of successive transmission blocks which contain errors, detecting if said count exceeds a predetermined value, designating an error-correction word in at least the next-supplied transmission block as being erroneous, whereby at least two words in a de-interleaved block containing words derived from said one and said different data sources are identified as being erroneous, and inhibiting the correction of a PCM word contained in a deinterleaved block having at least two erroneous words therein.

7. A method according to claim 6 wherein said step of time de-interleaving each supplied transmission block comprises delaying each word contained in said supplied transmission block by a respectively different time delay, the minimum difference between two respective time delays being equal to D, wherein D is the time period occupied by a predetermined number of successive transmission blocks, said predetermined value being at least equal to said predetermined number.

8. A method according to claim 4 wherein said step of time de-interleaving each supplied transmission block comprises delaying each word contained in said supplied transmission block by a respectively different time delay, the minimum difference between two respective time delays being equal to the time period occupied by a predetermined number of successive transmission blocks, and wherein said step of inhibiting the correction of a PCM word comprises counting the number of successive transmission blocks which contain errors, detecting if said count exceeds said predetermined number, designating an error correction word in each of the next m transmission blocks as being erroneous (m=the number of transmission blocks supplied during the largest of said time delays), whereby at least three words in a de-interleaved block containing words derived from said one and said different data sources are identified as being erroneous, and inhibiting the correction of a PCM word contained in a de-interleaved block having at least three erroneous words therein.

9. A method according to claim 4 wherein said step of time de-interleaving each supplied transmission block comprises delaying each word contained in said supplied transmission block by a respectively different time delay, the minimum difference between two respective time delays being equal to the time period occupied by a predetermined number of successive transmission blocks; and wherein said step of inhibiting the correction of a PCM word comprises counting the number of successive transmission blocks which contain errors, detecting if said count exceeds said predetermined number, designating all of the words in the next-supplied transmission block as being erroneous, whereby at least three words in a de-interleaved block containing words derived from said one and said different data sources are identified as being erroneous, and inhibiting the correction of a PCM word contained in a de-interleaved block having at least three erroneous words therein.

10. A PCM signal processing apparatus for receiving successive transmission blocks, each comprising time-interleaved PCM, errorcorrection and error detection words, from either of first or second selectable data sources, wherein an error interval is established during the transition period that the selection of data sources is changed over from one to the other, said apparatus comprising:: detecting means responsive to said error detection words for detecting if a received transmission block contains an error; error identifying means for identifying as being erroneous each of the time-interleaved words included in the received transmission block which has been detected as containing an error; de-interleaving means for time de-interleaving each received transmission block to recover a deinterleaved block comprising de-interleaved PCM and error-correction words, erroneous ones of said de-interleaved words being respectively identified; error correcting means coupled to said deinterleaving means for correcting an erroneous PCM word in said de-interleaved block as a function of the remaining non-erroneous PCM and error-correction words in that de-interleaved block; and inhibit means for inhibiting said error correcting means if the de-interleaved block supplied thereto contains at least one word derived from said first data source and another word derived from said second data source.

1 Apparatus according to claim 10 wherein said error correcting means includes syndrome generating means for generating a syndrome from said PCM and error-correction words in said deinterleaved block, and wherein said inhibit means comprises means for producing a syndrome signal if said syndrome differs from a predetermined value, means coupled to said de-interleaving means for producing a no-error signal if none of the words in said de-interleaved block are erroneous, and means for producing an inhibit signal of predetermined duration in response to the concurrence of said syndrome and no-error signals, whereby the operation of said error correcting means is inhibited for the duration of said inhibit signal.

12. Apparatus according to claim 1 1 wherein said error identifying means produces a respective error signal associated with each PCM and errorcorrection word in a received transmission block that has been detected as being erroneous, the respective error signals remaining associated with the de-interleaved PCM and error-correction words, and wherein said means for producing a no-error signal comprises coincidence means supplied with the error signals associated with the PCM and error-correction words of each deinterleaved block to detect the absence of error signals associated with said words.

13. Apparatus according to claim 12 wherein said coincidence means comprises a NOR gate.

14. Apparatus according to claim 12 wherein said means for producing an inhibit signal comprises AND gate means coupled to receive said syndrome signal and said no-error signal, and pulse generating means coupled to the output of said AND gate means.

15. Apparatus according to claim 14 wherein each de-interleaved block comprises two PCM words and one error-correction word, and wherein said pulse generating means includes monostable multivibrator means having a time constant equal to the time interval occupied by two successive de-interleaved blocks.

16. Apparatus according to claim 11 wherein each de-interleaved block includes two errorcorrection words, wherein said syndrome generating means generates a syndrome from said PCM words and a predetermined one of said error-correction words, and wherein said means for producing an inhibit signal produces said inhibit signal of a duration substantially equal to the time interval occupied by a predetermined number of successive de-interleaved blocks.

17. Apparatus according to claim 10 wherein said error correcting means does not operate if two or more words in a de-interleaved block supplied thereto are identified as being erroneous, and wherein said inhibit means comprises counting means for counting the number of successive transmission blocks which contain errors, means for detecting if said count exceeds a predetermined value, and error designating means for designating an error-correction word in at least the next received transmission block as being erroneous, whereby at least two words in a de-interleaved block that contains words which are derived from said first and second data sources are identified as being erroneous.

18. Apparatus according to claim 17 wherein said de-interleaving means comprises plural delay means, each having a respectively different time delay and each delaying a respective word contained in said received transmission block, the minimum difference between two respective time delays being equal to D, wherein D is the time period occupied by a predetermined number of successive transmission blocks; and wherein said predetermined value is at least equal to said predetermined number.

19. Apparatus according to claim 18 wherein D is the time period occupied by two successive transmission blocks.

20. Apparatus according to claim 10 wherein said error correcting means does not operate if three or more words in a de-interleaved block supplied thereto are identified as being erroneous, and wherein said inhibit means comprises counting means for counting the number of successive transmission blocks which contain errors, means for detecting if said count exceeds a predetermined value and error designating means for designating an error-correction word in a predetermined number of the next received transmission blocks as being erroneous. whereby at least three words in each de-interleaved block that contains words which are derived from said first and second data source are identified as being erroneous.

21. A PCM signal processing apparatus for receiving successive transmission blocks, each comprising time-interleaved PCM, errorcorrection and error detection words, from either of first or second selectable data sources, wherein an error interval is established during the transition period that the selection of data sources is changed over from one to the other, said apparatus comprising:: detecting means responsive to said error detection words for detecting if a received transmission block contains an error; error identifying means for identifying as being erroneous each of the time-interleaved words included in the received transmission block which has been detected as containing an error; de-interleaving means for time de-interleaving each received transmission block to recover a deinterleaved block comprising de-interleaved PCM and error-correct words, erroneous ones of said de-interleaved words being respectively identified; error correcting means coupled to said deinterleaving means and operative to correct an erroneous PCM word in said de-interleaved block as a function of the remaining PCM and errorcorrection words in that de-interleaved block, provided that the total number of erroneous words in that block is less than a predetermined number;; syndrome generating means for generating a syndrome from said PCM and error-correction words in said de-interleaved block; means for producing a syndrome signal if said syndrome differs from a predetermined value; means coupled to said de-interleaving means for producing a no-error signal if none of the words in said de-interleaved block are erroneous; means for supplying an inhibit signal of predetermined duration to said error correcting means in response to the concurrence of said syndrome and no-error signals, whereby the operation of said error correcting means is inhibited for the duration of said inhibit signal; counting means for counting the number of successive transmission blocks which contain errors; means for detecting if said count exceeds a predetermined value representing a predetermined duration of said error interval; and error designating means for designating an error-correction word in a predetermined number of the next received transmission blocks as being erroneous, whereby the number of words identified as erroneous in each de-interleaved block that contains words which are derived from said first and second data source is at least equal to said predetermined amount.

22. A method according to claim 1 and substantially as any one of the examples hereinbefore described with reference to the accompanying drawings.

23. Apparatus according to claim 10 and substantially as any one of the examples hereinbefore described with reference to the accompanying drawings.