GB2070363A

GB2070363A - Apparatus for converting the period of a periodic signal to a digital count signal

Info

Publication number: GB2070363A
Application number: GB8104894A
Authority: GB
Original assignee: Sperry Corp
Current assignee: Sperry Corp
Priority date: 1980-02-25
Filing date: 1981-02-17
Publication date: 1981-09-03
Also published as: FR2476848A1; IT1170752B; JPS56153499A; IT8147881A0; DE3106904A1; IT8147881A1

Abstract

The output of a vibrating diaphragm pressure sensor 20, which output is a periodic signal with a periodicity a function of measured pressure, is applied to the input of a sensor period counter 22 through a period clock gate 23. The period clock gate 23 is enabled by the first occurring leading edge of the vibrating diaphragm sensor output signal after the occurrence of a start conversion command. The enable signal for the period clock gate 23 also enables a high speed clock gate 28 through which a high frequency clock signal is gated into a high speed counter 27. When the most significant bit of the high speed counter 27 switches to the ONE state, both gates 23,28 are disabled upon the occurrence of the next following leading edge of the sensor output signal. The sensor period is derived from the output of the sensor period counter 22 and the output of the high speed counter 27 by a processor 29 that divides the number of sensor periods that have occurred into the time that the gates were enabled. The processor 29 also controls the conversion time by preloading the high speed counter 27 with a conversion time control number. <IMAGE>

Description

SPECIFICATION Apparatus for converting the period of a periodic signal to a digital count signal This invention relates to apparatus for converting the period of a periodic signal to a digital count signal, particularly (but not exclusively) for use with vibrating diaphragm pressure sensors.

Vibrating diaphragm pressure sensors are in use in the art for measuring atmospheric pressure. Such devices provide an output signal having a frequency that varies as a function of pressure. The sensor output signal therefore is a periodic signal where the duration of the sensor signal period varies in accordance with the measured pressure. Such a vibrating diaphragm pressure sensor device is described in British Patent Specification No. 1,228,401.

British Patent Specification No. 1,562,278 also discloses details of such a sensor. Both patent specifications are in the name of the present applicants.

Referring to Figures 1A and 1 B of the accompanying drawings, graphs of sensor period and sensor frequency versus pressure, respectively, for a typical pressure sensor are illustrated. It will be observed that for relatively high pressures the sensitivity of the device is low and for relatively low pressures the sensitivity of the device is high, the sensitivity of the device being indicated by the slope of the curve. For example, with respect to Figure 1A, at high pressure the slope of the curve, as denominated by the partial derivative of sensor period with respect to pressure, is small whereas at low pressures the slope of the curve is large. Thus, it will be appreciated that at high pressures where the sensitivity of the device (slope of the curve) is low, a relativey large change in pressure results in only a relatively small change in sensor period.At the low pressures where the sensitivity of the device is high, a relatively small change in pressure results in a relatively large change in sensor period.

A prior art technique for measuring the sensor period by converting the period time interval into a digital count is to utilise the sensor period to gate a high frequency clock pulse signal into a counter. The number of pulses accumulated in the counter during a sensor period provides a digital count proportionai to the time interval of the period. In order to increase the accuracy and resolution of the time interval measurement, time interval averaging is utilised in the prior art wherein the digital count is averaged over a number of sensor periods.

Referring to Figure 2 of the accompanying drawings, a prior art period-to-count converter utilising time interval averaging is illustrated. The output of a vibrating diaphragm pressure sensor 10 (having a vibration frequency fp, a period Tp) is applied to a fixed period counter 11. The pressure applied to the sensor is denoted by Ps. The fixed period counter 11 counts a preset number N of sensor periods and provides an enabling signal to a gate 12 for the duration of the N periods. During the occurrence of the N sensor periods, the gate 12 transmits a high frequency clock signal from a high frequency clock pulse generator 13 (having a frequencyfc and a period Tc) to a high speed counter 14. Since the gate 12 is enabled for a fixed integral number of sensor periods, the digital count output of the counter 14 provides a measure of the sensor period.For reasons well understood in the art of time interval averaging, the larger the number of periods N over which the measurement is averaged, the greater will be the accuracy and resolution of the measurement.

In other words, the larger the number of periods N, the smaller will be the weight (of significance) of each clock pulse from the clock pulse generator 13 with respect to its bit significance in the digital count output from the counter 14. The following example may clarify these concepts.

It it is desired to measure a sensor period equal in duration to 4.55 high frequency clock pulse intervals and the counter 11 is set to enable the gate 12 only during one sensor period, either 4 or 5 counts will be accumulated in the counter 14 depending on the relative phase between the sensor output and the high frequency clock. If, however, the counter 11 is set to enable the gate 12 for ten sensor periods, either 45 or 46 clock pulses will be accumulated in the counter 14. When dividing by the number of periods N, a result of 4.5 or 4.6 is obtained, indicating a significant increase in accuracy and resolution. If the conversion were controlled to occur over one hundred sensor periods, then, ignoring time base anomalies, precisely 455 high frequency clock pulses will be accumulated in the counter 14, providing further enhanced accuracy and resolution.

Although providing the advantages of time interval averaging, the period-to-count converter of Figure 2 suffers from numerous disadvantages. In systems wherein a fixed amount of conversion time is available, the number of periods N of the counter 11 is set whereby N periods of the longest sensor period occur just within the available conversion time. As is appreciated from Figure 1A, the longest sensor period occurs at the low pressure end of the sensor pressure range. With the number of sensor periods N fixed in this manner, it will be appreciated that the time interval averaging to improve accuracy and pressure resolution will occur over this fixed number of sensor periods throughout the pressure range of the device.At the low pressure end of the range, this number of sensor periods over which the averaging occurs is typically more than adequate because of the high sensitivity of the device in this range. At the high frequency end of the pressure range, however, averaging over this number of cycles typically results in inadequate accuracy and pressure resolution because of the low sensitivity of the device in this range. It is generally only over the middle of the pressure range of the device that the number of periods over which the averaging occurs is just sufficient to provide desired accuracy and resolution.

In addition to the degradation in accuracy and pressure resolution experienced by the system as the pressure to be measured increases, significant amounts of conversion time are wasted. Since, as described above, the fixed number of sensor periods N of the longest sensor period just fit into the available conversion time, it will be appreciated that the same number of shorter sensor periods occur in significantly less than the available conversion time.

At the high pressure end of the pressure range, most of the conversion interval is dead time that is wasted during the operation of the system. Such systems may be of the type controlled by a microprocessor wherein the system operating program is reiterated a fixed number of times a second resulting in the requirement of a fixed time in which the conversion is performed.

If in systems where operating parameters permit, the number of sensor periods N over which the time interval averaging occurs is set so as to provide good resolution and accuracy at the high pressure end of the range, the required conversion time at the low frequency end of the range would become prohibitively large. In any type of system utilising the prior art converter of Figure 2, irrespective of the value at which the number of sensor periods N is fixed, the conversion time over the range of the vibrating diaphragm pressure sensor will vary by an undesirably large amount and the sensor period resolution bit weight per hig frequency clock pulse will also vary in an undesirable manner resulting in problems in system design.

In the prior period-to-count converter of Figure 2, once the number of periods N is determined from system consideratons, this number is permanently fixed into the hardware. The results in an additional problem when utilising the prior converter in that changes in conversion requirements (such as a desired change in resolution or conversion time or in sensor characteristics resulting from, for example, a sensor replacement) necessitate an undesirable hardware redesign and reconfiguration of the converter.

It is an aim of the present invention in its preferred form to reduce the required conversion time and also to provide an increase in the pressure resolution over the range of pressures to be measured. It is a further aim to effect changes in resolution and conversion time without requiring hardware redesign.

According to the invention there is provided apparatus for converting the period of a periodic signal to a digital count signal, comprising control means for initiating a conversion interval at a predetermined time phase of the periodic signal and terminating the conversion interval upon the next occurrence of the predetermined time phase of the periodic signal following a predetermined time interval after the initiation of the conversion interval, first counter means enabled by the control means to count the periods of the periodic signal occurring during the conversion interval, thereby counting an integral number of the periods, clock pulse generator means for providing a clock pulse signal, and second counter means enabled by the control means to count the pulses of the clock pulse signal occurring during the conversion interval, the count outputs of the first and second counter means providing the digital count signal.

The above disadvantages of the prior art are overcome by the herein described apparatus according to the invention for converting the period of a periodic signal to a digital count signal. The described apparatus according to the invention comprises a control circuit for initiating a conversion interval at a predetermined time phase of the periodic signal and terminating the conversion interval upon the next occurrence of the predetermined time phase of the periodic signal that follows a predetermined time interval after the initiation of the conversion interval. The apparatus further comprises a sensor period counter enabled by the control circuit to count the periods of the periodic signal occurring during the conversion interval, thereby counting an integral number of the periods.A high speed counter is enabled by the control circuit to count the pulses of a high frequency clock pulse signal that occur during the conversion interval.

Means responsive to the count outputs of the sensor period counter and the high speed counter provide the digital count signal representative of the period of the periodic signal.

Preferably, the predetermined time interval controlling the termination of the conversion interval is rendered variable by preloading the high speed counterwith a predetermined number and byterminating the conversion interval upon the next occurrence of the predetermined time phase of the periodic signal following the occurrence of a predetermined count of the high speed counter. In a computer controlled system, the preload number that controls the duration of the conversion interval may be provided by the system software placing the determination of conversion time and resolution under computer control.

Of the accompanying drawings, Figures lA, 1B and 2 have been mentioned previously. A preferred embodiment of the invention is shown in the remaining figures, in which Figure 3 is a schematic block diagram of a period-to-count converter forming the preferred embodiment of the present invention, Figure 4 is a waveform timing diagram of signals appearing at various points of Figure 3, Figure 5A is a chart illustraing sequential states of the sensor period counter and the high speed counter during the operation of the apparatus with a particular preload number, Figure 5B is a delineation of computations performed on the count outputs of Figure 5A of the sensor period counter and the high speed counter to provide sensor period and frequency, Figure 6A is a chart illustrating sequential states of the sensor period counter and the high speed counter during the operation of the apparatus with another particular preload number, and Figure 6B is a delineation of the computations performed on the count outputs of Figure 6a of the sensor period counter and the high speed counter to provide the sensor period and frequency.

Figure 3 illustrates a schematic block diagram of the preferred converter and Figure 4 depicts waveforms at various points of the converter of Figure 3.

A vibrating diaphragm pressure sensor 20, of the type discussed above, provides its periodic output signal on a lead 21 to a sensor period couner 22 via a period clock gate 23. The periodic signal from the sensor 20 is denominated by the reference character A and is depicted in Figure 4 as the sensorfrequency. The sensor frequency signal transmitted through the gate 23 to the counter 22 is denominated by the reference character E and is depicted in Figure 4 as the period clock. The periodic signal on the lead 21 is also applied to control circuitry 24 for reasons to be discussed.

A high frequency clock pulse generator 25 provides a high frequency clock pulse signal on a lead 26 to a high speed counter 27 via a high speed clock gate 28. The high frequency clock pulse signal on the lead 26 is denominated by the reference character C and is illustrated in Figure 4 as the oscillator output.

The high frequency clock pulse signal transmitted through the gate 28 to the counter 27 is denominated by the reference character F and is depicted in Figure 4 as the high speed clock.

The digital count outputs from the counters 22 and 27 comprise a digital count signal which may be applied to a microprocessor 29 wherein computations may be performed for deriving a digital count signal at 30 from the count outputs of the counters 22 and 27 repesentative of the period of the periodic signal from the sensor 20 as well as a signal at 31 representative of the frequency of the output signal of the sensor 20. The most significant bit (msb) of the count output from the counter 27 is applied via a lead 32 to the control circuitry 24 for reasons to be explained. The msb signal from the counter 27 is denominated by the reference character G and is depicted in Figure 4 as te high speed counter msb.

At the beginning of a conversion interval, the processor 29 preloads the counter 27 with a predetermined counter preload number via leads 33 for reasons to be discussed. The processor 29 also issues a start conversion command signal via a lead 34 to the control circuitry 24. The start conversion command signal is denominated by the reference character B and is illustrated in Figure 4 as the start conversion signal.

In response to the start conversion command on the line 34, the msb signal on the line 32 and the sensor output signal on the line 21, the control circuitry 24 provides an enable signal on a lead 35 to enable the gates 23 and 28 in a manner to be described. The enable signal on the lead 35 is denominated by the reference character D and is illustrated in Figure 4 as the enable signal.

With continued reference to Figures 3 and 4, the operation of the preferred embodiment of the period-to-count converter of the present invention will now be described. Upon issuance of the start conversion command by the processor 29 to the control circuitry 24, the control circuitry 24 resets the sensor period counter 22 to zero and resets the most significant bit and a number of the low order bits of the high speed counter 27 to zero by connections not shown; and, via leads 33, loads the counter preload number from the processor 29 into the remaining high order bits of the counter 27. The magnitude of the counter preload number controls the duration of the conversion interval and hence the resolution of the converter in a manner to be further clarified.For a given vibrating diaphragm sensor and given system characteristics and requirements, the counter preload number provided by the processor 29 is generally a constant set into the system software.

Since the counter preload number is provided by software, the number may readily be altered to accommodate changing system requirements. The counter preload number may be altered to accommodate a change in sensor characteristics due to sensor replacement or a change in system requirements such as an increase or decrease in pressure resolution or accuracy or a change in desired conversion time. In dual sensor systems, such as air data computers, the sensor signals may be multiplexed to the converter and different preload numbers used for each sensor, as required by system design.

After the issuance of the start conversion command pulse on the line 34, conventional circuits within the control circuitry 24 in response to the next occurring leading edge of the sensor output signal on the line 21 provide the enable signal on the line 35. The enable signal on the line 35 renders conductive the period clock gate 23 and the high speed clock gate 28, thereby transmitting the period clock signal to the sensor period counter 22 and the high speed clock signal to the high speed counter 27. Thus, it will be appreciated that upon the occurrence of the first leading edge of the sensor output signal following the start conversion command, the counters 22 and 27 begin counting the respectively applied signals. Since the sensor period counter 22 was initially reset to zero, the counter 22 begins counting upwardly from the zero count.Since the high speed counter 27 was initially preset to the counter preload number, the counter 27 begins counting upwardly from the preload. As the counting process proceeds, the counter 22 accumulates the count of sensor periods which have occurred since the counting process started and the high speed counter 27 accumulates the sum of the number to which the counter was originally preloaded plus the number of periods from the oscillator 25 which have elapsed since the start of the counting process.

As the counter 27 continues counting high speed clock pulses, eventually the count therein will increase to the point where the most significant bit of the counter will be set. Conventional circuits within the control circuitry 24 responsive to the msb signal from the counter 27 and to the sensor output signal on the lead 21 terminate the enable signal on the lead 35 upon the occurrence of the next following leading edge of the sensor output signal. Thus, upon the occurrence of the leading edge of the sensor output signal following the setting of the msb of the counter 27, the gates 23 and 28 are disabled terminating the counting process in both the sensor period counter 22 and the high speed counter 27.

It will be appreciated from the foregoing that the conversion interval, as demarcated by the enable pulse D illustrated in Figure 4 and during which the counters 22 and 27 are enabled to count, occurs over an integral number of periods of the sensor output signal. At the end of the conversion interval, the sensor period counter 22 contains a digital count of the number of sensor periods that have occurred and the high speed counter 27 contains a digital count of the preload number plus the number of periods of the high speed clock signal that have occurred during the conversion interval. The digital period count output from the sensor period counter 22 and the digital high speed count output from the high speed counter 27 comprise a digital count signal suitable for entry into the processor 29 for computing the period of the sensor output signal as well as the frequency thereof.Accordingly, the processor 29 divides the duration of the conversion interval by the number of sensor periods occurring during the conversion interval to provide the sensor period. The sensor frequency is computed from the reciprocal of the sensor period. The conversion time is derived from the count output of the high speed counter 27, the counter preload number and the frequency of the high speed clock.

Referring now to Figure 5A, a chart of sequential counter states exemplifying the operation of the converter of Figure 3 is illustrated. In this illustrative embodiment the high speed counter 27 comprises a 21-bit counter and the sensor period counter 22 comprises a 7-bit counter. In the illustrated example, bits 13 to 19 of the high speed counter 27 are preloaded by the processor 29 to (0 111 0 1 0), thus the initial state of the high speed counter is the equivalent of (4 7 5 1 3 6) decimal. The most significant bit 20 of the high speed counter 27 as well as the least significant bits 0 to 12 are initially cleared as described above. It is observed that after the most significant bit 20 of the high speed counter 27 switches to the ONE state, the counting procedure continues until the next occurring leading edge of the sensor output signal.Figure 5B delineates the manner in which the digital count outputs from the counters 22 and 27 may be utilised to provide the sensor frequency. It is observed that for a sensor frequency of approximately 1 7 9 3 Hz, the conversion time is between 18 and 19 milliseconds. Figures 6A and 6B provide another example of the operation of the converter of Figure 3 wherein the high speed counter preload number is (00 11 0 11) resulting in an initial high speed counter state of (2 2 1 8 4) decimal. It is observed that for a sensor frequency of again approximately 1 7 93 Hz the conversion time is now between 26 and 27 milliseconds.

The examples of Figures 5A and 6A demonstrate that the conversion time is controlled bythe preload number provided by the processor 29, thus placing the conversion time directly under the control of the processor. It will be appreciated that the computations delineated in Figures 5B and 6B may be readily implemented in the data processor 29 by conventional discrete digital or analog circuitry or by coded software in a stored program digital computer in accordance with conventional program routines prepared from the delineated computations.

Since an increase in conversion time results in time interval averaging over a larger number of sensor periods, an increase in conversion time results in an increase in resolution. Since an increase in conversion time results in a larger number of high speed clock pulses being accumulated, the bit weight of each pulse is accordingly reduced. Thus when the conversion time is increased, each high speed pulse represents a smaller incremental pressure change, thereby increasing the pressure resolution of the converter. Since the conversion time is controlled by the preload number provided to the high speed counter 27 by the processor 29, it will be apprecated that the resolution of the converter is directly under the control of the digital processor 29.

Thus as the preload number is increased, the conversion time decreases and the uncertainty in the pressure measurement or the sensor frequency increases. The converse effect occurs for a decrease in the preload number.

Therefore, it will be appreciated that, unlike the prior art arrangement discussed above with respect to Figure 2, where a change in conversion time or resolution requires an undesirable hardware alteration, changes in these system parameters are effected by a mere software alteration in the counter of Figure 3. Thus by utilising the counter of Figure 3 the conversion time and resolution of the system can be placed under computer control, facilitating adaptability of the converter to different sensors, applications and conditions.

To exemplify the improvements which can result by utilising the present invention, consider a particular pressure sensor over a particular pressure range wherein the sensor frequency varies from 942.86 Hz to 3565.06 Hz. Utilising a converter based on the prior art discussed above with respect to Figure 2, the conversion time for a fixed number 16 of sensor periods varies from 4.49 to 18 milliseconds. Utilising the inventive converter described and setting the minimum conversion time at 7.68 milliseconds, the conversion time now varies from 7.68 to 9.8 milliseconds. Thus, the maximum conversion time of the inventive converter is shorter than that of the prior art arrangement and, additionally, the inventive converter provides better worst-case pressure resolution than the prior art device.Thus it will be appreciated that the inventive converter simultaneously improves pressure resolution and conversion time compared with the converter of the prior art. The conversion time for the inventive converter is relatively constant compared with that of the converter of the prior art. Additionally, the sensor period bit weight of each high speed clock pulse and the concomitant sensor period resolution vary undesirably in the arrangement of the prior art, whereas in the inventive converter the high speed counter bit weight and sensor period resolution are approximately constant.

The present invention has been described in terms of terminating the conversion interval in accordance with the setting of the msb of the high speed counter 27. It will be appreciated that any predetermined count of the high sped counter 27 may be utilised to the same effect. The present invention also encompasses other mechanisms for terminating the conversion interval. For example, a timer such as a monostable multivibrator may be utilised to time a predetermined interval from the leading edge of the enable signal so as to terminate the enable signal at the next occurring sensor frequency leading edge after the predetermined interval.Alternatively, the sensor period counter 22 may be utilised to control the high speed clock gate in accordance with counting for a time that is greater than or equal to a predetermined interval so as to enable the high speed clock gate for an integral number of sensor periods that just exceed the predetermined interval.

The above described embodiment of the invention was explained in terms of utilising the leading edge of the sensor frequency signal for initiating and terminating the conversion interval. It will be appreciated that alternatively any predetermined time phase of the signal may be utilised for this purpose.

For example, the trailing edges may be so utilised.

Alternatively the conversion interval may be started at a leading edge and ended at a trailing edge or vice versa. With this arrangement an integral number of sensor periods plus one-half of a sensor period are utilised in the computations.

Figures 5B and 6B delineate particular computations for providing sensor period and sensor frequency. These computations involve deriving the conversion time by subtracting the counter preload number from the count output of the high speed counter 27 and dividing by the frequency of the high speed clock. It will be appreciated that such computations are exemplary, other computations being usable to provide the same result.

The present invention may be considered as providing an adaptive converter in that it automatically adapts the number of sensor periods over which the time interval averaging is effected in accordance with the computer controlled conversion interval.

The number of sensor periods is a variable depending on the conversion interval. The invention may be used to select the maximum possible number of sensor periods over which to provide the averaging.

The Figure 3 embodiment of the present invention utilises a high speed clock pulse train that is asynchronous with respect to the start conversion pulse and with respect to the beginning of the conversion interval. It will be appreciated that synchronised clock pulse gating may also be utilised in the inventive converter to provide an even further improvement in the accuracy enhancement provided by time interval averaging. In such a system, the clock pulses would trigger logic to provide the synchronising function. Although the present invention has been described in terms of utilisation with a vibrating element pressure sensor, it will be appreciated that the inventive converter may also be utilised to advantage with other sensors or devices that provide periodic signals.

The inventive converter provides an ancillary advantage in reducing the effective noise of the system. Since in the inventive converter averaging is generally effected over longer time intervals than in the prior art, the system noise is more efficaciously averaged out.

Claims

1. Apparatus for converting the period of a periodic signal to a digital count signal, comprising control means for initiating a conversion interval at a predetermined time phase of the periodic signal and terminating the conversion interval upon the next occurrence of the predetermined time phase of the periodic signal following a predetermined time interval after the initiation of the conversion interval, first counter means enabled by the control means to countthe periods of the periodic signal occurring during the conversion interval, thereby counting an integral number of the periods, clock pulse generator means for providing a clock pulse signal, and second counter means enabled by the control means to count the pulses of the clock pulse signal occurring during the conversion interval, the count outputs of the first and second counter means providing the digital count signal.

2. Apparatus according to claim 1, wherein the control means includes means for loading the second counter means with a first predetermined count, to determine the predetermined time interval.

3. Apparatus according to claim 1, wherein the control means includes means responsive to the periodic signal and to a second predetermined count of the second counter means for terminating the conversion interval upon the next occurrence of the predetermined time phase of the periodic signal following the occurrence of the second predetermined count of the second counter means.

4. Apparatus according to claim 3, wherein the second predetermined count is represented by the setting of a predetermined bit of the second counter means, and the means for terminating the conversion interval comprises means responsive to the periodic signal and to the predetermined bit of the second counter means for terminating the conversion interval upon the next occurrence of the predetermined time phase of the periodic signal following the setting of the predetermined bit of the second counter means.

5. Apparatus according to claim 4, wherein the predetermined bit comprises the most significant bit of the second counter means, and the means for terminating the conversion interval comprises means responsive to the periodic signal and to said most significant bit of the second counter means for terminating the conversion interval upon the next occurrence of the predetermined time phase of the periodic signal following the setting of the predetermined bit of the second counter means.

6. Apparatus according to claim 1, wherein the predetermined time phase occurs at the leading edges of the period signal, and the control means comprises means for initiating the conversion interval at the occurrence of a leading edge of the periodic signal and terminating the conversion interval upon the next occurrence of a leading edge of the periodic signal following a predetermined time interval after the initiation of the conversion interval.

7. Apparatus according to claim 3, wherein the predetermined time phase occurs at the leading edges of the periodic signal, and the means for terminating the conversion interval comprises means responsive to the periodic signal and to the second predetermined count of the second counter means for terminating the conversion interval upon the next occurrence of a leading edge of the periodic signal following the occurrence of the second predetermined count of the second counter means.

8. Apparatus according to claim 5, wherein the predetermined time phase occurs at the leading edges of the periodic signal, and the means for terminating the conversion interval comprises means responsive to the periodic signal and to the most significant bit of the second counter means for terminating the conversion interval upon the next occurrence of a leading edge of the periodic signal following the setting of the most significant bit of the second counter means.

9. Apparatus according to any of the preceding claims, wherein the first counter means comprises a first counter, and gating means responsive to the periodic signal and coupled to the control means for transmitting the periodic signal to the first counter during the conversion interval.

10. Apparatus according to any of the preceding claims, wherein the second counter means comprises a second counter, and gating means responsive to the clock pulse signal and coupled to the control means for transmitting the clock pulse signal to the second counter during the conversion interval.

11. Apparatus according to any of the preceding claims, and further including data processing means responsive to the count outputs of the first and second counter means for computing the period of the periodic signal therefrom.

12. Apparatus according to claim 2, and further including data processing means for providing the first predetemined count to the second counter means and for computing the period of the periodic signal by subtracting the first predetermined count from the count output of the second counter means and dividing the difference thereof by the frequency of the clock pulse signal and by the count output of the first counter means.

13. Apparatus according to claim 1, wherein the control means comprises means responsive to a start conversion command signal for initiating the conversion interval at the next occurrence of the predetermined time phase of the periodic signal following the start conversion command signal and terminating the conversion interval upon the next occurrence of the predetermined time phase of the periodic signal following the predetermined time interval after the initiation of the conversion interval.

14. Apparatus according to any of the preceding claims, and for use with a vibrating diaphragm pressure sensor in which the periodic signal is provided by the sensor.

15. Apparatus for converting the period of a periodic signal to a digital count signal comprising control means for initiating a conversion interval at a first predetermined time phase of the periodic signal and terminating the conversion interval upon the next occurrence of a second predetermined time phase of the periodic signal next following a predetermined time interval after said initiation of the conversion interval, first counter means enabled by the control means to count the periods of the periodic signal occurring during the conversion interval, thereby counting an integral number of the periods, clock pulse generator means for providing a clock pulse signal, and second counter means enabled by the control means to count the pulses of the clock pulse signal occurring during the conversion interval, the count outputs of the first and second counter means providing the digital count signal.

16. Apparatus for converting the period of a periodic signal to a digital count signal, the apparatus being constructed and arranged substantially as herein particularly described with reference to Figures 3 to 6B of the accompanying drawings.