GB2068286A - Reactive sputter etching of silicon - Google Patents

Reactive sputter etching of silicon Download PDF

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Publication number
GB2068286A
GB2068286A GB8103292A GB8103292A GB2068286A GB 2068286 A GB2068286 A GB 2068286A GB 8103292 A GB8103292 A GB 8103292A GB 8103292 A GB8103292 A GB 8103292A GB 2068286 A GB2068286 A GB 2068286A
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etching
chlorine
gas
silicon
etched
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GB2068286B (en
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AT&T Corp
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Western Electric Co Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • CCHEMISTRY; METALLURGY
    • C04CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04BLIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B41/00After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
    • C04B41/53After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone involving the removal of at least part of the materials of the treated article, e.g. etching, drying of hardened concrete
    • C04B41/5338Etching
    • C04B41/5346Dry etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Plasma & Fusion (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Structural Engineering (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

Highly selective etching of silicon, relative to silicon dioxide and other common masking materials, can be achieved by reactive sputter etching using a plasma derived from chlorine. The etching is highly uniform and free from loading effects. For monocrystalline silicon and undoped polycrystalline silicon the etching is anisotropic. For doped polycrystalline silicon the etching can be controlled to by anywhere between isotropic and completely vertical. <IMAGE>

Description

SPECIFICATION Reactive sputter etching of silicon This invention relates to dry etching processes and in particular in reactive sputter etching of silicon.
Considerably interest exists in employing dry processing techniques for patterning workpieces such as semiconductor wafers. The interest in such techniques stems from their generally better resolution and improved dimensional and shape control capabilities relative to standard wet etching. Thus, dry etching is being utilized increasingly for pattern delineation in the processing of, for example, semiconductor wafers to form large-scale-integrated (LSI) devices.
Various dry etching processes that involve the use of gaseous plasmas are known, as described, for example, in "Plasma-Assisted Etching for Pattern Transfer" by C.J. Mogab and W.R. Harshbarger, J. Vac. Sci. 8 Tech., 16 (2), March/April 1979, p. 408. As indicated therein, particular emphasis in recent work has been directed at developing processes that utilize reactive gas plasmas in a mode wherein chemical reactions are enhanced by charged particle bombardment.
One advantageous such process, designated reactive sputter (or ion) etching, is described in the aforecited Mogab-Harshbarger article and in Proc. 6th Int'l Vacuum Congr. 1974, Japan. J. Appl. Phys., suppl. 2, pt. 1, pp.
435-438, 1974.
Considerable effort has been directed recently at trying to devise reliable reactive sputter etching processes for fine-line pattern delineation in silicon surfaces. Of particular practical interest has been the work directed at etching polysilicon. Polysilicon films, both doped and undoped, constitute constituent layers of commercially significant LSI devices such as 64K dynamic random-access-memories (RAMs) of the metal-oxide-semiconductor (MOS) type. Accordingly, it was recognized that improved methods of patterning silicon by reactive sputter etching, if available, could contribute significantly to decreasing the cost and improving the performance of such devices and other structures that include silicon substrates or layers.
According to the present invention there is provided a method of etching a silicon surface region of a body in an apparatus which comprises an anode electrode and a cathode electrode which holds the body, wherein a plasma is formed by the imposition of an electric field across a gas introduced between the electrodes, which gas comprises chlorine as the active reactant species. For monocrystalline silicon and undoped polycrystalline silicon the etching is anisotropic. For doped polycrystalline silicon the etching can be controlled to be isotropic, completely anisotropic (i.e. substantially no lateral etching) or anywhere in between.
Anisotropic reactive sputter etching can be carried out by selecting chlorine partial pressures, chlorine gas flows and power densities in the ranges 2-to-50 microns, 2-to-150 cubic centimetres per minute and 0.03-to-2 watts per square centimetre respectively.
Isotropic reactive sputter etching of doped polysilicon can be carried out by selecting chlorine partial pressures, chlorine gas flows and power densities in the ranges 2-to-50 microns, 2-to-150 cubic centimetres per minute and 0.06-to-2 watts per square centimetre, respectively. In selecting particular values from these ranges to achieve isotropic, rather than anisotropic, etching of doped polysilicon, it is characteristic of each set of selected values that for a given power density there is a corresponding minimum or threshold pressure above which isotropic etching occurs. As the power density is increased, the corresponding threshold pressure for isotropic etching increases linearly. Or, for a given pressure, there is a maximum power density below which isotropic etching occurs.
Some embodiments of the invention will now be described by way of example with reference to the accompanying drawing in i which: Figure 1 is a schematic depiction of a parallel-plate reactor in which the processes of the present invention can be carried out; Figure 2 is a sectional representation of a masked monocrystalline silicon member that is capable of being etched in accordance with this invention; and Figure 3 is a sectional representation of a masked polycrystalline silicon layer to be etched in accordance with the present invention.
The parallel-plate reactor shown in Fig. 1 comprises an etching chamber 10 defined by a cylindrical nonconductive member 12 and two conductive end plates 14 and 16. The member 12 is made of glass and the plates 14 and 16 are each made of aluminium. In addition, the depicted reactor includes a conductive workpiece holder 18, also made of aluminium. In one illustrative case, the bottom of the holder 18 constitutes a 25 cm (10-inch) circular surface designed to have seven 7.5 cm (3-inch) wafers placed thereon.
Wafers 20, whose bottom (i.e., front) surfaces are to be etched, are shown in Fig. 1 mounted on the bottom surface of a plate 22.
The plate 22 is designed to be secured to the holder 18 by any suitable standard instrumentality (not shown) such as clamps or screws and is made of a conductive material such as aluminium. The top or back surfaces of the wafers 20 are maintained in electrical contact with the plate 22.
The wafers 20 of Fig. 1 are maintained in place on the plate 22 by a cover plate 24 having apertures therethrough. The apertures are positioned in aligned registry with the wafers 20 and are each slightly smaller in diameter than the respectively aligned wafer.
In that way, a major portion of the front surface of each wafer is exposed for etching.
By any standard means, the cover plate 24 is secured to the plate 22.
The cover plate 24 included in the etching apparatus of Fig. 1 is made of a low-sputteryield material that does not react chemically with the etching gas to form a nonvolatile material. Suitable such materials include anodized aluminium and fused silica.
The workpiece holder 18 shown in Fig. 1 is capacitively coupled via a radio-frequency tuning network 26 to a radio-frequency generator 28 which is designed to drive the holder 18 at a frequency of 13.56 megahertz. Further, the holder 18 is connected through a filter network, comprising an inductor 30 and a capacitor 32, to a meter 34 that indicates the peak value of the radio4requency voltage applied to the holder 18.
In Fig. 1, the end plate 14 is connected to a point of reference potential such as ground.
The plate 14 is the anode of the depicted reactor. The workpiece holder 18 constituted the driven cathode of the reactor. In one reactor of the type shown in Fig. 1, the anode-to-cathode separation was approximately 25 cm (10 inches) and the diameter of the anode plate was approximately 43 cm (17 inches).
The end plate 16 of the Fig. 1 arrangement is also connected to ground. Additionally, an open-ended cylindrical shield 36 surrounding the holder 18 is connected to the plate 16 and thus to ground. The portion of the holder 18 that extends through the plate 16 is electrically insulated therefrom by a nonconductive bushing 38.
A chlorine gas atmosphere is established in the chamber 10 of Fig. 1. Chlorine gas is controlled to flow into the indicated chamber from a standard supply 40. Additionally, a prescribed low pressure condition is maintained in the chamber by means of a conventional pump system 42.
By introducing chlorine gas into the chamber 10 (Fig. 1) and establishing an electrical field between the anode 14 and the cathode 18, as specified in particular detail below, a reactive plasma is generated in the chamber 10. The plasma established therein has a uniform dark space in the immediate vicinity of the workpiece surfaces to be etched. Volatile products formed at the workpiece surfaces during the etching process are exhausted from the chamber by the system 42.
Fig. 2 is a cross-sectional depiction of a portion of one of the wafers 20 to be etched in the chamber 10 of Fig. 1. In Fig. 2, a conventionally patterned masking layer 46 is shown formed on a substrate 48 made of monocrystalline silicon which, for example, is either p- or n-doped to exhibit a resistivity of approximately 1-to- 10 ohm-centimetres. The unmasked portions of the silicon substrate 48 are removed in a reactive sputter etching process to form vertically walled features therein exhibiting virtually no undercutting relative to the overlying masking layer 46. As indicated in Fig. 2 by dashed lines 47, such anisotropic etching of the substrate 48 forms therein a precisely defined channel.
The ability to anisotropically etch features in monocrystalline silicon is of practical importance in connection with the fabrication of microminiature electronic devices. Thus, the aforespecified channel formed in the substrate 48 of Fig. 2 represents, for example, one step in the process of fabricating a microminiature MOS capacitor. Other device structures that require the anisotropic etching of a substrate or layer of monocrystalline silicon during the fabrication thereof are known in the art.
Anisotropic etching of both doped and undoped polysilicon layers is of significant importance in the fabrication of LSI devices.
Thus, for example, in making MOS RAMs it is typically necessary at different steps in the fabrication sequence to precisely pattern thin layers of doped and undoped polysilicon.
Fig. 3 represents in cross-section a portion of an MOS RAM device structure that includes a polysilicon layer to be etched. In Fig.
3, a thin (for example, 500-Angstrom-unit) layer 50 of silicon dioxide is shown on a monocrystalline silicon member 52. On top of the layer 50 is a layer 54 of polycrystalline silicon. Illustratively, the layer 54 is about 5000 Angstrom units thick. On top of the layer 54 to be etched is a conventionally patterned masking layer 56.
Fig. 3 is to be considered a generic depiction of different portions of the same memory device. In some portions of the device being fabricated, the layer 54 is made of doped polysilicon and is commonly referred to as the poly 1 level, as is well known in the art. In other portions of the same device, the layer 54 is made of undoped polysilicon. This undoped layer is commonly referred to as the poly 2 level.
Anisotropic etching of layers of either doped or undoped polysilicon can be achieved. Anisotropic etching of the layer 54 of Fig. 3 is represented therein by vertical dashed lines 58. But it is also feasible to achieve isotropic etching of doped polysilicon layers. A com- i pletely isotropic profile is represented by - curved dashed lines 60 in Fig. 3. Moreover, it is possible to selectively control the etching of a a doped polysilicon layer to achieve an edge profile therein intermediate the completely anisotropic and completely isotropic cases illustrated in Fig. 3.
In the examples the doped polysilicon is a polysilicon layer to which a p dopant such as phosphorus has been added. Illustratively, the dopant concentration in such a layer is controlled to establish a resistivity therein in the range 20-to-100 ohm-centimetres.
Various materials are suitable for forming the patterned masking layers 46 and 56 shown in Figs. 2 and 3. These materials include organic or inorganic resists, silicon dioxide, magnesium oxide, aluminium oxide, titanium, tantalum, tungsten oxide, cobalt oxide, and the refractory silicides of titanium, tantalum and tungsten. Masking layers made of these materials are patterned by standard lithographic and etching techniques.
Reactive sputter etching of monocrystalline silicon and doped or undoped polycrystalline silicon is carried out in a chlorine gas atmosphere. In a preferred embodiment, the atmosphere established in the etching chamber comprises essentially pure chlorine. Typically, as a practical matter, this means that chlorine gas having a purity of, for example, approximately 95-to-99.5 volume percent is the sole constituent purposely introduced into the chamber. Under the particular process conditions specified herein, such a pure chlorine gas atmosphere has a relatively high etching rate for silicon. Moreover, the selectivity therein between the silicon to be etched and other layers (such as the masking layer and other layers in the device structure made, for example, of silicon dioxide) is relatively high.
In addition, the use of only chlorine gas as the medium introduced into the chamber is generally preferred because of the relative simplicity of handling and controlling a onegas supply.
Constituents other than chlorine may, however, also be added to the reaction chamber to achieve controlled etching of silicon, provided that the process conditions specified herein are maintained. In general, however, adding another constituent to chlorine decreases the differential etch rate between silicon and other materials such as silicon dioxide in the structure being processed.
Illustratively, the constituents that may be added to chlorine to carry out reactive sputter etching of silicon include argon or any other noble gas up to approximately 20-to-25 volume percent, or nitrogen up to approximately 20-to-25 volume percent, or helium up to approximately 50 volume percent.
For anisotropic etching in the equipment described a chlorine partial pressure of about 5 microns is established in the etching chamber, with a chlorine gas flow into the etching chamber of approximately 10 cubic centimetres per minute.
A power density of approximately 0.25 watts per square centimetre is established at the surfaces of the workpieces to be etched.
For the particular conditions established in the examples, monocrystalline silicon and undoped polycrystalline silicon were each anisotropically etched at a rate of approximately 600 Angstrom units per minute. The corresponding anisotropic etch rate for doped polysilicon was about 1200 Angstrom units per minute.
To achieve anisotropic etching of a doped polysilicon layer as described herein, it is essential that the backside of the workpiece to be etched be maintained in good electrical contact with the driven cathode electrode during the etching process. Otherwise, isotropic etching of the doped polysilicon layer will result. For undoped polysilicon and monocrystalline silicon, however, anisotropic etching is achieved whether or not the backside of the workpiece electrically contacts the driven cathode electrode.
Anisotropic etching processes of the type specified above have a relatively high differential etch rate with respect to, for example, both silicon dioxide and standard resist materials such as HPR-204 (commercially available from Philip A. Hunt Chemical Corp. Paiisades Park, New Jersey). The illustrative processes for monocrystalline silicon and undoped polysilicon etch silicon approximately 30 times faster than silicon dioxide and about three times faster than resist. The illustrative process for doped polysilicon etches the polysilicon layer about 50 times faster than silicon dioxide and about six times faster than resist.
As mentioned above, isotropic etching of doped polysilicon results if the backside of the workpiece to be etched is not maintained in electrical contact with the driven cathode electrode of the etching apparatus. Alternatively, isotropic etching of doped polysilicon can be achieved while the backside of the workpiece is maintained in electrical contact with the driven cathode electrode. This is accomplished by establishing particular conditions in the etching chamber, as specified below. And, significantly, by changing these conditions, the etching process can be controlled to vary between completely isotropic and completely anisotropic.
In example, completely isotropic reactive sputter etching of doped polysilicon in a chlorine gas atmosphere is achieved in a parallelplate reactor by establishing therein a chlorine partial pressure of approximately 20 microns, a gas flow of approximately 10 cubic centimetres per minute and a power density of 0.125 watts per square centimetre. By varying these parameters between the values specified in this paragraph and those specified earlier above for anisotropic etching of doped polysilicon, the edge profile of the etched layer can be controlled to occur anywhere in the range between completely isotropic and completely anisotropic.Thus, for example, if these parameters are established at approximately 15 microns, 10 cubic centimetres per minute and 0.20 watts per square centimetre, an etching condition for doped polysilicon almost exactly half way between completely isotropic and completely anisotropic is achieved. In this condition, the amount of undercutting (maximum lateral etch) is approx- imately half the vertical thickness of the etched layer.
It is hypothesized by applicants that in the herein-specified etching process ions incident on the workpiece to be etched activate chlorine species on the surface of the workpiece.
In turn, chlorine so activated reacts with the material (silicon) to be etched to form volatile products that are removed from the etching chamber by the pumping system connected thereto. In practice, the flow of chlorine into the chamber is advantageously maintained above a threshold value. In that way, an adequate supply of the active species (chlorine) is provided, whereby a specified etching rate is achieved and maintained during the etching process.
The reactive sputter etching processes described herein employ low power densities.
For this reason the processes do not cause any appreciable thermally induced distortions such as workpiece warpage or dimensional changes in the equipment itself. Additionally, the availability and design of radio-frequency generators for energizing the etching equipment is facilitated by the relatively low power requirements.
Further, the processes described herein exhibit a relatively high uniformity of etch rate across each workpiece as well as from workpiece to workpiece. In practice, such variations in etch rate have been determined not to exceed about i 2 per cent.
Additionally, the processes of the present invention do not exhibit any appreciable loading effects. (As is well known, loading is the dependence of etch time on the total surface area to be etched). Moreover, the edge profile, the etch rate and the selectivity of each of those processes have been determined to be virtually independent of the specific pattern geometry, feature size and masking material involved in the etching operation.

Claims (12)

1. A method of etching a silicon surface region of a body in an apparatus which comprises an anode electrode and a cathode electrode which holds the body, wherein a plasma is formed by the imposition of an electric field across a gas introduced between the electrodes, which gas comprises chlorine as the active reactant species.
2. A method as claimed in claim 1 wherein a chlorine partial pressure in the range 2-to-50 microns is established in the apparatus and the power density at the surface being etched is in the range 0.03-to-2 watts per square centimetre.
3. A method as claimed in claim 1 or claim 2 wherein chlorine gas is introduced into said apparatus at a rate in the range 2-to-150 cubic centimetres per minute.
4. A method as claimed in any of the preceding claims wherein the chlorine partial pressure and the power density are such that the etching is anisotropic.
5. A method as claimed in claim 4 wherein said apparatus comprises a parallelplate reactor in which the chlorine partial pressure is approximately 5 microns, the chlorine gas is introduced at a rate of approximately 10 cubic centimetres per minute and the power density at the surface being etched is approximately 0.25 watts per square centimetre.
6. A method as claimed in any of the preceding claims wherein the surface to be etched is of doped polycrystalline silicon having a patterned masking layer thereon, and wherein the opposite surface of the body is maintained in electrical contact with the cathode electrode.
7. A method as claimed in any of claims 1 to 3 wherein the surface to be etched is of doped polycrystalline silicon having a patterned masking layer thereon and wherein the body is not in electrical contact with the cathode electrode.
8. A method as claimed in any of the preceding claims wherein the gas comprises at least fifty per cent by volume of chlorine.
9. A method as claimed in claim 8 wherein the gas is a mixture of helium and chlorine.
10. A method as claimed in claim 8 wherein the gas is a mixture of chlorine and an additive consisting of nitrogen or a noble gas, the additive constituting not more than twenty-five per cent by volume of the mixture.
11. A method as claimed in claim 8 wherein the gas is substantially pure chlorine.
12. A method of etching substantially as herein described with reference to the accompanying drawings.
1 3. A method of etching substantially as herein described with respect to any of the examples.
GB8103292A 1980-02-06 1981-02-03 Reactive sputter etching of silicon Expired GB2068286B (en)

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US11910380A 1980-02-06 1980-02-06

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JP (1) JPS56130928A (en)
CA (1) CA1148895A (en)
DE (1) DE3104024A1 (en)
FR (1) FR2478421A1 (en)
GB (1) GB2068286B (en)
NL (1) NL190592C (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5149676A (en) * 1990-06-22 1992-09-22 Hyundai Electronics Industries Co., Ltd. Silicon layer having increased surface area and method for manufacturing

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3606959A1 (en) * 1986-03-04 1987-09-10 Leybold Heraeus Gmbh & Co Kg DEVICE FOR PLASMA TREATMENT OF SUBSTRATES IN A PLASMA DISCHARGE EXCITED BY HIGH FREQUENCY
JPH0831439B2 (en) * 1986-03-05 1996-03-27 株式会社東芝 Reactive ion etching method
DE3935189A1 (en) * 1989-10-23 1991-05-08 Leybold Ag Ionic etching substrates of silicon di:oxide coated - with poly-silicon or silicide layers-using etching gas of chlorine, silicon chloride and nitrogen

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4104086A (en) * 1977-08-15 1978-08-01 International Business Machines Corporation Method for forming isolated regions of silicon utilizing reactive ion etching
US4226665A (en) * 1978-07-31 1980-10-07 Bell Telephone Laboratories, Incorporated Device fabrication by plasma etching

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5149676A (en) * 1990-06-22 1992-09-22 Hyundai Electronics Industries Co., Ltd. Silicon layer having increased surface area and method for manufacturing
US5304828A (en) * 1990-06-22 1994-04-19 Hyundai Electronics Industries Co., Ltd. Silicon layer having increased surface area and method for manufacturing

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FR2478421B1 (en) 1983-12-23
NL8100560A (en) 1981-09-01
NL190592B (en) 1993-12-01
DE3104024C2 (en) 1988-08-18
NL190592C (en) 1994-05-02
CA1148895A (en) 1983-06-28
GB2068286B (en) 1984-07-11
FR2478421A1 (en) 1981-09-18
JPS56130928A (en) 1981-10-14
DE3104024A1 (en) 1981-12-17

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