GB2067018A - Electronic device packages - Google Patents

Abstract

An electronic device package (100) is disclosed in which one or more attendant devices (103) required for, say, an integrated circuit (101) contained in the package are fabricated as part of the package itself (Fig. 1).

Description

SPECIFICATION Electronic device packages This invention relates to electronic device packages.

There have been numerous prior art electronic device packaging arrangements for enclosing or supporting an electronic device such as an integrated circuit (IC) chip. These # prior art packaging arrangements have, in some situations, also served an auxiliary but similar function as a support structure for attendant devices such as pull up resistors or filter capacitors. In these cases the attendant devices are "piggybacked" onto the existing packaging arrangement and then interconnected with the IC chip via free-standing conductors.

According to one aspect of the present invention there is provided an electronic device package comprising a monolithic structure of dielectric material configured in the shape of a package for an electronic device, and interconnecting means incorporated in said dielectric material for making connection to an electronic device when packaged therein, in which the dielectric material and the interconnecting means of the package itself constitute at least one electronic component having a required impedance characteristic.

In this way required attendant devices such as resistors, capacitors or inductors are incorporated within the material of the package itself so obviating the need for "piggybacked" arrangements. The package may be used for containing an integrated circuit (IC) and may be used to protect the IC from a potentially damaging environment or it may be the support structure on which the IC is mounted.

The dielectric material of the electronic device package may be ceramic or some other suitable material such as glass or polymer.

In U.S. patent No. 3,845,365 there is disclosed an improved method for making a low cost discrete multilayer capacitor using a glass-ceramic material for the dielectric and noble metal materials for the electrodes, wherein both sets of these materials can be cofired to make the discrete capacitor in a single operation. Thus, there is disclosed that by using methods known to the art, conducting materials, resistive materials, etc. can be fired or cofired into a ceramic matrix in arrangements that result in the required electrical characteristics.

In accordance with another aspect of the present invention there is provided a method of fabricating an electronic device package in accordance with the aforesaid first aspect of the present invention, the method comprising the steps of forming the dielectric material in a green state into the shape of said package whilst incorporating at least one conductive region into the dielectric material in a predetermined pattern, and heat treating the formed package to form a substantially monolithic unit.

Some exemplary embodiments of the invention will now be described reference being made to the accompanying drawings in which; Figure 1 is a cutaway diagram of an integrated circuit dual in-line DIP package in accordance with the present invention; Figure 2 is a cross-sectional view of the package of Fig. 1; Figure 3 is a perspective view of the package of Fig. 2 partially cut-away to reveal an incorporated capacitor; Figure 4 is a similar view to that of Fig. 3 wherein two capacitors connected to a common lead are fabricated into the package; Figure 5 illustrates a package according to the present invention wherein an inductor is fabricated into the package; and Figure 6 shows the package of Fig. 3 with a resistor layered over the single capacitor.

In order to simplify the description of the present invention, no mention will be made of the exact composition of materials or processing times used to fabricate the package since these factors can vary substantially depending upon the exact characteristics and component values required. The known art, such as the above-referenced patent, illustrate various combinations of materials that can be used to achieve the attendant device required, be it conductor, dielectric, capacitor, or resistor and to digress into a technical discussion of these matters is beyond the scope of this invention.

Also, at this point in the description, a definition of the terminology employed herein is appropriate. Many terms have vague and often overlapping meanings, therefore, for the purpose of this description, the word conductive will describe an element that carries electric current and would include conductors and also resistive elements. The term dielectric will describe a material that will pass an electric field but does not conduct electricity.

In Fig. 1, a dual in-line IC package (DIP) 100 is shown with the bottom part cut away to reveal the enclosed integrated circuit, 101.

Integrated circuit 101 is connected by leads 102 to circuit elements 103 and 104 that have been fabricated into the top of DIP package 100. Fig. 2 shows the cross section of circuit element 103 (a capacitor) shown in Fig. 1, which element is incorporated into the enclosing package 100 of an integrated circuit. As in Fig. 1, circuit element 103 is shown in the top of DIP package 100. Integrated circuit 102 is attached in conventional fashion to package 100 which is composed of dielectric material 200. Package 100 includes two regions of conductor material 201, 203 configured as two parallel sheets separated by a region of the dielectric material 200. Thus, this arrangement of materials comprises an attendant device 103 which exhibits the characteristics of a capacitor.Leads.202 and 204 connect capacitor plates 201 and 203, respectively, via terminals 205 and 206, respectively, to integrated circuit 101. Package 200 therefore functions as both an attendant device 103 as well as a package enclosing integrated circuit 101.

Fig. 3- reveals the same package as shown in Figs. 1 and 2 relieved of materials thdt obscure the structure of the capacitor. Conducting materials fused into the package form the plates 201, 203 of capacitor 103. The necessary dielectric is made up of the insulating material of package 200. Integrated circuit 101 is connected to the plates 201, 203 of capacitor 103 by means of terminals 205, 206 which are connected to the illustrated leads 202, 204. Although the drawing shows conductors and insulator as separate, it must be borne in mind that both conductor and insulator comprise a monolithic structure which is part of the whole chip enclosure. It should be noted here that the attendant devices may be directly connected to integrated circuit 101, rather than connected by employing terminals 205, 206 and leads 202, 204.

In particular, in Fig. 2, capacitor plate 201 may be directly connected to the bottom of integrated circuit 101 simply by eliminating part of the dielectric material 200 that is shown in Fig. 2 separating the two.

Several layers of capacitor plates can be built into a single package. Fig. 4 shows two capacitors connected to a common lead. To the right side of the drawing is the common terminal 401 that provides a conducting path between common plates 402 and the lead 403 from integrated circuit 101. Other IC leads 404, 405 connect from integrated circuit 101 to terminals 406, 407 respectively that serve the remaining plates 408 and 409.

The illustrated capacitors may be used, for example, to filter several power supplies. Capacitors may have common plates as shown, or may be built separately.

Both capacitors and resistors are commonly used with integrated circuits. Fig. 6 exemplifies a means whereby the two can be incorporated into an IC chip enclosure as taught by the subject invention. In Fig. 6, a layer of resistive material 601 is fused into the enclosure (as is a capacitor) and connected to integrated circuit chip 101 as the conductor material in the previous examples. In particular, resistive material forms terminals 610, 611 which connect resistor 601 to integrated circuit 101 via leads 603 and 602, respectively. The underlying capacitor, comprised of plates 606 and 608, are connected via terminals 607, 609 and leads 604, 605, respectively, to integrated circuit 101 as described above.

Any material that can be incorporated into the substance of the enclosure may be used to compose part of a circuit element. Fig. 5 illustrates magnetic material 501 that increases the inductance of the conductor 502 surrounding it. An inductor circuit is shown in Fig. 5 wherein leads 503 and 504 from integrated circuit 101 are connected to the extremes (at the right and left sides of the drawing) of the inductor at terminals 505 and 506.

The package structure disclosed above may be achieved in numerous ways. A preferred method entails fabricating a layer of dielectric material in the green or unfired state into the basic shape of an electronic device package, then fabricating the attendant device(s) on top of this basic package. To wit, in the case of a capacitor, a region of conductor material in the green state would be applied in the shape and size of a capacitor plate to the surface of the basic electronic device package. This conductor region would be overlaid by a region of dielectric material in the green state followed by another region of conductor material in the green state in the size and shape of the second capacitor plate.This resultant combination would then be covered by another layer of dielectric material in the green state to protect the attendant device from the ambient environment and to complete the electronic device package structure. This entire structure would then be heat treated in appropriate fashion to form a substantially monolithic unit.

The exact details of this fabrication procedure would be dependent upon the materials selected to fabricate the package as well as the exact package and attendant device characteristics desired. This fabrication process may include drying or firing each layer of material in the green state after it is applied, employing elevated temperature, applying pressure or a vacuum, as well as various methods of forming the dielectric material into the shape of a device package and applying the attendant device structure in the green state to the basic electronic device package.

While a specific embodiment of our invention has been disclosed, variations in structural detail within the scope of the appended claims are possible and are contemplated. There is no intention of limitation to what is contained in the abstract or the exact disclosure as herein presented.

Claims (10)

1. An electronic device package comprising a monolithic structure of dielectric material configured in the shape of a package for an electronic device, and interconnecting means incorporated in said dielectric material for making connection to an electronic device when packaged therein, in which the dielectric material and the interconnecting means of the package itself constitute at least one electronic component having a required impedance characteristic.

2. A package as claimed in claim 1, comprising at least one conductive member incorporated in the dielectric material of the package for affording the required impedance characteristic.

3. A package as claimed in claim 2, in which the conductive member comprises resistive material whereby said package affords a resistive characteristic.

4. A package as claimed in claim 2 or claim 3, comprising a plurality of flat spaced apart conductive regions whereby said package affords a capacitive characteristic.

5. A package as claimed in any of claims 2 to 4, in which the conductive member constitutes an inductor whereby said package affords an inductive characteristic.

6. A package as claimed in claim 5, comprising magnetic material which forms a core for said inductor.

7. A method of fabricating an electronic device package in accordance with any preceding claim, comprising the steps of forming the dielectric material in a green state into the shape of said package whilst incorporating at least one conductive region into the dielectric material in a predetermined pattern, and heat treating the formed package to form a substantially monolithic unit.

8. A method as claimed in claim 7, in which the heat treating step includes subjecting the formed package to elevated temperature to cause it to coalesce, and heat treating the formed package to form a glass ceramic out of the dielectric material and to sinter the conductive region.

9. A method as claimed in claim 7 or claim 8, comprising the steps of forming the dielectric material in the green state into the shape of an electronic device package, performing the following application steps one or more times: applying one or more conductive films to the dielectric material in a predetermined pattern, applying a layer of the dielectric material in the green state in a predetermined pattern over the conductive films; and heat treating the dielectric material-conductive film combination to form a substantially monolithic unit.

10. An electronic device package substantially as hereinbefore described with reference to the accompanying drawings.