GB2065370A - Methods of making semiconductor bodies for integrated circuits - Google Patents

Methods of making semiconductor bodies for integrated circuits Download PDF

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GB2065370A
GB2065370A GB8039459A GB8039459A GB2065370A GB 2065370 A GB2065370 A GB 2065370A GB 8039459 A GB8039459 A GB 8039459A GB 8039459 A GB8039459 A GB 8039459A GB 2065370 A GB2065370 A GB 2065370A
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concave portion
forming
growth layer
semiconductor
semiconductor growth
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Seiko Instruments Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02543—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The side walls of a recess or cavity in a semiconductor substrate (10, 13) are masked with an insulating layer (7) before depositing material (113) in the cavity by vapour phase epitaxy. The deposition is terminated when the surface is level with that of the substrate. A small groove (V3) is left at the edge of the epitaxial region as opposed to an extension of the monocrystalline material onto the upper face of the mask which occurs if the sides of the recess are exposed. The masking layer may also cover part of the floor of the recess. In a double stage embodiment the epitaxial growth is continued to project above the original surface the recess thus defined is filled by the same method. Various semiconductor devices may be formed in the different surface regions to form an integrated circuit. <IMAGE>

Description

SPECIFICATION Method of making integrated circuits This invention relates to methods of making integrated circuits and more particularly, although not so restricted, to methods of making integrated circuits including various types of field effect transistors, for example, integrated circuits including field effect transistors and bipolar transistors, and integrated circuits having transistors which have different structural parameters, such as different impurity concentration and/or different conductivity type and/or different thickness of an epitaxial growth layer etc.
Field effect transistors can be roughly classified into those of the insulation gate type (MIS), those of the junction gate type (BJT), static induction transistors (SIT) and field effect transistors (FET) having similar characteristics to those of pentodes. A bipolar transistor is one such kind of transistor. Although a SIT has advantages of higher speed operation and lower power consumption compared to other types of transistor, a low impurity concentration region of less than 1015 cm - 3 is generally required. On the other hand, although a MIS. FET has advantages of lower speed operation with lower DC power consumption, an impurity concentration layer of more than 1014 cm~3 is generally required.In addition, SITs and BJTs have a relatively large current density capacity and so SITs are ideal for voltage regulating operation and BJTs are ideal for constant current operation.
In integrated circuits for timepieces, it is desirable to use SITs for a crystal controlled oscillator circuit and for the part of a frequency divider circuit which operates at relatively high speed, and to use MOS.FETs for the part of the frequency divider circuit which operates at relatively low speed and to use BJTs or SITs for a stepping motor driving circuit. Moreover, SITs and BJTs may be used for linear circuits, such as, for example, constant voltage source circuits and constant current source circuits. Considering, for example, the channel portion of a SIT integrated circuit, there are many structural factors, such as thickness and impurity concentration which affect, for example, frequency characteristics and amplification factors.It is, therefore, preferable that SITs having various structural pa rameters are incorporated on the same substrate in order to realise an integrated circuit having all the advantages-of high efficiency, multi-function and relatively low power consumption.
The present invention seeks to provide a method of making an integrated circuit by forming two or more regions of different impurity concentration, conductivity type and thickness in such a way that the surface levels of these regions are substantially the same, semiconductor devices being formed in each of the regions. The present invention also seeks to provide a method of making an integrated circuit in which photo-lithography is easily and accurately carried out because the said regions are at the same level, and in which transistors have different structural parameters and characteristics are incorporated on to the same substrate. As a result, it may be possible to include semiconductor devices which previously were formed on two or more chips, on a single integrated circuit and achieve higher performance.
According to the present invention there is provided a method of making an integrated circuit comprising the steps of: forming a concave portion on a single crystal semiconductor substrate; forming an insulating layer on the faces of said concave portion except in a a region of a bottom face thereof; forming a semiconductor growth layer on said bottom face by a vapour deposition technique using a gaseous mixture of the chloride of the semiconductor material and hydrogen, in such a way that an upper surface of the semiconductor growth layer is at substantially the same level as an upper surface of the concave portion; and forming a semiconductor device in said semiconductor growth layer.
In a preferred embodiment the method comprises the steps of forming a first concave portion on said substrate, forming a first semiconductor growth layer on a bottom face of the first concave portion so that an upper surface of the first semiconductor growth layer is higher than an upper surface of the substrate, depositing said insulating film on said semiconductor growth layer but not on a bottom face of a second concave portion defined by said first semiconductor growth layer, forming a second semiconductor growth layer on said bottom face of the second concave portion in such a way that an upper surface of the second semiconductor growth layer is at substantially the same level as the upper surface of the first semiconductor growth layer.
The method may include forming a high impurity concentration region on the faces of the concave portion prior to forming said insulating film and said semiconductor growth layer. Alternatively the method may include forming a high impurity concentration region on the faces of the first concave portion prior to forming said first semiconductor growth layer.
In one embodiment the method includes forming at least one insulated gate type field effect transistor in said substrate and at least one bipolar transistor or junction type field effect transistor in said semiconductor growth layer. In another embodiment the method includes forming a junction type field effect transistor in said first semiconductor growth layer and a field effect transistor or a bipolar transistor in said second semiconductor growth layer.
The invention is illustrated, merely by way of example, in the accompanying drawings, in which: Figures 1 (a) to 1 (c) are sectional views illustrating one conventional method of making an integrated circuit; Figures 2(a) and 2(b) are sectional views illustrating another conventional method of making an integrated circuit; Figure 3(a) to 3(c) illustrate the steps of one method according to the present invention for making an integrated circuit; Figures 4(a) and 4(b) illustrate the steps of another method according to the present invention for making an integrated circuit; and Figures 5(a) to 5(e) illustrate the steps of yet another method according to the present invention for making an integrated circuit.
Throughout the drawings like parts have been designated by the same reference numerals.
Figs. 1 (a) to 1 (c) are sectional views illustrating the conventional steps for forming a vertical junction type SIT and a MOS.FET on the same integrated chip. Fig. 1 (a) shows an n region 11 formed on a portion of an ntype silicon substrate 20 with an impurity concentration of approximately 1 0 15cm An n - epitaxial layer 13 with an impurity concentration of approximately 1013cm-3 is deposited on the substrate. The n region 11 is a buried layer which, in the completed integrated circuit, will form a main electrode of a SIT.The thickness of the n- epitaxial layer 13 is between 5 and 20 ym, its actual thickness being determined by the desired characteristics of the SIT to be formed. Fig.
1(b) shows a concave portion V3 formed in the n- epitaxial layer 13 and extending to the n+ region 11. This concave portion V3 is formed by selectively etching the n- epitaxial layer using an oxide mask. A concave portion V for > MOS.FET is formed similarly and extends to the substrate 10. Since the concave portion V3 is shallower than the portion V, at least two etching steps are required and each depth of the portions should be the same as the thickness of the n- epitaxial layer 13. Subse quentiy p+ gate regions 14 of the SIT, a p+ source region 112 of the MOS.FET and a p+ drain region 111 of the MOS.FET are formed by using a p ' selective diffusion technique.
Then, an n r source region 1 2 of the SIT and an n F drain region 21 thereof are formed by using an n selective diffusion technique. An n+ source-drain region is formed within a preformed p well if an N-channei MOS.FET is to be formed.
Fig. 1 (c) shows a drain electrode 1, a source electrode 2 and a gate electrode 4 of the SIT and electrodes 101 102, 104 of the MOS.FET. these electrodes being formed by a selective etching technique of an insulating film 7 and subsequent evaporation of metal through windows formed in the insulating film 7 by the etching technique. It is particularly important to align a mask on the insulating film accurately in order to form the windows for the electrodes of the SIT and MOS FET in the correct positions. To perform this step, a mask and a photoresist are coated over the insulating layer and photographically exposed However, tight exposure is impossible due to the concave portions so that the windows cannot be formed to a high degree of accuracy.Recently, a projection exposing process has been suggested but due to depth of focus, accuracy is not greatly improved since the top face and the bottom face of the concave portion V have to be exposed at the same time. Moreover, the probiems of nonuniformity of thickness of the photoresist, cutting off of metal wiring are problems that have to be solved in the future. Moreover, the characteristics of each transistor on the integrated circuit depend on parameters such as conductivity type of each region, impurity concentration, thickness etc., but it is far from simple to vary these parameters using, for example the conventional method of Fig. 1.
Moreover, it is not always desirable to form the n+ buried layer by a deep diffusion tech niqtue because a heating process of relatively long duration is required.
In an attempt to overcome the above described defects or problems, a conventional buried epitaxial growth technique has been employed. Another conventional method of making an integrated circuit and using this technique is illustrated in Figs. 2(a) and 2(b).
In this method an epitaxial growth technique is carried out after the insulating film 7 is deposited on the substrate 10 and an opening has been formed in the insulating film and the concave portion V has been etched (Fig. 2(a)).
As shown in Fig. 2(b), the concave portion V is perfectly filled with a single crystal growth layer 13 and a polycrystal growth layer 33 is deposited on the insulating film 7 at the same time. However, a projecting region 23 is formed on the edge of the concave portion V due to the single crystal growth layer 13 growing in the vertical direction. Thus the polycrystal growth layer 33 and the projecting portion 23 have to be removed by polishing the upper surface at relatively high speed.
However, this results in the surface of the substrate 10 being scratched. To avoid the necessity for the polishing step, it has been proposed to form the insulating film 7 so that it overhangs the concave portion V, or to form it by a CVD technique including gaseous HCI.
However, it is impossible then to fill concave portions of different depths at the same time and to obtain a flat upper surface to the integrated circuit. To avoid this defect various methods, for example as disclosed !n 4apa- nese Patent Applicatons Nos 8303 t 74 and 63032/79 have been proposed. However, these methods impose a limitation of size since they require that the surface of the substrate is a low figure surface such as, (111), (113), (112) surfaces and the width of the concave portion has to be more than twice the interval of produced growth nucleations to obtain any remarkable effect.
Figs. 3(a) to 3(c) illustrate the steps of one method according to the present invention for making an integrated circuit. In Fig. 3(a) after an n - epitaxial layer 13 is formed over all the surface of the n+ silicon substrate 10, a concave portion V2 is formed by a conventional selective etching technique, such as, a low temperature dry etching technique involving plasma etching and ion etching, a gas etching technique using, for example, HCI and H2, an etching technique using HF or an etching technique using an alkali aqueous solution, for example, APW. An n+ buried layer 11 is formed on the side faces and bottom face of the concave portion V2 by a selective diffusion technique.The top face of the concave portion V2 i.e. the upper surface of the n- epitaxial layer 13 and the side faces thereof are then covered with an insulating film 7 of, for example, silicon dioxide. As shown in Fig. 3(b) an n type epitaxial layer 113 is formed by a selective growth technique in such a way that the upper surface thereof is at the same level as that of the n - epitaxial layer 13. At this time, since the insulating film 7 which is used as a mask for this selective growth technique covers the side faces of the concave portion V2, no projecting portion such as the projecting portion 23 shown in Fig. 2(b) is formed. However, a relatively shallow concave portion V3 is formed adjacent the n- epitaxial layer 13.
Due to auto-doping an impurity diffusion during the selective growth technique, the n + buried layer 11 rises on the side of the rrtype epitaxial layer 113. The selective growth technique may be carried out using a gaseous mixture of SiCI4 and H2 (Mol ratio of SiCI4 is equal to or more than 0.5%) at a temperature between 1000 C and 1150do, with the maximum width of the insulating film being not more than 1 mm. so that no polycrystal layer is deposited on the insulating film 7. The required thickness of the insulating film 7 is, however, usually approximately more than 1000 A but a thermal oxidation film or a CVD film is generally used when its thickness is more than 5000 . After this, transistors are formed in each of the regions using conventional techniques.A vertical type SIT having an n+ source region 12 and p+ gate region 14 are formed in the n - epitaxial layer 13 and a P-channel MOS.FET having a p+ source region 112, a p + drain region 119 and gate region 114 is formed in the n-type epitaxial layer 113.
Fig. 3(c) is a sectional view of the completed integrated circuit. The buried layer 11 is led out through the n+ diffusion layer on the side face of the concave portion V2 from the concave portion V3. An IIL type SITL or other types of logic circuit may also be formed in the n- epitaxial layer 13, and it will be appreciated that a bipolar transistor, a FET, or any other type of transistor or transistor circuit may also be formed therein. A ptype layer may be employed instead of the type epitaxial layer 113, and an N-channel MOS transistor, a P-channel SIT, an FET or the like may be incorporated therein.A p+ buried layer can be used instead of the n + buried layer 11 and moreover opposite conductivity type of impurity may be diffused during the epitaxial growth technique on to the side faces and the bottom face of the concave portion V2. These modifications and variations are dictated by the desired characteristics of the integrated circuit to be formed.
The method described in connection with Figs. 3(a) to 3(c) require two or more epitaxial layers which are different in impurity concenoration or conductivity type.
Figs. 4(a) and 4(b) illustrate another method according to the present invention for making an integrated circuit where both the portion close to the surface of the substrate 10 and the epitaxial layer are used so that, for exam ple, a junction type transistor and an MOS transistor are formed.
Referring to Fig. 4(a), after a concave portion V2 is formed on a Rtype substrate 10, an n + buried layer 12 (for example to form an n+ source region) is formed on the side faces and the bottom face of the concave portion V2 by a diffusion technique, and an opening is defined in at least one portion of an insulating film 7 in the region of the bottom face of the concave portion V2. Next, a selective epitaxial growth technique is performed in a similar way to that illustrated in the preceding embodiment to form an n- epitaxial growth layer 1 3 in such a way that the upper surface of the n- epitaxial growth layer 13 is at the same lever as the substrate 10 and only shallow concave portions remain. This is shown in Fig. 4(b).As described above, a vertical junction type SITL or 12L type SITL can be formed in the n- epitaxial growth layer 13 and it is easy to incorporate a Nchannel MOS.FET or circuit into the surface of the substrate 10. The conductivity type and impurity concentration of the substrate, the buried layer 12 and the n- epitaxial growth layer 13 can be properly determined in accordance with the characteristics of the integrated circuit to be formed.
Figs. 5(a) to 5(e) illustrate the steps of yet another method according to the present invention for making an integrated circuit. The integrated circuit in this embodiment has SITs and BJTs. Fig. 5(a) shows a first concave portion V, formed on a ptype substrate 10 using a mask constituted by a silicon nitride (Si3N4)film 8. A n + buried layer 12 is formed on the bottom face and side faces of the concave portion V1 using the film 8 as a mask by means of a combined oxidation and selective diffusion technique. Then an oxide insulating film 7 on the bottom face of the first concave portion V1 is removed using, for example, a conventional photo-lithography technique, and ion etching technique or a directional plasma etching technique.
Fig. 5(b) illustrates the step in which a nepitaxial growth layer 13 with a thickness of, for example, 8 ym is formed by an epitaxial growth technique. The n- epitaxial growth layer 13 has a thickness greater than the depth of the first concave portion V, which, for example, has a depth of 5,us. Thus a projecting portion, relative to the concave portion V2, with a width of 20 ym is formed. The n- epitaxial growth layer 13 has an impurity concentration of 5 x 10'3 cm-3.
Next, as illustrated in Fig. 5(c), a selective oxidation technique is performed using the film 8 to form a further oxide insulating film 7 on the top face and side faces of the n - epitaxial growth layer 13 and then the film 8 is removed.
Fig. 5(d) shows the formation of an n+ epitaxial growth layer 22 by a selective epitaxial growth technique. The n+ growth layer 22 has a thickness of 0.5 #m and an impurity concentration of, for example, 1 x 10'9 cm 3.
An n epitaxial growth layer 113 with a thickness of 2.5 #m and for example an impurity concentration of 1 X 10'5 cm - 3 is then formed except on the n- epitaxial growth layer 13 by a selective epitaxial growth technique. This is relatively easy to perform since the portion masked by the insulating film 7 is small.
Finally, as illustrated in Fig. 5(e), an upward or vertical type SIT, and nf source region of which is constituted by the buried layer 12, is warmed with a p+ gate region 14 and a n+ drain region 11 in the n - epitaxial growth layer 13. An upward or vertical type npn BJT, an emitter region of which is constituted by the n + epitaxial growth layer 22, is formed with a p base region 214 and a pf base region 204 and an n+ collector region 211 in the n epitaxial growth layer 113. An electrode 202 for the buried layer is formed through the n+ epitaxial growth layer 22 and an n+ region 222.
In this embodiment of the present invention a lower impurity concentration region is required for the SIT and a thin and relatively low impurity concentration region for the BJT are formed in such a manner that the surface level of the region for the SIT is equal to that of the region for the BJT, as a result of which, an integrated circuit which has both the advantage of the high frequency characteristics of the SIT and the constant current characteristics of the BJT can be easily fabricated and can be realised without cutting-off metal wiring, deviation of distribution of thickness of the photo-resist film etc.
In the embodiments of the present invention described above a selective growth technique is carried out once or twice. However it will be appreciated that the number of times the selective growth technique is carried out depends upon the construction of the integrated circuit to be made. Impurity concentration, conductivity type and thickness of the epitaxial growth layers are also determined by the construction of the integrated circuit to be made. The presence or absence of a buried layer, the conductivity type thereof and the resistivity thereof are also dependent upon the construction of the integrated circuit to be made. As seen from Fig. 5. the buried layer 12 on the side face of the concave portion is used as a diffusion layer for isolation and moreover, the insulating film 7 is buried. As a result, the insulating film 7 is also used as an isolating layer and the diffusion layer 12 may be omitted. This construction is advantageous from the point of view of high density packing.
The present invention has been described in relation to silicon semiconductors but it is also applicable to other types of semiconductors, such as, Ge, Ga As, Ga P, In Ga P, Ga Al As, etc. for which a selective growth technique can be effected by using the chloride of the semiconducting material. The same effect can also be obtained when a liquid growth technique is employed.

Claims (10)

1. A method of making an integrated circuit comprising the steps of: forming a concave portion on a single crystal semiconductor substrate; forming an insulating layer on the faces of said concave portion except in a region of a bottom face thereof; forming a semiconductor growth layer on said bottom face by a vapour deposition technique using a gaseous mixture of the chloride of the semiconductor material and hydrogen, in such a way that an upper surface of the semiconductor growth layer is at substantially the same level as an upper surface of the concave portion; and forming a semiconductor device in said semiconductor growth layer.
2. A method as claimed in claim 1 comprising the steps of forming a first concave portion on said substrate, forming a first semiconductor growth layer on a bottom face of the first concave portion so that an upper surface of the first semiconductor growth layer is higher than an upper surface of the substrate, depositing said insulating film on said semiconductor growth layer but not on a bottom face of a second concave portion defined by said first semiconductor growth layer, forming a second semiconductor growth layer on said bottom face of the second concave portion in such a way that an upper surface of the second semiconductor growth layer is at substantially the same level as the upper surface of the first semiconductor growth layer.
3. A method as claimed in claim 1 including forming a high impurity concentration region on the faces of the concave portion prior to forming said insulating film and said semiconductor growth layer.
4. A method as claimed in claim 2 including forming a high impurity concentration region on the faces of the first concave portion prior to forming said first semiconductor growth layer.
5. A method as claimed in claim 1 or 3 including forming at least one insulated gate type field effect transistor in said substrate and at least one bipolar transistor or junction type field effect transistor in said semiconductor growth layer.
6. A method as claimed in claim 2 or 4 including forming a junction type field effect transistor in said first semiconductor growth layer and a field effect transistor or a bipolar transistor in said second semiconductor growth layer.
7. A method of making an integrated circuit substantially as herein described with reference to Figs. 3(a) to 3(c) or Figs. 4(a) and 4(c) or Figs. 5(a) to 5(e).
8. An integrated circuit when made by the method as claimed in any preceding claim.
9. A method of fabricating integrated circuits which comprises the steps of: forming a relative concave portion V2 on a semiconductor single-crystal substrate; forming insulating film on the surface and the side face of said concave portion V2 except for at least one portion of the bottom face of said concave portion V2 after depositing insulating film on the surface of said substrate; forming semiconductor growth layer on the bottom face of said concave portion V2 by CVD method using a mixture gas containing semiconductor chloride and hydrogen in such a way that top surface of the layer is the same level of the upper face of said concave portion V2; and, fabricating semiconductor devices in said substrate and said growth layer.
10. A method for fabricating integrated circuits as claimed in claim 9 wherein the step of forming said concave portion V2 is composed of the steps of depositing a first insulation film on a first substrate after forming another concave portion V, and defining opening in said first insulation film of at least one portion of bottom face of said another concave portion V,; and, selectively forming a first semiconductor growth layer on the bottom face of said another concave portion V, by said CVD method in such a way that the level of top face of said layer is higher than that of the surface of said first concave portion V2 in order to relatively form concave portion.
GB8039459A 1979-12-11 1980-12-09 Method of making semiconductor bodies for integrated circuits Expired GB2065370B (en)

Applications Claiming Priority (1)

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JP16046179A JPS5683046A (en) 1979-12-11 1979-12-11 Manufacture of integrated circuit

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GB2065370A true GB2065370A (en) 1981-06-24
GB2065370B GB2065370B (en) 1983-11-23

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3225398A1 (en) * 1981-07-07 1983-01-27 Nippon Electric Co., Ltd., Tokyo SEMICONDUCTOR DEVICE AND METHOD FOR THEIR PRODUCTION
FR2547954A1 (en) * 1983-06-21 1984-12-28 Efcis PROCESS FOR PRODUCING ISOLATED SEMICONDUCTOR COMPONENTS IN A SEMICONDUCTOR WAFER
EP0156964A1 (en) * 1983-11-18 1985-10-09 Motorola, Inc. Means and method for improved junction isolation
US5476809A (en) * 1993-05-22 1995-12-19 Nec Corporation Semiconductor device and method of manufacturing the same
GB2368726A (en) * 2000-08-11 2002-05-08 Samsung Electronics Co Ltd Selective epitaxial growth method in semiconductor device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59204252A (en) * 1983-05-06 1984-11-19 Matsushita Electronics Corp Manufacture of semiconductor integrated circuit
US4660278A (en) * 1985-06-26 1987-04-28 Texas Instruments Incorporated Process of making IC isolation structure
JP2701881B2 (en) * 1987-09-28 1998-01-21 テキサス インスツルメンツ インコーポレイテツド Semiconductor isolation region

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3225398A1 (en) * 1981-07-07 1983-01-27 Nippon Electric Co., Ltd., Tokyo SEMICONDUCTOR DEVICE AND METHOD FOR THEIR PRODUCTION
FR2547954A1 (en) * 1983-06-21 1984-12-28 Efcis PROCESS FOR PRODUCING ISOLATED SEMICONDUCTOR COMPONENTS IN A SEMICONDUCTOR WAFER
EP0135401A1 (en) * 1983-06-21 1985-03-27 Sgs-Thomson Microelectronics S.A. Process for producing isolated semiconductor components in a semiconductor substrate
US4679309A (en) * 1983-06-21 1987-07-14 Societe Pour L'etude Et La Fabrication De Circuits Integres Speciaux E.F.C.I.S. Process for manufacturing isolated semi conductor components in a semi conductor wafer
EP0156964A1 (en) * 1983-11-18 1985-10-09 Motorola, Inc. Means and method for improved junction isolation
US5476809A (en) * 1993-05-22 1995-12-19 Nec Corporation Semiconductor device and method of manufacturing the same
GB2368726A (en) * 2000-08-11 2002-05-08 Samsung Electronics Co Ltd Selective epitaxial growth method in semiconductor device
GB2368726B (en) * 2000-08-11 2002-10-02 Samsung Electronics Co Ltd Selective epitaxial growth method in semiconductor device

Also Published As

Publication number Publication date
GB2065370B (en) 1983-11-23
JPS5683046A (en) 1981-07-07

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