GB2065354A - Addressing liquid crystal displays - Google Patents

Abstract

In a method of selectively addressing a liquid crystal (LC) matrix display, a dyed cholesteric-nematic phase-change cell has all elements periodically accessed in a random sequence at a rate substantially higher than the switching speed of the LC. Except those which are required to switch from 'on' to 'off' or vice versa, all the elements are driven with a random 'sustain' sequence of +V, -V and 0V which when integrated approximates to V/ 2ROOT 2 r.m.s. (3a-3c=3f). Elements which are to be turned 'off' are driven over a number of cycles with zero applied voltage (3a-3d=3g). Elements which are to be turned 'on' are correspondingly driven with a random sequence of +V and -V only (3a-3b=3e). <IMAGE>

Description

SPECIFICATION Addressing liquid crystal displays This invention relates to a method and means for selectively addressing liquid crystal displays in matrix form.

There is considerable interest in producing panels for displaying alphanumeric and other complex information which do not rely on the cathode ray tube. Liquid crystal display panels have many desirable features for this applicaton, such as flat construction with minimal thickness and relatively low voltage requirements. For a large display the obvious way to drive the individual display elements is using orthogonal sets of drive electrodes on each glass substrate to minimise interconnection problems. For twisted nematic liquid crystals and other "single threshold" electro-optic effects the display is then scanned in a conventional multiplexing scheme. This, however, requires that the element has a sharp (ideally, a step function) optical threshold.For a twisted nematic display viewed by reflected light the number of ways that can be multiplexed at present for good contrast and viewing angle is less than 10, hence for say a 1 28 X 1 28 matric display more than 1 500 connections would be required.

An alternative liquid crystal is that known as the cholesteric-nematic phase change display with a dye added for enhanced contrast (DCNPC). This type of liquid crystal has been shown to have useful short term memory effects, as described by W. Greubel, Applied Physics Letter 25, No.1, 5-7 (1974) and others. These liquid crystals require a higher voltage to turn 'on' (clear) than to turn 'off' (coloured). Segments (elements) that are below the upper threshold but are 'on' revert to the 'off' state in a time dependent on the liquid crystal mixture, the surface alignment and the applied voltage. Such displays require that segments which are to remain 'on' for any length of time to be 'refreshed' periodically. However, if this refreshing is effected on a line-by-line basis undesirable optical effects are created.Preferably the display is refreshed on segment-by-segment basis with the segments being addressed randomly or pseudorandomly.

Fig. 1 shows the behaviour of a typical DCNPC liquid crystal containing, for example, 93.2% Merck 1132, 4.5% C15, 2.3% D35 with homeotropic alignment. This shows an 'off' to 'on' threshold of about 1 5V r.m.s. and a fast (20 ms) 'on' to 'off' threshold at about 5V r.m.s. If the display is biased 'on' and then has the bias reduced to between 5V and 10V r.m.s. it stays optically 'on' for a time, dependent on the voltage, from about 2 to 20 seconds. During this period if the bias voltage is removed, i.e. zero volts are maintained, for a short time (about 20 ms) and then reapplied, the display turns 'off' optically and will now noticeably come 'on' again.

A pseudo-random method of displaying limited information on a matrix display without special restrictions on the liquid crystal material, in particular its sharpness of threshold, is described in 'Non Multiplexed Addressing Methods for Liquid Crystal Oscilloscope Displays', I.A. Shanks, P.A. Holland and C.J.T.

Smith, Displays, April 1979, pp. 33-41. In that method selected segments of the display, limited to one per column, receive zero voltage drive whilst all others receive an equal r.s.m. voltage. This is achieved in the following way: Each row electrode has applied to it an individual pseudo-random sequence of binary logic levels where logic 1 is typically 1 8 V, logic 0 = O V. The signals on the column electrodes are selected from the row signals on the basis that the one selected segment per column always has equal row and column voltages and hence a net zero voltage drive.

All the other segments of the display receive random sequences of + 1, 0, - 1 logic levels as the display is refreshed frame by frame.

The background of the display therefore has 1 /ç2 of the logic 1 level voltage as its r.m.s.

drive, with zero d.c. content, both averaged over the repeat time of the pseudo-random sequence. The display electrodes are driven by CMOS shift registers operating at up to 1 8 V hence nearly 1 3 V can be supplied to the background areas. The frame repeat time for the circuit must be short compared to the response time of the liquid crystal.

When this type of device is used for twisted nematic displays in parallel polarisers, a single element per column of the display is in the non-transmitting (off) state and all others are clear (on). This has led to the use of this type of display as an oscilloscope and any other display which requires only one selected segment per column. The drive system can also be used with the dyed cholesteric-nematic phase-change (DCNPC) effect with similar results if the background drive is sufficient to turn the display elements clear (on). The selected elements, having zero voltage drive, remain coloured.

According to the present invention a method for selectively addressing a liquid crystal display in matrix form includes accessing the segments (elements) of the display periodically in a random or pseudo-random sequence, applying to the accessed segments generally a random or pseudo-random sequence of + V, - V or 0V at a rate substantially in excess of the turn 'on' or turn 'off speed of the liquid crystal material, said V having a value in excess of the 'off' to 'on' threshold voltage for the liquid crystal material, said voltage sequence when integrated with respect to time approximates to V/ 2 r.m.s., and for selectively addressed segments witholding either the + V, - V values or the OV value, depending on whether an addressed segment is to be in an 'on' state or an 'off' state, said witholding having a duration at least equal to the switching time of the liquid crystal material.

The invention also provides an apparatus for selectively addressing a liquid crystal display in matrix form comprising means for generating a random or pseudo-random sequence of binary logic levels at a rate substantially in excess of the turn 'on' or turn 'off' speed of the liquid crystal material, means for accessing the matrix segments (elements) of the display in accordance with said logic level sequence, means for applying to each of the accessed segments a random or pseudo-random sequence of three voltage levels being respectively + V, - V or OV where V has a value in excess of the 'off' to 'on' threshold voltage of the liquid crystal material, said voltage sequence when integrated with respect to time approximating to V/ç2 r.m.s., and means for modifying the logic level sequence whereby for a selectively addressed segment the applied voltage is either + V or OV for a period of time at least equal to the switching time of the liquid crystal material depending on whether the addressed segment is to be in an 'on' state or an 'off' state.

An embodiment of the invention will now be described with reference to Figs. 2 and 3 of the accompanying drawings, in which: Figure 2 is a block diagram of a liquid crystal display, and Figure 3 illustrates various waveforms appearing in the circuitry of Fig. 2.

For explanatory purposes only it will be assumed that the display consists of a 1 28 x 1 28 matrix of dyed cholesteric-nematic phase change (DNCPC) segments. The DCNPC material is assumed to have a characteristic such as that shown in Fig. 1. It will be noted that there are three basic voltage conditions required. These are: (1) The sustaining voltage When the display segment is neither being driven 'off' nor kept 'on' it has to receive a steady r.m.s. voltage to keep the segment in its bistable mode. This voltage is VA on Fig. 1.

(2) The write voltage Every display segment that is to be 'on' has to be written and rewritten periodically. This is accomplished by supplying a voltage Vc higher than the 'off' to 'on' threshold for a short period (typically 100 ms). When the write voltage is subsequently replaced by the sustain voltage the display remains 'on' at position B on Fig. 1. Ideally the 'on' segments should be rewritten before the decay from point B to point A becomes noticeable, e.g. at point D.

[3) The erase voltage To switch a segment 'off' the voltage has to be reduced to below the 'on' to 'off' thresh Dld, i.e. below VE. The time required is generally about a quarter of the write period.

The pseudo-random pulse addressing method of driving matrix displays is very well suited to the requirements of the hysteresis effect. The sustain voltage is supplied by the normal background r.m.s. voltage. This is not a steady voltage and can have periods of zero volts included. Tests with a cell known to switch off with a 20 ms zero voltage period have shown that a frame time of 400 ys is short enough to avoid false switching. This requirement is within the capabilities of the proposed electronic systems.

The 'write' voltages are achieved by using the pseudo-random pulse circuit with complementary selection. This means that drive on selected segments is either + 1 or - ? (+ 18 V or - 1 8V). This is an r.m.s. voltage /2 times the background voltage. This requires the 'off' to 'on' threshold to have a certain minimum sharpness.

The erase voltage (zero volts) is supplied by operating the pseudo-random pulse circuit with the normal selection.

In the circuit shown in Fig. 2 addressing is accomplished by means of a conventional keyboard input 1 or otherwise. A microprocessor 2 generates a 1 28 x 1 28 bit pattern in response to the keyboard input and this pattern is stored in a memory 3. The microprocessor sends sequences of 1 28 eight-bit words via input buffer 4 to a selected segment memory 5. Each 8-bit word consists of a 7-bit segment address and one status bit designating whether the segment is 'on' or 'off' .

Meanwhile, a pseudo-random generator 6 generates a 128-bit pseudo-random sequence and this sequence is fed via a multiplexer 7 and voltage level shifter 8 to 128-bit shift register 9. The 128-bit sequence is then transferred to a second 128-bit shift register 10. The pseudo-random sequence is simultaneously loaded into a random access memory 11 under the control of addresses generated by a counter 1 2. These addresses are fed to the memory 11 and are also used to access the selected segment memory 5. When the 128-bit sequence from generator 6 is completed the random access memory 11 is accessed, via multiplexer 1 3 using the 7-bit addresses stored in memory 5. As the 128-bit sequence stored in memory 11 is read out it is modified by the 8th bit, which is applied to an Exclusive-OR gate 14 together with the read out 128-bit pattern from memory 11.

This (modified) pattern is fed via multiplexer 7 and level shifter 8 to shift register 9. Thus at the end of the cycle both shift registers 9 and 10 are loaded with 128-bit patterns, and the appropriate voltages are applied to the display.

The whole cycle is repeated at intervals of 300,us. The voltage waveforms are shown in Fig. 3. Fig. 3 (a) shows a typical pseudorandom row voltage sequence, in which the voltage applied to a row of segments has eigher + 1 5V or zero. Fig. 3 (b) illustrates a typical column voltage sequence for a segment which is being turned 'on'. Note that this sequence is the complement of the pseudo-random sequence in Fig. 3 (a). Fig. 3 (c) shows a typical 'sustaining' voltage sequence applied to a column. This is a separate random sequence which alternates between OV and 15V. Fig. 3 (d) shows a typical column voltage sequence for a segment that is being turned 'off'. Note that this sequence is the same as that of Fig. 3 (a).

If now we consider the applied voltage at a given segment, Fig. 3 (e) shows the voltage drive at that segment when that segment is being turned on. Because this drive voltage is the difference between the row and column voltages it alternates between + 1 5V and - 1 5V. Once the segment is turned on it is sustained by a drive voltage that is the difference between the row and column voltages of Figs. 3 (a) and 3 (c) respectively, as shown in Fig. 3 (f). This, being the sum of two pseudorandom sequences, has 3 voltage levels of + V, - V and OV. The result is that the applied voltage when integrated with respect to time approximates to a root mean square value of V/ç2. Finally to turn the segment 'off' the applied voltage, being the sum of Figs. 3 (a) and 3 (d), is zero as shown in Fig.

3 (g). It has been stated that the pseudorandom sequence has a duration of 300 juts.

By contrast the turn 'on' time is probably in the region of 20-100 ms, as is the turn off time.

Claims (6)

1. A method for selectively addressing a liquid crystal display in matrix form includes accessing the segments (elements) of the display periodically in a random or pseudo-random sequence, applying to the accessed segments generally a random or pseudo-random sequence of + V, - V or OV at a rate substantially in excess of the turn 'on' or turn 'off speed of the liquid crystal material, said V having a value in excess of the 'off' to 'on' threshold voltage for the liquid crystal material, said voltage sequence when integrated with respect to time approximately to V/og2 r.m.s., and for seletively addressed segments withholding either the + V, - V values or the OV value, depending on whether an addressed segment is to be in an 'on' state or an 'off' state, said withholding having a duration at least equal to the switching time of the liquid crystal material.

2. A method according to claim 1 wherein the liquid crystal material is a dyed characteristic phase change material.

3. A method for selectively addressing a liquid crystal display in matrix form substantially as described with reference to the accompanying drawings.

4. An apparatus for selectively addressing a liquid crystal display in matric form comprising means for generating a random or pseudorandom sequence of binary logic levels at a rate substantially in excess of the turn 'on' or turn 'off' speed of the liquid crystal material, means for accessing the matrix segments (elements) of the display in accordance with said logic level sequence, means for applying to each of the accessed segments a random or pseudo-random sequence of three voltage levels being respectively + V, - V or OV where V has a value in excess of the 'off' to 'on' threshold voltage of the liquid crystal material, said voltage sequence when integrated with respect to time approximating to V/ç2 r.m.s., and means for modifying the logic level sequence whereby for a selectively addressed segment the applied voltage is either + V or OV for a period of time at least equal to the switching time of the liquid crystal material depending on whether the addressed segment is to be in an 'on' state or an 'off' state.

5. Apparatus according to claim 4 wherein the liquid crystal material is a dyed cholesteric-nematic phase change material.

6. Apparatus for selectively addressing a liquid crystal display in matrix form substantially as described with reference to the accompanying drawings.