GB2064173A - A Method and Apparatus for Controlling the State of a Device - Google Patents
A Method and Apparatus for Controlling the State of a Device Download PDFInfo
- Publication number
- GB2064173A GB2064173A GB8036180A GB8036180A GB2064173A GB 2064173 A GB2064173 A GB 2064173A GB 8036180 A GB8036180 A GB 8036180A GB 8036180 A GB8036180 A GB 8036180A GB 2064173 A GB2064173 A GB 2064173A
- Authority
- GB
- United Kingdom
- Prior art keywords
- signal
- circuit
- capacitor
- state
- integrator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 12
- 239000003990 capacitor Substances 0.000 claims abstract description 24
- 238000012546 transfer Methods 0.000 claims description 11
- 238000005316 response function Methods 0.000 claims description 9
- 230000000694 effects Effects 0.000 claims description 3
- 238000012544 monitoring process Methods 0.000 claims description 3
- 230000008859 change Effects 0.000 claims description 2
- 230000001131 transforming effect Effects 0.000 claims 1
- 238000007599 discharging Methods 0.000 abstract description 2
- 239000004020 conductor Substances 0.000 description 19
- 238000010586 diagram Methods 0.000 description 7
- 238000012545 processing Methods 0.000 description 4
- 230000009471 action Effects 0.000 description 2
- 238000007620 mathematical function Methods 0.000 description 2
- 238000012937 correction Methods 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B5/00—Anti-hunting arrangements
- G05B5/01—Anti-hunting arrangements electric
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B11/00—Automatic controllers
- G05B11/01—Automatic controllers electric
- G05B11/36—Automatic controllers electric with provision for obtaining particular characteristics, e.g. proportional, integral, differential
- G05B11/42—Automatic controllers electric with provision for obtaining particular characteristics, e.g. proportional, integral, differential for obtaining a characteristic which is both proportional and time-dependent, e.g. P. I., P. I. D.
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Feedback Control In General (AREA)
Abstract
A control circuit comprises a comparator 1, receiving a reference signal Ve and a state signal Ve from a controlled device 3, and deriving an error signal E which is processed in a circuit 2 to provide a command signal Vs. The circuit 3 includes an integrator (5) having a capacitor (5b). A discharge circuit for discharging the capacitor (5b) when a predetermined condition exists comprises a discharge signal generator (-V; 15, 17; or 22) connected to the summation point (5a) in the integrator through at least one switch (8; 16, 18; or 23). The closure of the switches (8; 16, 18 and 23) is controlled by a command circuit (9-14; 15, 20) for receiving the error signal. <IMAGE>
Description
SPECIFICATION
A Method and Apparatus for Changing the
Response Function of an Integrator
The present invention relates to a method and apparatus for changing the response function of an integrator.
An integrator provides an output y=AJxdt in response to an input x, A being a negative constant number. The response function of the integrator is changed so that y=f(x) where f(x) is any mathematical function whatsoever.
According to the invention there is provided a method for controlling the state of a device, the method comprising the steps of producing a first signal proportional an error signal which is the difference between a command signal Uc representing the desired state of the device, and a state signal U6 representing the actual state of the device, producing a second signal proportional to the integral of the error signal, generating a control signal Us for controlling the state of the device by summing the first and second signals, monitoring the error signal, the differential with respect to time
dE
dt of the error signal, and the command signal Us, and modifying the integral of the error signal in such a sense to prevent the state signal Ue exceeding a maximum value USM, whenever the following conditions exist:
ds < O; < w; dt and
dE
C < U.-P, dt wherein w, C and s are positive constants, whereby to change the transfer function of the control from an integral form to a differential form.
According to the invention there is further provided a control circuit for controlling the state of a device, the control circuit comprising an
amplifier for receiving an error signal E=U,--U,, wherein Uc is a command signal representing a desired state for the device and Ue a state signal representing the actual state of the device, the amplifier being arranged to produce a first signal proportional to the error signal, an integrator including a capacitor, and being arranged to receive said error signal E, to provide a second signal proportional to the integral of the error signal, a summing circuit connected to receive the first and second signals to provide a command signal Us, and a discharge circuit for the capacitor of the integrator the discharge circuit comprising a potential supply terminal, a switch connected between this terminal and the capacitor, a differentiating circuit for receiving the error signal
E to provide a third signal proportional to the differential of the error signal when the differential error signal is of one polarity first comparator means for producing a first command signal when the error E is less than a predetermined value of the other polarity, and second comparator means for producing a second command signal when the third signal is less than the difference between the command signal Us and a predetermined value of said other polarity, the said first and second comparator means being arranged to effect closure of the said switch only while the said first command signal and the second command signal are in existence at the same time.
According to the invention, there is still further provided apparatus for changing the response function of an integrator having a capacitor, the apparatus comprising an input terminal for feeding an input signal x to the integrator, an output terminal for receiving an output signal y from the integrator, means connected to monitor at least one of the input and output terminals and operative only while a predetermined condition exists to feed a control signal to the capacitor to vary the output of the integrator.
Signal processing circuits and methods, embodying the invention, will now be described, by way of example, with reference to the accompanying diagrammatic drawings, in which:
Figure 1 is a block diagram of a control circuit embodying the invention;
Figure 2 is a graph of the state signal U6 as a function of time, responding to a slow increase
AU in the command signal U;
Figure 3 is a diagram of a state signal Ue as a function of time responding to a rapid increase AU of the command signal U;
Figure 4 is a circuit diagram of the block diagram of Figure 1; and
Figure 5 is a block diagram of processing circuit having two possible response functions.
The control circuit shown in Figure 1 comprises a comparator 1 receiving, on the one hand, a reference of command signal Uc, and on the other hand, a state signal U,, the comparator supplied at its output 1 a an error signal E having an amplitude equal to UcUe. The error signal E is processed by the circuit 2 which provides at its output 2a a command signal Us. The command signal is applied to the command input 3a of a member or device 3 to be controlled which delivers in its turn to an output 3b the state signal Ue representing a parameter indicative of the state of the member 3.
The processing circuit 2 is a linear circuit or network and includes an inverting amplifier 4 having a constant gain, an integrator 5, and an inverting summing circuit 6. The amplifier and integrator 4 and 5 receive at their input the signal
E whilst the circuit 6 adds the output signals from the circuits 4 and 5 together, inverts the sum and feeds the resulting output signal to a conductor 6a connected to the command terminal 3a, of the
member 3.
Such a control circuit, having a linear characteristic by using an integrator with a
proportional gain, may, in certain situations, give rise to substantial differences between the values of the state signal (U6) and the command signal (Uc). In a case where the value U6 must not be allowed to exceed a permissible maximum value USM, a transfer function circuit is connected
between the terminal 1 a and the conductor 6a to
avoid the value Ue, exceeding the maximum
permissible value U6M. This additional circuit has a
non-linear characteristic, and will not modify the transfer function of the control circuit except
under certain conditions.
The transfer function circuit of Figure 1 has three independent circuit parts; a first circuit part
A, which when it is connected, confers to the
circuit 2 an overall transfer circuit function of the
differential type adding to the proportion gain of the circuit 4; a second circuit part B, which, when
it is connected, confers on the circuit 2 an overall
transfer function of proportional type, and a third
circuit part C, which when it is connected, adds to the transfer function of the circuit 2 a term of
integral type.
The first circuit part is connected when the following conditions exist;
dE < 0; E < w; dt
dE C < U.-P dt where w and C are positive constants, and P is a positive constant equal to the maximum value U SM which can take the absolute value of Us.
The second circuit part is connected when the following conditions exist:
dE E < O; < Q dt
The third circuit part C is connected under the following condition:
E < O
The first circuit part A comprises a terminal providing a negative potential --V connected through a conductor 200 and a switch 8, to the summation point 5a of the integrator 5. The switch 8 is controlled by the output signal of a
comparator circuit 9 which compares the value U8-P with a value C C
dt supplied by a differentiating circuit 10 connected to receive the signal E.The value U8-P is supplied by a summing circuit 11 having one input connected to the conductor 6a and the other input is connected to a terminal providing a constant negative potential -P. Between the differentiating circuit 10 and the comparator 9 is the series combination of a switch 12 and a diode 13. The switch 12 is controlled by the output signal of a comparator 14 which compares the signal E with a constant negative potential w. The cathode of the diode 13 is connected to the output of the differentiating circuit 10.
The second circuit part B comprises a differentiating circuit 1 5 connected to receive the signal E. The output 1 5a of the differentiating circuit 1 5 is connected to the summation point 5a of the integrator through the series combination of a diode 16, an amplifier having constant gain 1 7, and a switch 18. The cathode of the diode 16 is connected to the output of the circuit 1 5, the switch 18 is controlled by the output signal from a comparator 20 which compares the signal E with zero value which is provided by an earth potential terminal 21.
The third circuit part C comprises a constant gain amplifier 22 having an input 22a connected to receive the signal E. The output of the amplifier 22 is connected to the summing point 5a of the integrator 5 through a switch 23 which is controlled by the output signal of the comparator 20.
The operation of the control circuit of Figure 1 will now be described whilst also referring to
Figure 2 and 3. These Figures 2 and 3 show the variation of U6 as a function to time starting at the instant to where the signal Uc commences to grow from the value UO up to an upper value Ul.
Figure 2 shows the case where the passage U6 from UO to U, is relatively show and Figure 3 shows the other case, where this passage is fast.
The curve (C) of U6 as a function of time comprises three sections. The section Cl during which the conditions E > 0 and
d - < O.
dt exist; the section C2 during which the conditions
E < O and dE
< 0 dt exist; and the section C3 during which the conditions E < 0 and
dE > 0 dt exist.
During the period of section C, of the curve (C), the comparator 20 applies to the command terminal of the switches 18 and 23 an opening signal, such that the parts B and C are disconnected. The comparator 14 applies an opening signal to the command terminal of the switch 12 when E > w in order to disconnect the circuit part A.
As soon as E < w that is to say starting from a point A on the curve (C), the comparator 14 applies a closure signal to the switch 12. When the switch 12 is thereupon closed the signal
dE
dt is supplied by the differentiating circuit 10 to the diode. Because this circuit signal is negative, the diode 1 3 is rendered conductive. The comparator 9 responds to the output of the diode 1 3 and the circuit 11 to apply to the command terminal switch 8 a closure signal when the condition
dE C < US-P; dt obtains.
Thus, each time the latter condition is satisfied, a negative signal --V of amplitude at least equal to that of the maximum value of the absolute value () is applied at the point 5a. This signal discharges the capacitor Sb of the integrating circuit 5; the capacitor Sb having been previously charged by the signal E. The effect of any integral gain of the integrator 5 is thus suppressed and the value Us is diminished to equal
dE
P+C
dt
The function of overall transfer of the circuit 2, except the circuit 4, is likewise of the differential type.
When one is working on the part C2 of the curve (C), the action of the part A continues so long as the.condition
dE
C < U5-P dt is satisfied. It will be noted that in Figure 2, the slope P1 of the curve C, at the point A is too small, (since P1 U5-P) for the circuit part A to be connected in contrast, in Figure 3, the slope P2 of the curve C, at the point A is sufficiently great (since P2 > U5-P) for the circuit part A to be connected in order to anticipate the correction of the curve (C) to avoid Ue exceeding the value UeM.
Figures 2 and 3 show in broken lines the curve sections (C'2, C'3), (C"2, C'3) which the curve (C) would have followed had the parts A, B and C not been brought into play.
Over the section C2 the comparator 20 applies to the switches 18 and 23 a closure signal thus
connecting the parts B and C. The signal
dE
C'
dt supplied by the differentiating circuit 15 to the diode U is negative, and so the diode 1 6 is rendered conductive. This signal is then amplified by the amplifier 17, and applied to the point 5a, through the closed switch 1 8. The integrator (5) thereupon integrates this amplified signal
dE
K
dt and feeds the result K'E to the conductor 6a.K' has a negative sign and so acts to reduce the value of Us. The circuit part B actually confers on the control circuit 2 an overall transfer function of the proportional type, provided however that over the said section C2, the coefficient K is selected to be sufficiently large for the signal K' to remain iarge in relation to the signal K,SE dt; assuming treatment by the circuit 5 and 6 of the signal received directly by the circuit 5.
Over the section C2 of the curve (C) the condition dE
> 0, dt exists and so the diodes 13 and 1 6 are blocked,
to disconnect the circuit parts A and B.
The circuit part C remains connected when working over the sections C2 and C3 of the curve
C. The amplifier 22 in practice applies a signal K2E to the point 5a, through the closed switch 23, which after processing by the integrator 5, becomes a signal K3JE dt at the conductor 6a. K2 is selected to be sufficiently small so that amplitude of the signal (E dt remains small in relation to that of the signal K' because of the action of the circuit part B over the major section
C2. The signal K3 dt due to the circuit part C is thus reduced to the value of Us.
Thus the different non-linear networks or circuit parts A, B, C, connect and disconnect themselves from the circuit 2 as a function of the value of Us, E and
dE
dt
The non-linear networks or circuit parts when they are connected, always cause a reduction in the command signal Us, without causing a discontinuity in Us and dU5 dt
These circuit parts A, B, C, disconnect themselves without causing a variation in Us and so leave the switch 5 of the circuit 2 with an initial condition favourable to respond to a variation AU in the signal Uc, without exceeding the maximum value USM forte.
Figure 4 is a circuit diagram of the block diagram of Figure 1. In Figure 4 the inverting differentiator 1 60 corresponds to the differentiating circuit 10 of Figure 1.
The summing circuit 11 of Figure 1 is formed by a junction point 1 62. The junction point 1 62 is connected (a) to a conductor 1 63 connected to the conductor 6a through a resistor 25;
(b) to a conductor 1 70 connected to the output 1 60a of the circuit 1 60 through a diode 180 and a variable resistor 190; and
(c) to a tap 51 a of a voltage divider 51 connected between earth 21 the voltage source -V. The output signal from the point 1 62 is connected to the inverting input of an operational amplifier 49.
The switch 8 and the comparator 9 of Figure 1 are formed by the operational amplifier 49 and a diode 53; the anode of the diode being connected to the output of the amplifier 49 by a conductor 52 and the cathode of the diode 53, being connected to the point 5a by a conductor 41.
The diode 180 corresponds to the diode 13 of
Figure 1. The switch 12 and the comparator 14 of
Figure 1 correspond in Figure 4 to an operational amplifier 43 having its inverted input connected on the one hand through a resistor 44 to the terminal 1 a and, on the other hand, through a resistor 45, to the tap 46a on a voltage divider 46 connected between earth 21 and the voltage source -V.
The differentiating circuit of Figure 1 corresponds to an inverting differentiating circuit 26 of Figure 4.
The diode 1 6 of Figure 6 corresponds to a diode 28 of Figure 4. The diode 28 is connected with the aid of a conductor 27 between the output of the differentiating circuit 26 and the input of an inverting amplifier 30 having a constant but controllable gain 30. The amplifier 30 corresponds to the amplifier 1 7 of Figure 1.
The switch 18 and the comparator 30 of Figure 1 correspond to an operational amplifier 100 of
Figure 4. The inverting input of the amplifier 100 is connected to receive the signal E and the output is connected to the summation point 30a of the amplifier 30, through a diode 101; the anode of the diode 101 being connected to the circuit 100.
The switch 18 and the comparator 20 of Figure 1 are formed in Figure 4 by a diode 57 interposed in a conductor 27 connecting the output of the amplifier 30, to the point 5a; the anode of the diode 27 being connected to the circuit 30.
The amplifier 22 of Figure 1 corresponds to an inverting amplifier 102 in Figure 4. The output of the amplifier 102 is connected to the point 30a by a conductor 55 through a variable resistor 56.
The switch 23 of Figure 1 corresponds to the members 100, 101, 30 57 of Figure 4 hereinbefore described. The circuit of Figure 4 includes trigger circuits (not shown in Figure 1) for discharging the capacitor Sb of the circuit 5 when the amplitude of Us reaches the maximum permissible value USM=P. A first trigger circuit applies to the point 5a the voltage --V when Us reaches the value +USM.This first circuit comprises an operational amplifier 38 having its inverted input connected, on the one hand, through a resistor 90, to the conductor 6a and, on the other hand, through a resistor 39, to the tap 40a of a voltage divider 40 connected between earth 21 and the constant negative potential source -V. A diode 42 is interposed in a conductor 41 connecting the output of circuit 38 to the point 5a; the cathode of the diode 42 being connected to the circuit 38.
A second trigger circuit applies to the point 5a a voltage +V when Us reaches the value -U SM=+P. This second circuit comprises an operational amplifier 33 having an inverting input connected, on the one hand, through a resistor 80 to a conductor 6a and, on the other hand, through a resistor 34, to the tap 35a of a voltage divider 35 connected between the earth 21 and a constant positive potential source +V. A diode 37 is interposed in a conductor 36 connecting the output of the circuit to the point 5a; the cathode of the diode being connected to the point 5a.
The present invention is not limited to control circuits, but can be embodied in any circuit having at least two operational response functions such as the circuit shown in Figure 5, and in which parts similar to those of Figure 1 are similarly referenced. Figure 5 shows a calculating circuit 201 receiving an input signal x and providing an output signal y. A closure signal is applied to the command terminal of the switch 8 interposed in a conductor 200 extending between the point 5a and the source -V, each time that the output signal has the same sign as the voltage (-V) and exceeds an absolute value of y=f(x); f(x) being any mathematical function whatsoever.
Claims (16)
1. A method for controlling the state of a device, the method comprising the steps of producing a first signal proportional to an error signal E which is the difference between a command signal Uc representing the desired state of the device and a state signal U6 representing the actual state of the device, producing a second signal proportional to the integral of the error signal, generating a control signal Us for controlling the state of the device by summing the first and second signals, monitoring the error signal E, the differential with respect to time dE dt of the error signal, and the command signal Us, and modifying the integral of the error signal in such a sense to prevent the state signal U8 exceeding a maximum value UOM, whenever the following conditions exist:
d
< 0; E < w; dt and
dE C < U8-P; dt wherein w, C and P are positive constants, whereby to change the transfer function of the control from an integral form to a differential form.
2. A method according to claim 1, including the step of producing a signal proportional to the differential
dE
dt whilst the conditions E < O and
dE < 0 dt exist and transforming the transfer function of the control from an integral form into a proportional form.
3. A method according to claim 1 or to claim 2, including the step of modifying the second signal with a signal proportional to the error signal E whenever E < 0.
4. A method according to any one of claims 1 to 3, including the step of limiting the value of the command signal between two extreme values of opposite polarity.
5. A control circuit for controlling the state of a device, the control circuit comprising an amplifier for receiving an error signal E=UcU6, wherein Uc is a command signal representing a desired state for the device and Ue a state signal representing the actual state of the device, the amplifier being arranged to produce a first signal proportional to the error signal, an integrator including a capacitor, and being arranged to receive said error signal E, to provide a second signal, a summing circuit connected to receive the first and second signals to provide a command signal Us, and a discharge circuit for the capacitor of the integrator, the discharge circuit comprising a potential supply terminal, a switch connected between this terminal and the capacitor, a differentiating circuit for receiving the error signal to provide a third signal proportional to the differential of the error signal when the differentiated error signal is of one polarity, first comparator means for producing a first command signal when the error E is less than a predetermined value of the other polarity, and second comparator means for producing a second command signal when the third signal is less than the difference between the command signal Us and a predetermined value of said other polarity, the said first and second comparator means being arranged to effect closure of the said switch only while the first command signal and the second command signal are in existence at the same time.
6. A circuit according to claim 5, wherein the discharge circuit includes a second switch connected between the capacitor and a circuit for supplying a fourth signal proportional to the differential of the error signal, and a control circuit arranged to close the second switch only while the error signal and its differential are both negative.
7. A circuit according to claim 5 or to claim 6, wherein the discharge circuit comprises a third switch connected between the capacitor and a circuit arranged to supply a fifth signal directly proportional to the error signal, and a command circuit operable to close the third switch when the error signal is of the opposite polarity.
8. Apparatus for changing the response function of an integrator having a capacitor, the apparatus comprising an input terminal for feeding an input signal x to the integrator, an output terminal for receiving an output signal y from the integrator, means connected to monitor at least one of the input and output terminals and operative only while a predetermined condition exists to feed a control signal to the capacitor to vary the output of the integrator.
9. Apparatus according to claim 8, wherein the predetermined condition exists while the output signal y exceeds a predetermined level and the control signal fed to the capacitor comprises a signal of such polarity as to discharge the capacitor.
10. Apparatus according to claim 8, wherein the predetermined condition exists only while both the output signal y exceeds a predetermined level and the differential of the signal x is of one polarity and less than a predetermined value and the signal fed to the capacitor comprises a signal of such polarity as to discharge the capacitor.
11. Apparatus according to any one of claims 8 to 10 wherein the predetermined condition exists while the differential of the input signal x and the input signal x are both of the same predetermined polarity and wherein the control signal comprises the differential of the input signal.
12. Apparatus according to any one of claims 8 to 11, wherein the predetermined condition exists while the output signal exceeds a predetermined reference level and the control signal comprises the signal y.
13. Apparatus according to claim 8, wherein the monitoring means is operative to produce a predetermined function f(x) from the input signal (x) and is operative to compare the value of the function f(x) with the value y and to discharge the capacitor when a predetermined relationship between f(x) and (y) is achieved.
14. Apparatus for changing the response function of an integrator having capacitor substantially as hereinbefore described with reference to Figures 1 to 4 of the accompanying drawings.
15. Apparatus for changing the response function of an integrator having capacitor substantially as hereinbefore described with reference to Figure 5 of the accompanying drawings.
16. A method for controlling the state of a device substantially as hereinbefore described with reference to Figures 1 to 4 of the accompanying drawings.
1 7. A control circuit for controlling the state of a device substantially as hereinbefore described with reference to Figures 1 to 4 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR7927875A FR2469830B1 (en) | 1979-11-13 | 1979-11-13 | METHOD FOR CHANGING THE RESPONSE FUNCTION OF AN INTEGRATER, CIRCUIT FOR CARRYING OUT SAID METHOD, AND CONTROL SYSTEM AND CIRCUIT USING THE ABOVE-MENTIONED METHOD AND CIRCUIT |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2064173A true GB2064173A (en) | 1981-06-10 |
| GB2064173B GB2064173B (en) | 1984-02-29 |
Family
ID=9231576
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8036180A Expired GB2064173B (en) | 1979-11-13 | 1980-11-11 | Method and apparatus for controlling the state of a device |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS5682903A (en) |
| FR (1) | FR2469830B1 (en) |
| GB (1) | GB2064173B (en) |
| IN (1) | IN155009B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0098909A2 (en) * | 1982-07-14 | 1984-01-25 | VDO Adolf Schindling AG | Idling speed controller, in particular for vehicles |
-
1979
- 1979-11-13 FR FR7927875A patent/FR2469830B1/en not_active Expired
-
1980
- 1980-11-04 IN IN792/DEL/80A patent/IN155009B/en unknown
- 1980-11-11 GB GB8036180A patent/GB2064173B/en not_active Expired
- 1980-11-13 JP JP15891580A patent/JPS5682903A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0098909A2 (en) * | 1982-07-14 | 1984-01-25 | VDO Adolf Schindling AG | Idling speed controller, in particular for vehicles |
| EP0098909A3 (en) * | 1982-07-14 | 1984-07-25 | Vdo Adolf Schindling Ag | Idling speed controller, in particular for vehicles |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2064173B (en) | 1984-02-29 |
| JPS5682903A (en) | 1981-07-07 |
| FR2469830B1 (en) | 1985-09-27 |
| IN155009B (en) | 1984-12-22 |
| FR2469830A1 (en) | 1981-05-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19991111 |