GB2063561A - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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Publication number
GB2063561A
GB2063561A GB8033736A GB8033736A GB2063561A GB 2063561 A GB2063561 A GB 2063561A GB 8033736 A GB8033736 A GB 8033736A GB 8033736 A GB8033736 A GB 8033736A GB 2063561 A GB2063561 A GB 2063561A
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Prior art keywords
region
impurity
regions
insulation
semiconductor device
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GB8033736A
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GB2063561B (en
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Toshiba Corp
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Tokyo Shibaura Electric Co Ltd
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Publication of GB2063561A publication Critical patent/GB2063561A/en
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Publication of GB2063561B publication Critical patent/GB2063561B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

In a junction gate FET at least one insulating region 25a, 25b is formed at the interface between the source or drain region 22, 23 and the channel region 24. The gate region 26 is produced so that it abuts the insulating region(s) 25a, 25b so that the gate junction does not exhibit a curved edge profile with the associated electric field concentration. This structure increases the high voltage resistance of the FET while enabling the use of a shallow gate region which facilitates the simultaneous formation of bipolar transistors. <IMAGE>

Description

SPECIFICATION r Semiconductor device and manufacturing method therefor The present invention relates to a semiconductor device, especially a field effect transistor, and a manufacturing method for the same.
With a conventional junction type field effect transistor (J-FET), high voltage resistance is achieved with the construction shown in Fig. 1, for example. A p-type source region 12 and a p-type drain region 13 both of high concentration are formed in.an n-type silicon substrate 11. A p-type channel region 14 of low concentration is formed between the source region 12 and the drain region 13, and an n-type gate region 15 of high concentration is formed in the channel region 14.
Thus, the n-type gate region 15 functions to prevent direct contact between the p-type source region 12 and the p-type drain region 13, so that the voltage resistance at the pn junction is determined by the concentration in the p-type channel region 14.
However, with the transistor of such a construction, the factor which determines the voltage resistance includes, in addition to the concentration of the channel region 14, the shape (curvature) of the gate region 15. When the junction depth of the gate region 15 is shallow, the radius of curvature becomes smaller so that the electric field is concentrated at this part. Thus, the voltage resistance is determined more by the curvature than by the concentration of the channel region 14, resulting in degradation of the voltage resistance. For achieving high voltage resistance with such a conventional structure, it is necessary to form both the channel region 14 and the gate region 15 to be deep for enlarging the radius of curvature, and to widen the distances between the gate region 15, the source region 12, and the drain region 13.
For manufacturing such a transistor, it is necessary to perform high temperature diffusion for a long period of time, so simultaneous formation with other bipolar integrated circuits becomes impossible. Further, the elements cannot be made smaller since wide distances must be maintained between the gate region 15, the source region 12, and the drain region 13.
The present invention has been made to overcome these problems and has for its object to provide a semiconductor device and a manufacturing method therefor according to which the voltage resistance may be made higher, the elements may be made smaller, and simultaneous formation of general bipolar integrated circuits may be possible.
According to one aspect of the present invention, there is provided a semiconductor device including: a , semiconductor substrate of one conductivity type; first and second impurity regions of opposite conductivity type to that of said substrate, which are formed in the surface of said substrate to be opposed and separate from each other; a third impurity region of the same conductivity type as that of said first and second impurity regions, which is formed between said first and second impurity regions and have an impurity concentration lower than that of said first and second impurity regions; at least one insulation region formed shallower than said third impurity region along the interfaces between said first impurity region or second impurity region and said third impurity region; and a fourth impurity region of opposite conductivity type to that of said third impurity region, which is formed between said insulation regions when two said insulation regions are formed, and between said insulation region and one of said first and second impurity regions when one said insulation region is formed.
In this semiconductor device, said first and second impurity regions may constitute the source and drain regions of the field effect transistor, and said fourth impurity region may constitute the gate region of the field effect transistor.
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device including the steps of: forming first and second impurity regions of opposite conductivity type to one conductivity type of a semiconductor substrate in the surface of said substrate to be opposed and separate from each other; forming a third impurity region of the same conductivity type as that of said first and second impurity regions between said first and second impurity regions, said third impurity region having an impurity concentration lower than that of said first and second impurity regions; forming at least one insulation region shallower than said third impurity region along the interfaces of said first impurity region or second impurity region and said third impurity region; and forming a fourth impurity region of opposite conductivity type to that of said third impurity region in said third impurity region to be shallower than said insulation region.
This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figure 1 is a sectional view of a conventional semiconductor device; Figure 2 is a sectional view of a semiconductor device in accordance with one embodiment of the present invention; Figures 3(A) through 3(C) are sectional views illustrating the manufacturing method of the device shown in Fig. 2; Figure 4 is a sectional view of an integrated circuit including the device shown in Fig. 2 and a bipolar transistor; and Figure 5 is a sectional view of a semiconductor device in accordance with another embodiment of the present invention.
One embodiment of the present invention will be described with reference to the accompanying drawings. in Fig. 2, numeral 21 denotes an n-type silicon substrate, and a ptype source region 22 and a p-type drain region 23 of high concentration are formed on the major surface of the substrate 21. A ptype channel region 24 of low concentration and of the same conductivity type as that of the source region 22 and the drain region 23 is formed between the source region 22 and the drain region 23. Insulation regions 25a and 25b of SiO2 (silicon oxide films) are formed at the interfaces of the channel region 24 with the source region 22 and the drain region 23.An n-type gate region 26 of high concentration is formed at a position surrounded by the insulation regions 25a and 25b and the channel region 24 in such a manner as to secure junctions with the insulation regions 25a and 25b and the channel region 24. The junction of the gate region 26 with the channel region 24, that is, a pn junction, is a planar junction. Thus, the electric field is not concentrated at the pn junction so that the voltage resistance is not degraded.
It is, therefore, not necessary to make the channel region 24 and the gate region 26 deep or to widen the distances between the gate region 26, the source region 22 and the drain region 23 so that the elements may be made smaller.
A method for manufacturing a semiconductor device as described above will be described. A p-type impurity such as boron (B) is introduced at high concentration by the known ion implantation method to one major surface of the n-type silicon substrate 21 to form the source region 22 and the drain region 23 as shown in Fig. 3(A). A p-type impurity such as boron (B) is introduced at low concentration by the ion implantation method between the source region 22 and the drain region 23 to form the channel region 24.The junction depth of the channel region 24, the source region 22 and the drain region 23 is sufficient to be equivalent to the base depth of a general bipolar element (2.5-3.0 jim). An SiO2 film 27 is formed on the surface of the substrate 21 by the CVD (chemical vapor deposition) method, and an antioxidant film such as an Si3N4 (silicon nitride) film 28 is formed on the SiO2 film 27.The parts of the Si3N4 film 28 corresponding to the interfaces of the channel region 24 with the source region 22 and the drain region 23 are selectively exposed as shown in Fig. 3z Thereafter, using the Si3N4 as a mask, these parts of the interfaces are oxidized in an oxidizing atmosphere under pressure to form the insulation regions 25a and 25b. The conditions for the oxidation under pressure may be such that hydrogen is burned at 1,000 C at 9 atmospheres to form the insulation regions 25a and 25b of 1.5 #m thicliness in about 60 minutes.Since the junction depth, the layer resistance and so on irbf the already formed channel region 24, the source region 22 and the drain region 23 do not change during the oxidation under pressure, the punch-through voltage (Vp) of the field effect transistor may be set to a predeter mined value with excellent reproducibility.
When the method is used with a general npn transistor, the element characteristics such as current amplification factor (hfe) do not fluctuate and can be controlled to be excellent.
Then, the Si3N4 film 28 is removed as shown in Fig. 3(C), and the part of the SiO2 film 27 between the insulation regions 25a and 25b is exposed and an n-type impurity such as phosphorus (P) is diffused at high concentration through the exposed part to form the gate region 26. A PSG (phosphosilicate glass) film 29 is coated thereover by the CVD method to protect the surface.
With such a construction, a junction type field effect transistor with high voltage resistance and smaller elements is possible, and simultaneous formation with general bipolar integrated circuits becomes feasible. As shown in Fig. 4, a general bipolar npn transistor 33, for example, is formed with the junction type field effect transistor on a p-type silicon substrate 31 through an insulation isolating band 32. Then, it is possible to perform the diffusion of the n-type impurity of the gate region 26 of the junction type field effect transistor simultaneously with the diffusion of the n-type impurity of an emitter region 34 of the npn transistor 33. The junction depth of the gate region 26 must not exceed the depth of the insulation regions 25a and 25b.
Although the insulation regions 25a and 25b are formed prior to the formation of the gate region 26 in the above embodiment, this may alternatively be done after forming all of the elements.
Fig. 5 shows a field effect transistor in accordance with another embodiment of the present invention. In Fig. 5, the same parts are designated by the same reference numerals as in Fig. 2. The field effect transistor of Fig. 5 thus corresponds to that shown in Fig.
2, except the insulation region 25b is removed.
The voltage resistance is improved in the case of the FET in Fig. 5 to the same degree as that in Fig. 2. Furthermore, the case of Fig.
5 is more advantageous for smaller transistors in that the dimensions of the FET may be reduced by the space required for the region 25b since the insulation region 25b is not included.

Claims (7)

1. A semiconductor device comprising: a semiconductor substrate of one conductivity type; first and second impurity regions of opposite conductivity type to that of said substrate, which are formed in the surface of said substrate to be opposed and separate from each other; a a third impurity region of the same conductivity type as that of said first and second impurity regions, said third impurity region being formed between said first and second impurity regions and having an impurity concentration lower than that of said first and second impurity regions; at least one insulation region formed shallower than said third impurity region along the interfaces between said first impurity region or second impurity region and said third impurity region; and a fourth impurity region of opposite conductivity type to that of said third impurity region, which is formed between said insulation regions when two said insulation regions are formed, and between said insulation region and one of said first and second impurity regions when one said insulation region is formed.
2. A semiconductor device as claimed in claim 1 wherein said first and second impurity regions comprise the source region and the drain region of a field effect transistor and said fourth impurity region comprises the gate region of the field effect transistor.
3. A method for manufacturing a semiconductor device comprising the steps of: forming first and second impurity regions of opposite conductivity type to one conductivity type of a semiconductor substrate in the surface of said substrate to be opposed and separate from each other; forming a third impurity region of the same conductivity type as that of said first and second impurity regions between said first and second impurity regions, said third impurity region having an impurity concentration lower than that of said first and second impurity regions; forming at least one insulation region shallower than said third impurity region along the interfaces of said first impurity region or second impurity region and said third impurity region; and forming a fourth impurity region of opposite conductivity type to that of said third impurity region in said third impurity region to be shallower than said insulation region.
4. A method as claimed in claim 3 wherein said first and second impurity regions comprise the source region and the drain region of a field effect transistor and said fourth impurity region comprises the gate region of the field effect transistor.
5. A semiconductor device as claimed in claim 2 wherein one insulation region is formed between the source region and the gate region.
6. A semiconductor device, substantially as hereinbefore described with reference to the accompanying drawings.
7. A method for manufacturing a semiconductor device, substantially as hereinbefore described with reference to the accompanying drawings.
GB8033736A 1979-10-18 1980-10-20 Semiconductor device and manufacturing method therefor Expired GB2063561B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13439679A JPS5658259A (en) 1979-10-18 1979-10-18 Semiconductor device and production thereof

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GB2063561A true GB2063561A (en) 1981-06-03
GB2063561B GB2063561B (en) 1983-10-12

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2140616A (en) * 1980-03-03 1984-11-28 Raytheon Co Shallow channel field effect transistor
US4523368A (en) * 1980-03-03 1985-06-18 Raytheon Company Semiconductor devices and manufacturing methods
CN103972295A (en) * 2014-05-30 2014-08-06 电子科技大学 JFET (junction field-effect transistor) device and manufacturing method thereof
CN103972302A (en) * 2014-05-26 2014-08-06 电子科技大学 JFET (junction field-effect transistor) device and manufacturing method thereof

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1200725B (en) * 1985-08-28 1989-01-27 Sgs Microelettronica Spa INSULATION STRUCTURE IN MOS DEVICES AND ITS PREPARATION PROCEDURE
DE3620686C2 (en) * 1986-06-20 1999-07-22 Daimler Chrysler Ag Structured semiconductor body
JPH0234938A (en) * 1988-07-25 1990-02-05 Matsushita Electron Corp Semiconductor device
AU2009324423B8 (en) 2008-12-12 2014-04-10 Kids Ii, Inc Electromagnetic swing
CN204318176U (en) 2014-08-08 2015-05-13 儿童二代公司 For the control appliance of children's bouncer and baby support

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5729065B2 (en) * 1973-10-01 1982-06-21
JPS5364480A (en) * 1976-11-22 1978-06-08 Toshiba Corp Field effect semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2140616A (en) * 1980-03-03 1984-11-28 Raytheon Co Shallow channel field effect transistor
US4523368A (en) * 1980-03-03 1985-06-18 Raytheon Company Semiconductor devices and manufacturing methods
CN103972302A (en) * 2014-05-26 2014-08-06 电子科技大学 JFET (junction field-effect transistor) device and manufacturing method thereof
CN103972295A (en) * 2014-05-30 2014-08-06 电子科技大学 JFET (junction field-effect transistor) device and manufacturing method thereof

Also Published As

Publication number Publication date
DE3039009A1 (en) 1981-05-07
JPS5658259A (en) 1981-05-21
DE3039009C2 (en) 1985-12-19
GB2063561B (en) 1983-10-12

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746 Register noted 'licences of right' (sect. 46/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19951020