GB2059209A - Solid state switching system for coupling a d-c power supply to a load - Google Patents

Abstract

A d-c power supply is connected to a load via a power transistor triggered to its saturation condition by periodically recurring pulses having a time separation between successive pulses less than the transistor's storage time. Due to the storage time, the transistor (10) remains saturated in the absence of base drive current between pulses and maintains a continuous coupling of the d-c power supply to the load. With intermittent base current, substantial power is saved not only in the base drive circuit but also in the transistor itself. <IMAGE>

Description

SPECIFICATION Solid state switching system for coupling a d-c power supply to a load This invention relates to a solid state switching arrangement for controlling the delivery of d-c powerto a load. One well-known prior scheme is to connect the emitter-collector path of a power transistor in series with the load and the d-c power source.

When it is desired to turn the transistor on to apply the d-c power to the load, direct current is continuously supplied to the base-emitter junction to drive the transistor into its saturation mode and to hold it there. In effect, the transistorfunctions as a relay. Relatively small amplitude base current controls the flow of high magnitude collector or load current. This prior switching scheme, however, consumes a substantial amount of power and is very wasteful and inefficient.

The present invention constitutes a significant improvementoverthe prior switching arrangements for connecting d-c power supplies to load circuits since it not only is of simple and inexpensive construction, but also consumes considerably less power and is highly efficient.

The solid state switching system of the invention controls the application to a load of a d-c voltage developed by a d-c power supply. The system includes a power transistor having a base, an emitter and a collector and exhibiting a predetermined storage time. Means are provided for coupling the d-c power supply and load in series with the emitter-collector conduction path of the transistor. A pulse signal source produces periodically recurring pulses having a time separation between successive pulses less than the storage time of the transistor.

The switching system also includes means for applying the pulses between the base and the emitter to drive th z transistor into saturation thereby coupling the d-c power supply to the load to apply the d-c voltage thereto, the transistor remaining saturated between successive pulses to maintain continuous application of the d-e voltage to the load.

The features of the invention which are believed to be novel are set forth with particularity in the appended claim. The invention, together with further advantages and features thereof, may best be understood, however, by reference to the following description in conjunction with the accompanying drawing which illustrates a solid state switching system, constructed in accordance with the present invention, for applying a d-c voltage to a load.

Transistor 10is a conventional NPN powertransistor capable of handling very large load currents. D-C power supply 12 (schematically shown merely as a battery for simplicity) may constitute a d-c voltage source of either fixed or variable amplitude. For example, in one application of the invention d-c power supply 12 may be a potential source of around 300 volts. As another example, the invention may be incorporated in an inverter where four transistor switches, like transistor 10, are switched on and off in pairs and in a predetermined sequence to alternate the polarity of the d-c voltage applied to a load, thereby effectively delivering single-phase a-c power to the load.In that inverter environment, the magnitude of the d-e voltage provided by the d-c powersupply 12 may be adjustable in ordertovary the amplitude of the a-c voltage produced by the inverter.

Depending on the application of the invention, load 14 may take any of a variety of different forms and may include resistances, inductanes, and/or capacitances. For example, when transistor 10, and three other similar transistors, function as the switches in an inverter, the output of that inverter may be coupled to a single-phase a-c induction motor to control the rotation thereof. In that case, load 14 would be inductive.

Load 14 and d-c supply 12 are connected in series with the collector 16 and emitter 17 of transistor 10.

Since the transistor is normally non-conductive, it serves as a normally-open switch to maintain supply 12 and load 14 disconnected. The switch is closed, to apply the d-e voltage from source 12to load 14, by delivering to base 18 current of a magnitudesuffi- cient to drive the transistor into saturation, at which time a very low impedance will exist between collector 16 and emitter 17.

To control the operation of transistor 10, controlled pulse signal source 20 produces periodically recurring, positive-going pulses at a relatively high pulse repetition frequency. Preferably, the frequency will be at least 100 kilohertz. The amplitude of each of the positive-going pulses will be high enough to switch the transistor to its saturation mode. Hence, whenever it is desired to connect load 14 to d-c supply 12, pulse signal source 20 may be appropriately controlled so a series or train of periodically recurring pulses will be applied between base 18 and emitter 17 to drive the transistor into saturation and render it conductive. When the invention is in the environment of an inverter, pulse signal source 20 would be controlled by the customary logic circuits to turn the four transistors (like transistor 10) on and off at the correct times.

A salient feature of the invention resides in holding the transistor in its saturated condition during the application thereto of a series of spacedapart pulses, even though base current is removed between the occurrences of the pulses. This is accomplished by utilizing the charge storage characteristic of the transistor. When a transistor is driven to saturation by base drive current, minority carriers become stored in the base and collector regions and these carriers must be swept away, such as by recombination or absorption, after the termination of the base current before the transistor switches out of its saturation mode and turns off. This process of cleaning out the minority carriers requires a finite time interval which is referred to as the "storage time".While in many applications of transistors the storage time is a distinct disadvantage, that property is advantageously employed in the present invention. The specific duration of the storage time for any given transistor is determined by and dependent on several factors, such as the transistor type, the amplitude of the emitter-collector current or load current, the junction temperature and the external impedance coupled between the base and emitter.

Whateverthe storage time may be for the particu lar power transistor employed, pulse signal source 20 must be designed so that the pulses issuining therefrom will have a time separation (namely, the time interval from the trailing edge of one pulse to the leading edge of the next occurring pulse) less than that storage time. The pulses may take a variety of different waveshapes, frequencies and duty cycles and the switching system may still operate in accordance with the invention, as long as the time separation between the successive pulses applied to the base-emitter junction is less than the transistor's storage time. Under those conditions, the minority carriers will keep transistor 10 in its saturated mode between the occurrences of the pulses when the base current is absent.Hence, any time source 20 applies a series of pulses between base 18 and emitter 17, transistor 10 will remain saturated between successive pulses to maintain continuous application of the d-c voltage provided by d-c power supply 12, to load 14.

By employing intermittent base current to hold the transistor in its conductive state, major power savings are achieved in both the base drive circuit and in the transistor itself. When the base circuit is zero between pulses, the power consumed across the base-emitter junction will likewise be zero. In addition, without base current flowing through the junction the base-emitter voltage will be less than it otherwise would be with base current. As a result, the emitter-collectorvoltage drops during the time separations between pulses nd this reduces the power dissipated in the transistor through the emitter-collector conduction path. Furthermore, by employing a pulse train drive rather than a conttinuous drive, economies are realized in the construction of the drive circuit. For example, the size of the base drive power supply can be reduced since less power is dissipated through the base-emitterjunction.

While a particular embodiment of the invention has been shown and described, modifications, may be made, and it is intended in the appended claim to cover all such modification as may fall within the true spirit and scope of the invention.

Claims (2)

1. A solid state switching system for applying a d-c voltage, provided by a d-c power supply, to a load, comprising: a power transistor having a base, an emitter and a collector and exhibiting a predetermined storage time; means for coupling the d-c power supply and load in series with the emitter-collector conduction path of said transistor; a pulse signal source for producing periodically recurring pulses having a time separation between successive pulses less than the storage time of said transistor; and means for applying said pulses between said base and said emitter to drive said transistor into saturation thereby coupling the d-c power supply to the load to apply the d-c voltage thereto, said transistor remaining saturated between successive pulses to maintain continuous application of the d-c voltage to the load.

2. A solid state switching system constructed and arranged to operate substantially as hereinbefore described with reference to and as illustrated in the accompanying drawing. r