GB2042294A - Automatic gain control - Google Patents

Abstract

In a circuit for subjecting analogue input signals to one of a number of preselected degrees of amplification at 4, depending on the amplitude of said input signals prior to amplification, the amplified signals are applied to an analogue-to-digital converter device 3 and the digital signals together with information indicative of the degree of amplification which was applied to the corresponding analogue signals prior to conversion are fed out to output register 8. <IMAGE>

Description

SPECIFICATION Digital companding This invention relates to digital coding systems and in particular to the reduction of the noise level in such systems.

The advantages of digital over analogue recording especially when magnetic recording media are employed are well known. Since a digital signal does not involve partially magnetised states - it is essentially eitherfully "on" or fully "off" - most of the problems associated with analogue magnetic recording, namely those of non linearity, noise induced errors, drift effects and dynamic distortion are avoided.

However, particularly for high quality audio recording, as required in a Recording Studio, for example, it may still be necessary to significantly reduce the noise introduced during the recording of a signal, and to this end it is well known that instantaneous companding circuits may be used. Using three companding circuits for example, the dynamic range of a 12 bit pulse code modulation (PCM) system may typically be extended to have the equivalend noise level of a 15 bit system for a signal level 18dB below the peak coding level, although of course, the signal to noise ratio can never exceed that of the 12 bit PCM system itself at the peak coding level, i.e. 72dB.

Hitherto companding circuits such as these have usually required a high gain comparator for each range of inputs selected for expansion and so a neater, more compact arrangement is desirable particu marly for use in a multichannel system.

It is an object of the present invention to provide an improved digital companding arrangement.

According to the present invention there is provided a digital companding circuit comprising an amplification means arranged to subject analogue input signals applied thereto to one of a plurality of discrete preselected degrees of amplification in dependence on a control signal applied to said amplification means, an analogue-to-digital conversion circuit coupled to the output of said amplification means and a feedback circuit for responding to output signals provided by the conversion circuit to generate said control signal, in dependence upon the amplitude of said output signals, to control the degree of amplification to be applied to said input signals, the circuit including means for conveying to an output location thereof a digitally converted output signal in respect of a given analogue input signal that has been controllably amplified by said amplification means and also information indicative of the degree of amplification determined by the control signal and applied to said given input signal.

In orderthat the invention may be more fully understood specific embodiments thereof are described by way of example by reference to the accompanying drawings of which: Figure 1 illustrates a companding circuit suitable for converting an analogue signal to a digital signal, Figure 2 illustrates a circuit constituting the amplification control means used in the circuit of Figure land Figure 3 illustrates a companding circuit suitable for converting a digital signal back to an analogue signal.

In the description which follows a 12 bit PCM system is considered, although it will be appreciated that other systems may alternatively be used.

In one example of the present invention the four most significant bits from the output of a binary AID converter are used to determine in which of four ranges the amplitude of the analogue input signal lies.

In dependence on the amplitude range the input signal is then amplified by an appropriate, preset factor to generate a new input signal of an amplitude lying within the upper amplitude range of the converter. The new input signal is then fully converted to generate the companded digital output signal from the arrangement.

Using an offset binary code the four most significant bits are taken from the output of an A/D converter and passed to a true complement element, the MSB (BIT 1) being a parity bit which determines the sense of the other three bits.

If BIT 2 of the converter output is high (i.e. a binary "1 ") the input amplitude is at least half the converter peak coding value, Vp, and no amplification of the signal is necessary. If BIT3 is high and BIT2 is low, however, the input amplitude lies in the range SVp to iVp and so an amplification factor of 2 is required, and if BIT4 is high, BITS 2 and 3 being low, the input amplitude lies in the range iVp to 1/8Vp and an amplification factor of 4 is required. If BITS 2,3 and 4 are all low the input amplitude is less than 1/aVp and the amplitude factor is 8.This gives the basis of the amplification law used in the present arrangement, although it will be appreciated that in other arrangements other amplification laws could alternatively be adopted.

Figure 1 of the drawings illustrates two alternative circuits, used in accordance with the present invention, for determining the amplitude range of the analogue input signal and for putting the abovedescribed amplification law into effect.

In the first described embodiment the analgue switch, 10, and the associated attenuator, 11, enclosed within box, 100, and the AND gate, 12, are excluded from the circuit.

In this first embodiment the analogue input signal I/P is initially passed to a low pass filter 1 which removes unwanted high frequency signals, typically in excess of 20KHz. The filtered signal is then passed to a sample and hold circuit 2 which generates the input to a 12 bit AID converter 3, the amplification means 4, through which the sampled signal is passed, being set to an amplification factor of unity during this first pass through the converter. The converter 3 generates the four output bits (BITS 1 to 4 described above) necessary for determining the amplitude range containing the input signal, and since only four bits are required the conversion pro cess need proceed no further than this.The four bits generated by the converter 3 are passed via buffers to a true complement element 5 and the output therefrom is passed to an amplification control means 6 which is capable of generating two ranging bits, R1 and R2, having values indicative of the amplitude range containing the analogue input signal.

Figure 2 of the drawings shows a logic circuit suitable for receiving BITS 2,3 and 4 from the true complement element 5 and for generating the ranging bits R1 and R2, the symbols used in the circuit having their conventional meanings. If, for example, BITS 2, 3 and 4 are all "1", or alternatively if only BIT 2 or BITS 2 and 3 are "1" then both ranging bits, R1 and R2, have value "1". Alternatively if BIT 3 is "1" and BIT2 is "0" then R, will have the value "1" and R2 will have the value "0", and if BIT4 is "1" and BITS 2 and 3 are "0" then R1 will have the value "0" and R2 will then value "1". If all three bits are "0" however, then both R1 and R2 have the value "0" also.Each of the four possible combinations of values of R, and R2, therefore represents a different input amplitude range, although alternative circuits to receive more than three inputs will be readily envisaged by a person skilled in the art. In certain circumstances, for example when the amplitude of the analogue input signal is at leastVp, the lesser significant bits (BITS 3 and 4) are redundant for the purposes of determining the amplitude range. In another arrangement therefore a successive approximation AID converter is used to generate bits sequentially until sufficient information has been derived to generate the rang ing bits, R, and R2, i.e. until the converter first gener ates a bit having the value "1", at which point conversion ceases.Suitable command and short cycle pulses to accomplish this will be readily envisaged by a person skilled in the art, and these are produced by a crystal timing oscillator 7.

The ranging bits generated by the amplification control means 6 are used to set the gain of the amplification means 4 to the appropriate value i.e. to a gain of 1,2,4 or 8 in the present example. The amplification means 4 is a 4-channel programmable amplifier each channel thereof being responsive to only one combination of ranging bit values and having a different preset gain (i.e. 1, 2,4 or 8) as appropriate. Alternatively suitable amplification could be achieved using a variable gain amplifier and an associated decoderto receive the ranging bits.

Having updated the analogue input by an appropriate amplification factor and having allowed the system sufficient time to slew and settle (about 2,us is normally allowed after completion of the first conversion cycle) a second, full, conversion of the amplified input signal is performed, the 12 bit output being taken from the converter as a parallel word and loaded into a shift register 8 and then if desired read out serially for transmission. The output may be stored and decoded at a later stage. The ranging bits, R1 and R2, generated during the first conversion cycle are held in a quad latch 9 during the second conversion cycle and then loaded into the shift register 8 together with the output from the AID converter. As will be described below, the stored ranging bits are used to restore the decoded signal to its correct value.

In the above described arrangement it has been assumed that the amplitude range of the input signal and of the AID converter are identical, but in an alternative embodiment of the invention the AID circuit has a range 6dB less than that of the input signal. Thus whilst the range of the input signal may be + 10V, for example, the range of the converter may be only + 5V. The alternative embodiment is also shown in Figure 1 and includes the analogue switch, 10, and the attenuator, 11, enclosed within box 100, and the AND gate 12.

Provided the amplitude of the input signal does not exceed the converter peak coding value (t 5V) the arrangement still operates in the manner described above, the input signal being amplified by an appropriate factor (of 1, 2,4 or 8) selected in accordance with the values of the ranging bits generated during the first conversion cycle. If the amplitude of the input signal exceeds the converter peak coding value however, a 6dB attenuator shown at 11 in Figure 1 is switched into the circuit using the analogue switch 10, prior to the second pass through the converter, thereby bringing the amplitude of the input signal I/P, within the range of the converter 3.

In this embodiment the entire AID converter output signal derived from the first pass through the converter 3 is passed to the true complement element 4.

As before BITS 2,3 and 4 are used to generate an appropriate combination of ranging bits in accordance with the amplitude of the input signal, but in addition the entire output from the true complement element is passed to AND gate, 12, which generates a binary "1 " only if each element of the input thereto is also a binary "1" i.e. whenever the analogue input signal is at least equal to the peak coding value Vp of the converter. The AND gate therefore generates a third ranging bit R3, which is also stored in the latch 9 and provides an input to analogue switch 10. In this mannerthe analogue switch is activated to switch the attenuator 11 into the circuit whenever R3 has the value "1" i.e. whenever the analogue input signal I/P at least equals the peak coding value of the converter.The ranging bit R3 also constitutes part of the output from the arrangement and is loaded into shift register 8 along with R, and R2.

If the AND gate generates a binary "1" during the second conversion cycle this indicates that the analogue input signal still exceeds the converter peak coding value even after a 6dB attenuation and so the ranging bit, R3, generated during the second pass is used to indicate that limiting of the input signal is occurring.

Figure 3 of the drawings illustrates a circuit for decoding a loaded signal and for using the loaded ranging bits to restore the decoded amplitude to the correct value.

The coded data are loaded into a shift register 13f and then loaded into assembly latches, 14. Upon receipt of a suitable command signal the 12 bit output constituting the data is passed as a parallel word to a D/A converter 15 and the ranging bits, R1, R2 and R3, are simultaneously released to a decoder 16. The decoded ranging bits are passed to an analogue switch 17 which switch is an appropriate resistor (S, to S4) to attenuate the decoded signal to reconstitute the original amplitude. The attenuated analogue signal is then passed to a sample and hold circuit 18 to remove switching transients due to attenuation and conversion, and then to a low pass filter 19 to remove unwanted high frequency signals (typically greater than about 20KHz).

It may be desirable to attenuate the digital signal before decoding and provided bit saving is not of prime importance the ranging bits may be used in another arrangement to serially adjust the 12 bit output loaded into the shift register 8. If the input signal and the converter have the same range this may be achieved by using the generated ranging bits to gate up to three clocking pulses to the shift regis ter 8 to reduce the value of the stored bits by a factor of 2,4 or 8, as appropriate. For example if both R, and R2 are low (i.e. an amplification factor of 8 was applied by the amplification means 4) three docking pulses are generated to shift all the bits stored within the shift register by three positions downwards, thereby reducing the value of the bits by a factor of 8.

If both ranging bits are high however, then no clock ing pulses are generated and the arrangement of bits within the shift register remains unchanged. In this example of the invention, therefore, the ranging bits organisethe digital signal into a pseudo 15 bit for mat. If the third ranging bit R3 is also generated an additional amplification factor of 2 may be required (i.e. whenever R3 takes the value "1") and so in this case the digital output is organised into a pseudo 16 bit format. In both these examples it is necessary to use at least a 15 bit D/A converter to decode the signal art a later stage butthe need for setting precise gain adjustments after decoding is eliminated.

To ensure that the various stages of coding and decoding occur in their correct sequence they are organised using a conventional timing circuit.

A standard crystal timing oscillator, 7, generates pulses to activate the sample and hold circuit, the analogue to digital converter and the shift register in the correct sequence. A latch pulse is provided at the end of the first conversion to hold the range bits during the second conversion and an over-ride pulse ensures that both range bits R, and R2, which control the PRAM, have the value "1" (i.e. an amplification factor of 1) during the first cycle.

The STATUS signal from the analogue to digital converter produces a load pulse which loads the full digital output from the converter, and also the range bits from the latch if required into the shift register. A monostable 20 prevents the status pulse from pro ducing a load pulse after the first conversion.

The system described provides an arrangement whereby all the information necessary to organise a digital companding circuit is derived from the analogue to digital converter by double cycling, and as such is particularly versatile.

Due to the compact nature of this arrangement it is particularly well suited for use in a multichannel sys tern as used for example in recording studios.

Claims (11)

1. A digital companding circuit comprising an amplification means arranged to subject analogue input signals applied thereto to one of a plurality of discrete preselected degrees of amplification in dependence on a control signal applied to said amplification means, an analogue-to-digital conversion circuit coupled to the output of said amplification means and a feedback circuit for responding to output signals provided by the conversion circuit to generate said control signal, in dependence upon the amplitude of said output signals, to control the degree of amplification to be applied to said input signals, the circuit including means for conveying to an output location thereof a digitially converted output signal in respect of a given analogue input signal that has been controllably amplified by said amplification means and also information indicative ofthe degree of amplification determined by the control signal and applied to said given input signal.

2. A circuit according to Claim 1 wherein the given input signal is amplified by a factor of n, where n = 1,2,4 or 8 when the amplitude of the output signals lies in the range Vdn to VJ2n, Vp being the peak coding value of the A/D converter.

3. A circuit according to Claim 2 wherein the control signal comprises two ranging bits having values indicative ofthe amplitude range.

4. A circuit according to Claim 3 wherein the amplification means is a programmable amplifier.

5. A circuit according to Claim 3 wherein the amplification means is a variable gain amplifier cooperating with means for receiving and decoding the ranging bits.

6. A circuit according to Claims 1 to 5 wherein the feedback circuit includes means for generating a further control signal whenever the amplitude of the output signals at least equals the converter peak coding value, and means responsive to said further control signal for attenuating the given input signal by a preselected factor.

7. A circuit according to Claim 6 wherein said means for generating a further control signal is an AND gate for receiving the entire output from the AID converter.

8. A circuit according to Claims 6 or 7 wherein said preselected factor is 2.

9. A digital companding system comprising a digital companding circuit according to any one of Claims 1 to 8, a digital-to-analogue conversion circuit for receiving the digitally converted output signal from said digital companding circuit or for receiving a signal derived therefrom, and means responsive to said information to attenuate the output from the digital-to-analogue conversion circuit by a corresponding predetermined factor.

10. A digital companding arrangement as hereinbefore described by reference to and as illustrated in Figure 1 of the accompanying drawings.

11. A digital companding system, as hereinbefore described, by reference to and as illustrated in Figures 1 and 3 of the drawings.