GB2039429A - Ac switch using FET - Google Patents

Abstract

A field-effect transistor (FET) 10 is used as a switch for a load 12 energized by an AC source 11. A bias reference point is formed by two diodes 17 and 18 connected as shown to the two channel terminals of the FET. A control circuit 19,20,21 applies a control signal between the bias reference point and the gate 14 of the FET to turn it on or off. The diodes may be formed by the parasitic diodes of the FET 10, the bias voltage may be produced by rectifying the AC, and the control circuit may be powered from this bias voltage. The parasitic capacitance of the FET may form part of the control circuit. Shunting FET's may be provided to counteract the effect of unwanted parasitic components. Most or all of the active components of the control circuit may be formed in the same chip as the FET 10. A set of chips with individual FET's 10 may be used to provide several FET's in series for high voltages. <IMAGE>

Description

SPECIFICATION AC switch using FET The present invention is related to circuits in which power is transferred from an AC power supply to a load through a switch.

Various solid state devices have been used as switches in such circuits. For instance, planar bipolar power transistors have been used but these are devices which are not bidirectional by nature and which exhibit an inherent, more or less irreducible, minimum power dissipation characteristic even when fully switched on. And to be switched fully on, bipolar power transistors require a substantial amount of base current, i.e., control current, especially for higher collector, or load currents. Furthermore, they are also subject by nature to thermal runaway.

Perhaps more commonly used for controlling alternating polarity power supplies are thyristors of various kinds such as silicon controlled rectifiers and triacs. Such thyristors are switching devices primarily used in alternating polarity power supply control circuits because of their capability of handling relatively large power dissipations when switched fully on and for withstanding substantial reverse voltages when switched fully off. An advantage of these devices over bipolar power transistors is that they require little electrical power at device control gates whether operating in the off condition or in the on condition.

However, a thrysistor also has several disadvantages such as being a latching switch; that is, it cannot be switched off by a control signal once it has been switched on. Also, it can be switched on by sharp voltage transients thereacross without any action taking place at its control terminal. The control terminal, in many situations, cannot be electrically isolated simply and inexpensively from the load circuit, and large triggering currents may be required to switch on the thyristor devices. Finally, a thyristor cannot be easily provided in a monolithic integrated circuit with other circuit components because of its structure and power dissipation.

Hence, better primary power controlling devices are desired for use in controlling power transfer from alternating polarity electrical power supplies in alternating polarity operated circuits. Particularly useful would be a device which could be easily provided in a monolithic integrated circuit along with other circuit components, at least some of which would also be used in controlling power transfer from the AC power supply used. This would require that such a device not have too large a resistance if switched fully on, despite substantial current loads, but which would have a structure easily fabricated in such an integrated circuit. Further, the device should have a bidirectional current conduction capability for circuits in which current rectification is not desired.

Field-effect transistor devices can have many of the characteristics just described, including having a very symmetrical bidirectional current conducting capability when on. This is certainly so for metaloxide-semiconductorfield-effecttransistor (MOS FET) devices, which have the advantage of having the gates therein being very well isolated from the channel regions of the device. This isolation aids in providing a circuit to operate the field effect transistor device when both the circuit and these devices are formed in a monolithic integrated circuit chip, a difficult arrangement when the integrated circuit is to operate with an AC power supply.Such circuits must permit the operation of other circuit component devices in the monolithic integrated circuit while also controlling power transfers from the alternating polarity power supply through operating the primary power transfer control field-effect device.

Field-effect transistors are controlled by controlling the voltage appearing between the gate thereof and that one of the connections to the channel regions therein which is effectively serving as the transistor source. Difficulties arise in those circuits using a field-effect transistor to control power transfers from an AC power supply because the two connections to the channel region of such a transistor serve alternately as the source rather than one of them serving continually as the source.

Accordingly the present invention provides an AC switching circuit comprising an AC source, a load, and a switch comprising a main FET (field-effect transistor) all connected in series, a pair of diodes connected betwen the two channel terminals of the main FET and a bias reference point and correspondingly poled towards the bias reference point, and a control circuit connected between the bias reference point and the gate of the main FET.

A variety of switching circuits in accordance with the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 shows a basic form of AC switching circuit; Figure 2 shows a variation using a different form of FET; Figure 3 shows a control switch for use in the Figure 1 circuit; Figure 4 shows the parasitic components of the FET; Figure 5 shows a variation of the Figure 1 circuit in which parasitic diodes are used; Figure 6 shows a development of the Figure 5 circuit in which a rectifier generates a bias voltage; Figure 7shows a development of the Figure 6 circuit with a control circuit; Figure 8 shows a development of the Figure 5 circuit in which parasitic capacitance is used; Figure 9 shows a development of the Figure 1 circuit in which parasitic capacitance is used;; Figure 10 shows the use of a plurality of FET's to withstand higher voltages; Figure 11 shows a development of the Figure 6 circuit including a control circuit and shunting FET's; Figure 12 shows a development of the Figure 8 circuit using shunting FET's; and Figure 13 shows another development of the Figure 8 circuit using shunting FET's and a modified control circuit.

Figure 1 shows a first power switching circuit. The primary power controlling device is a field-effect transistor device, 10, which controls the flow of powerfromanACpowersupply 11 toa load 12, which is shown as a resistive load for simplicity though it could also have a reactive component.

Field-effect transistor device 10 is shown as a conventional enhancement mode, p-channel fieldeffect transistor but can be any field-effect device which is functionally equivalent to such an enhancement mode, p-channel field-effect transistor, as may happen where some or all of the circuit of Figure 1 (other than the power supplies) is to be formed in a monolithic integrated circuit, including forming device 10 therein.

Field-effect transistor 10 has an open-circuit substrate electrode 13, a gate electrode 14, and two electrodes 15 and 16 which are connected to pass through transistor 10 whatever major currents are to flow therethrough, and which provide ohmic contact to the electrical path regions encompassing the channel region of transistor 10. As the polarity of supply 11 alternates, electrode 15 will alternately serve as a source and as a drain in the circuit of Figure 1, and electrode 16 will be simultaneously serving in the opposite role.

Two diodes 17 and 18 are connected as shown from electrodes 15 and 16 of transistor 10 through a resistor 19 to gate electrode 14. Each of electrodes 17 and 18 has a small but finite reverse current leakage therethrough before any reverse bias voltage thereon reaches breakdown values. The value of resistor 19 is not critical and a typical choice would be 1.0 megohm. A constant polarity voltage supply 21 is connected in series with a switch 20, and this series arrangement is placed in parallel with resistor 19 as shown.

To understand the operation of this circuit, first consider the situation in which switch 20 is open and the load side of supply 11 is positive relative to the other side. In this situation, the circuit will prevent any significant power from being delivered to load means 12 from supply 11 by virtue of transistor 10 being switched off. Electrode 15 serves as the source while electrode 16 is the drain. Hence if transistor 10 is to be switched on, gate electrode 14 must be more negative than electrode 15 by an amount at least exceeding the threshold voltage of transistor 10. In the situation being considered, with switch 20 open, transistor 10 is maintained off because gate 14 is only a diode voltage drop more negative in voltage than electrode 15, which is following the positive voltage on supply 11.A gate current for charging gate capacitances of transistor 10 and supplying gate leakage currents will flow through diode 17 and resistor 19, the gate leakage current being very small because of the very high gate impedance of transistor 10. Also, diode 17 and gate capacitances will supply the above-mentioned leakage current of diode 18 which is reverse biased and otherwise plays no role in the circuit operation in this positive half-cycle of supply voltage 11. The resulting voltage drop across diode 17 is less than the threshold voltage of transistor 10 so that transistor 10 is off.

When the polarity of the load side of supply 11 changes so that a negative voltage appears on electrode 15 with respect to electrode 16, electrode 16 becomes the source while electrode 15 becomes the drain. Then if transistor 10 is to turn on, the gate electrode 14 must be more negative than electrode 16 by at least the threshold voltage of transistor 10.

But with switch 20 open, gate 14 is no more than one diode voltage drop more negative than electrode 16 due to the voltage clamping of diode 18 (and it may be more positive because of previously charged gate capacitance if these are not sufficiently discharged by the leakage of diodes 17 and 18). Diode 17 is reverse biased and, beyond its reverse current leakage, has no effect on circuit operation in these conditions. Hence, transistor 10 continues to be maintained off. The result is that, with switch 20 open, transistor 10 is off throughout the full cycle of the voltage supply 11.

If the supply is sufficient and the reverse leakage of diodes 17 and 18 is sufficiently small, the gate capacitances may have an average charge after the initial power supply cycle sufficient to keep both diodes 17 and 18 reversed biased except at times when the supply voltage is near its peak. In these circumstances, there will always be a positive voltage on gate 14 acting to hold transistor 10 off. Such parasitic capacitance effects will for the most part be ignored in the following, on the assumption that the supply frequency is sufficiently low to permit these parasitic capacitances to discharge sufficiently not to alter the current operation described.

Now, in contrast, consider the situation with switch 20 closed. When the load side of the supply 11 is positive, i.e., when electrode 15 is positive with respect to electrode 16, then gate 14 is more negative than electrode 15 by the diode drop due to diode 17 plus the voltage provided by supply 21.

Thus, if the voltage of supply 21, placed between the acting source and the gate of transistor 10, is sufficiently in excess of the transistor 10 threshold voltage, transistor 10 will be strongly turned on in the circuit of Figure 1 when switch 20 is closed. This result permits power to be delivered from supply 11 to load means 12 through transistor 10. Diode 18, being reversed biased in these circumstances, does not affect circuit operation.

Of course, sufficient positive voltage on gate 14 due to gate capacitances not having been sufficiently discharged may result in the voltage on gate 14 remaining positive with respect to electrode 15 despite switch 20 being closed. Then transistor 10 would remain off even though switch 20 had been closed. As stated above, such parasitic capacitance effects will not be further considered because a sufficiently low supply frequency is being assumed.

When the voltage of supply 11 reverses, it can be seen from the symmetry of the circuit that transistor 10 is again turned on. Thus when switch 20 is closed, current will flow through transistor 10 throughout the supply cycle.

It will be realized that the switch 20 could be replaced by a 2-way switch, connecting the gate 14 to either the resistor 19 or the battery 21. If this is done, then the resistor 19 can be removed and replaced by a short, so that gate 14 would be connected to the junction of diodes 17 and 18 either directly or via battery 21.

Figure 2 shows a modification of the circuit of Figure 1, including two changes. A new field-effect transistor device, 10', is substituted for the enhancement mode, p-channel field-effect transistor 10 of Figure 1. Also, power supply 21' has been substituted in Figure 2 for supply means 21 of Figure 1, supply means 21' having a reversed polarity. Device 10' is, or behaves effectively as, a depletion mode, p-channel, metal-oxide-semiconductorfield-effect transistor. Operation of the circuit in Figure 2 is essentially like that in Figure 1 except that transistor lo' is now turned on when switch means 20 is open because of operation of transistor 10' in the depletion mode.

In the depletion mode, a transistor is turned on when the gate is at some negative voltage, at zero voltage or at a positive voltage less than some threshold voltage with respect to the source voltage.

Only when the gate voltage is more positive than the source voltage by at least the threshold voltage is the transistor turned off. Hence, when switch means 20 closes, gate 14' will be held positive by supply 21' with respect to whichever of electrode 15' and 16' happens to be acting as the source by virtue of that electrode being positive with respect to the other depending on where supply 11 is in its output voltage cycle. This relative positiveness of electrode 14' will lead to turning off transistor 10' if the magnitude of voltage supply 21' is sufficiently large.

Devices such as junction field-effect devices (JFET) and metal-semiconductor field-effect devices (MES FET) are also basically depletion mode devices.

Thus, devices of these kinds, with properly chosen conductivity type channels, will operate in MOSFET depletion mode circuits such as that of Figure 2.

If n-channel devices are used, the necessary circuits will of course correspond to the circuits of Figures 1 and 2 with all polarities reversed.

The preceding circuit operation descriptions for the circuits of Figures 1 and 2 assume a sufficiently low supply frequency. Otherwise parasitic capacitive, diode and resistive effects associated with the power control transistor in these circuits may lead to different operation results. One possible mannerto raise the allowed supply frequency would be to effectively increase the leakage of the diodes in these circuits by shunting them with resistors.

The switch 20 has for convenience been shown as a mechanically operated switch. However, in most applications of this circuit, an electronic switch is more likely to be used. Figure 3 shows one possible electronic switch for use in the circuit of Figure 1.

The switch 20', replacing switch 20 of Figure 1, comprises an n-channel, enhancement mode, metaloxide-semiconductor field-effect transistor 60 having a drain electrode 61, a source electrode 61, and a substrate electrode 63. An input control signal voltage source 65 is connected between gate region 64 and terminal 62 of transistor 60. A p-channel, enhancement mode MOSFETwith an open-circuit substrate could also be used in place of transistor 60, but with such a p-channel MOSFET, control source 65 would be connected between the counterparts of gate 64 and terminal 61.

When, in the circuit of Figure 3, a voltage signal sufficiently larger than the threshold voltage of transistor 60 is provided by signal source 65, transistor 60 will be turned on causing a negative bias voltage, due to supply 21, to appear at gate 14 of transistor 10, sufficient to turn on transistor 10.

When the circuits in Figures 1 to 3 are to be partially or fully integrated in monolithic integrated circuits, the circuit components will be provided in appropriate manner. That is, for instance, the diodes may be provided by having a metal-oxidesemiconductor transistor operated with its drain tied to its gate while the resistors may also be formed by an active circuit component or by an electrically isolated semiconductor material portion serving as a passive resistor.

Figure 4 is a more detailed diagram of the transistor 10, showing a considerable number of effective but parasitic components in lumped form, all of these being present as a result of the structure of transistor 10. These parasitic components are in many cases more likely to be significant for a power controlling transistor such as transistor 10 because such a transistor is likely to be large compared to transistors used only for control signals.

Among the parasitic components shown in Figure 4 are a gate-to-channel capacitance 22 and a channel-to-substrate capacitance 23. Two other parasitic capacitances 8 and 9 are shown which are each effective between gate 14 and one of channel terminating regions 15 or 16. There is also shown the two parasitic channel-to-substrate diodes, 24 and 25, which are provided in the structure of transistor 10 by the semiconductor pn junctions occurring between the regions for source and drain connections to transistor 10 and the substrate of transistor 10. In a p-channel MOSFET, for instance, the substrate material is of a n-type conductivity while the connection regions 15 and 16 which terminate the ends of the channel region in the transistor 10, and serve as source and drain regions therein, are formed by diffusion or implantation of p-type conductivity impurities into the substrate material.

Also associated with these pn junctions are parasitic resistances 26 and 27 and parasitic capacitances 28 and 29. All of these parasitic componets will have more or less of an effect on the operating behavior of transistor 10, and soon the behavior of the circuit in which transistor 10 is provided, the significance of the effect depending on the conditions existing in such a circuit. Of course, capacitance 22 is essential for switching on transistor 10 while the other parasitic components shown with transistor 10 are normally desired to contribute as insignificantly as possible to the circuit operation.

Figure 5 is a variant of Figure 1 where the diodes 17 and 18 in the circuit of Figure 1 are provided in the circuit of Figures 5 by the parasitic effective diodes 24 and 25 inherent in the structure of transistor 10 as formed in a substrate having a connection point 13 therein. To have diodes 25 and 26 substitute for diodes 17 and 18 in Figure 1 effectively, a direct electrical connection is made between substrate 13 and resistor 19 as shown in Figure 2. Assuming that the supply frequency is not high enough for the parasitic capacitances shown in Figure 4 to change the operating characteristics, the operation of the Figure 5 circuit will be the same as that of the Figure 1 circuit. The Figure 2 circuit can of course be modified similarly.

The circuits of Figures 1 and 5 can control an AC supply, but it would be desirable to eliminate the need for a second power supply 21. In some circumstances, the use of another control circuit scheme which would avoid depending on the parasitic diodes inherent in the primary power transfer controlling transistor, but not requiring two separate diodes, would also be desirable.

Figure 6 shows such a circuit in which a capacitor 30 acts as an energy storage means which energizes the input signal controlled circuitry used to control the transistor 10. The parasitic components shown in Figure 6 are just the parasitic diodes 24 and 25 of Figures 4 and 5. At sufficiently low frequencies, the parasitic capacitances shown in connection with transistor 10 in Figure 4 will not be signficant factors in the operation of the circuit of Figure 6. Also, the leakage resistances 26 and 27 of Figure 4 are usually sufficiently large that they also will not be significant in the operation of this circuit. The gate of transistor 10 is connected to a switch 32 which can be switched to either side of capacitor 30. Capacitor 30 is connected between substrate connection 13 and a diode 31 which is connected to the junction of the supply 11 and the load 12.

The sole source of power used to operate the circuit of Figure 6 is supply 11. Supply 11 not only provides power for controlled transfer to the load 12, upon being selected to do so by appropriately activating a switch means 32, but also provides power to be stored in capacitor 30 to operate the other circuit components present used to control transistor 10. Of course. a separate power supply means could be used in place of capacitance 30, and a circuit for which this must be done using depletion mode devices is described below.

In operation with switch 32 connecting gate 14 to the substrate side of capacitor 30, the supply 11 will charge capacitor 30. This occurs when the side of supply 11 not connected to load 12 is positive while the side connected to load 12 is relatively negative.

In these circumstances, a charging current will flow through channel terminating region 16, parasitic diode 15. capacitor 30. and diode 31 to thereby charge capacitor 30. When supply 11 changes polarity, there will be no current flow through capacitor 30 due to supply 11 because diode 31 will be reserve biased. Further, there will be little discharge of capacitor 30 because of the reverse bias nature of all the diodes, including the parasitic ones, between the positive side of capacitor 30 and its negative side.

The only discharge of capacitor 30 under these circumstances will be due to small leakages through the large value leakage resistances present but not shown.

In this situation, transistor 10 will be held fully off because of the short occurring between gate 14 and substrate 13 through switch 32. Gate 14 will follow the substrate, which will always be within a voltage drop across one of the parasitic diodes 24 or 25 of the positive side of supply 11. Thus, the threshold voltage of transistor 10 will never be exceeded by the voltage occurring between gate region 14 and whichever of the terminating regions 15 and 16 is positive with respect to the other.

When switch 32 is changed over to connect the negatively charged side of capacitor 32 to gate region 14, transistor 10 is switched on. This occurs because gate region 14 is held negative with respect ot the substrate by the voltage appearing across capacitor 30. Yet, the substrate is still always within a diode voltage drop of the positive voltage appearing on one or other side of supply 11, through parasitic diodes 24 and 25. As a result, the gate of transistor 10 is held negative with respect to whichever of channel terminating regions 15 and 16 is positive and acting as the transistor source. For sufficient voltage across capacitor 30 (which in turn depends on a sufficient peak output voltage being provided by supply 11), in these circumstances, transistor 10 will be fully on.

Note that the occurrence of any discharging of capacitor 30 through the leakage resistances (not shown in Figure 6) spanning parasitic diodes 24 and 25 will not make any difference in the circuit operation. This is because supply 11 will recharge capacitor 30 on each half cycle during which the side of supply 11 not connected to the load means 12 is positive. Again, the charging path will be through the parasitic diode 25 and diode 31.

Thus, the circuit of Figure 6 provides a manner to control power transfers from alternating supply 11 to load 12 by simply having the switch 32 connect gate region 14 to one side or the other of capacitor 30. No external electrical power supply is required for operating the gate of the primary power transfer controlling component, transistor 10. The power for controlling this gate is supplied by supply 11 in storage across capacitor 30.

Certain modifications of this circuit are also possible. First of all, the addition of a diode 33 (shown by dashed lines) leads to capacitor 30 being charged in every half cycle of supply 11, assuming that diode 31 is retained. However, diode 31 could be eliminated and the circuit would continue to operate but not quite so satisfactorily as when diode 31 is present along.

The difficulty where diode 33 is used alone arises because this leads to transistor 10 not being always fully on when switch 32 is connected to the negative side of capacitor 30 for the purpose of bringing this about. This is because the recharging of capacitor 30 for any charge losses occurring, due to leakages, cannot take place unless transistor 10 is sufficiently turned off for the voltage drop thereacross to rise to a level of a few volts. Until that occurs in an arrangement using diode 33 alone, transistor 10 will have so little voltage drop across it (that is, will appear effectively as a short circuit) that no charging current will be able to flow through parasitic diode 24 to charge capacitor 30.

This same kind of problem arises if the load is removed from the location 12 and placed at location 34. Note, however, that these circuits are operable but that the current provided by supply 11 through load 34 will decrease somewhat from what it would have been had transistor 10 stayed fully turned on, and the power dissipation in transistor 10 will increase. Use of load 34 in place of load 12 will also require an initial current, during the first half cycle after switch 32 is activated, to switch transistor 10 on, to be drawn through load 34 to charge capacitor 30. Other possible load locations are 35 and 36.

Figure 7 now shows a circuit which is equivalent to the circuit of Figure 5 but which has an electronic implementation for the switch 32. Portions of the circuit shown in Figure 6 are shown in a circuit form suitable for integration in a monolithic integrated circuit chip, including switch 32. The diode 33 is shown as a p-channel MOSFET having its gate region shorted to one of the channel terminating regions thereof to thereby exhibit the characteristics of a diode. This p-channel MOSFET can be formed in the monolithic integrated substrate along with transistor 10 and along with p-channel MOSFET's 41 and 42 used in the switch 32.Diode 31, however, cannot be formed as a p-channel MOSFET integrated in the same monolithic integrated circuit chip where its substrate would be electrically in common with the substrates of the other transistors, and so has continued to be indicated by the normal diode symbol in this figure usually indicating an ordinary pn semiconductor junction diode. This is due to detrimental interaction occurring between the diode and other circuit components if provided on common or electrically joined substrates. Hence diode 31, if used at all, will be provided as an external component to any monolithic integrated circuit version of the circuit.On the other hand, diode 31 may, as before, be used exclusively without making any use of diode 33 where no current is desired to be passed through the load means 12 and no partial turn off of transistor 10 is desired during times when transistor 10 is otherwise to be on. Of course, diode 33 may be used exclusively without diode 31 where these factors are not important.

The substrate of diode 31 can be in common with the substrate of other transistors in Figure 6, even if diode 31 is formed by a field-effect transistor, if the load is removed from location 12 and placed instead at location 34.

In the circuit of Figure 7, field-effect transistors 41 and 42 and the associated switch control circuitry 43 are all electrically energized through the stored electrical energy provided on capacitor 30 by supply 11. Thus, no further power supplies are required to operate the circuit although, of course, storage means 30 could be a battery equivalent rather than a capacitance. Switch control circuitry 43 is expected to be formed in the monolithic integrated circuit with transistors 10,41 and 42 and is therefore typically going to be constructed with p-channel MOS circuitry components. Switch circuitry 43 will contain such electronic or electromechanical components, or sensors, or some combination thereof, as desired to produce the signals to operate field-effect transistors 41 and 42 as a switching means output to control the operation of the circuit.

In operation, switch 32 has transistor 41 on and transistor 42 off, or vice versa, as determined by control circuitry 43 and so these transistors together operate in series as the single pole, double throw switch 32 shown in Figure 6.

Figure 8 shows an alternative form of the control circuitry where the entire control circuit can be formed in a single monolithic integrated circuit chip.

Again, the primary power transfer control component is a p-channel field-effect transistor 10, with parasitic diodes 24 and 25 being shown along with parasitic gate-to-channel capacitance is the key to the operation of the circuit as it provides the bias voltage necessary to operate transistor 10 in those half cycle of power supply 11 in which a signal controlled transistor 50 for controlling transistor 10 is turned off.

Signal controlled transistor 50 is controlled by the bias control voltage source 57. Transistor 50 is also an enhancement mode, p-channel, MOSFET device although not necessarily similar to transistor 10 since transistor 50 need not carry the substantial currents which transistor 10 may in controlling powertransfersfrom supply 11 to load means 12.

The two parasitic diodes inherent in the structure of transistor 50 are shown and the gate region 53 of transistor 50 is connected to supply 11 as shown.

Bias control voltage source 57 may be connected between electrode 52 of transistor 50 and supply means 11 as shown; alternatively it may be connected between terminal 52 and the substrate point 13, as shown by the broken line. The substrate connections 13 of transistor 10 and 56 of transistor 50 are joined in common as would effectively be the case in a monolithic integrated circuit. Bias control voltage source 57 is capable of switching terminating region 52 of transistor 50 between zero volts and a negative voltage with respect to side of source 57 connected to supply 11. This negative voltage must sufficiently exceed the threshold voltage of transistor 10 to be capable of switching transistor 10 on strongly.

To understand the operation of this circuit, we consider first the state of transistor 50 on successive half-cycles of the supply 11. When the top end of supply 11 is positive, the gate of transistor 50 is fed with the most positive voltage in the circuit, and this transistor is therefore off. When the top end of supply 11 is negative, the gate of transistor 50 is negative and this transistor is turned on.

We next consider the voltage of the substrate point 13 of the transistor 10. On successive halfcycles of the source 11, the two channel terminals 15 and 16 of the transistor 10 will be positive alternately. The substrate point 13 must be at least as positive as the positive one of the two channel terminating regions 15 and 16; but if it is more positive than either, its voltage must fall gradually (because of leakage resistances, not shown). Hence the voltage at point 13 will follow the more positive of the two regions 15 and 16, apart from transient periods.

Consider now the situation where the bias source 57 produces 0 V (relative to the bottom of supply 11). When transistor 50 is on, this will put the same 0 V on the gate of transistor 10. For transistor 50 being on, the top end of supply 11 is negative, and the substrate 13 will therefore follow terminal 16, which is a O V (relative to the bottom of supply 11 again).

The parasitic capacitance 22 will have no appreciable charge produced on it. Also, since the gate of transistor 10 is at the same voltage as the more positive of terminals 15 and 16, transistor 10 will be off.

On the next half cycle of the supply 11, transistor 50 will be off. Terminal 15 of transistor 10 will be the more positive of its two channel terminals, and will act as the source. Parasitic diode 24 will hold the substrate 13 at the same voltage as terminal 15, and parasitic capacitance 22 will hold the gate 14 of transistor 10 at the same voltage as the substrate and, hence, source terminal 15. Transistor 10 will therefore remain off.

In contrast, consider now what happens if the bias source 57 produces a negative voltage (relative to the bottom end of supply 11). When transistor 50 is on, this negative voltage will appear also on the gate of transistor 10, and turn this transistor on. The negative voltage will also appear on the left-hand side of capacitance 22. This will tend to pull the right-hand side of this capacitance negative, so diode 25 will conduct, holding the right-hand side of capacitance 22 at O V and charging the capacitance as shown. When the supply 11 polarity reverses, on the next half-cycle, terminal 15 will become the source of transistor 10. Diode 24 will hold the substrate 13 at the voltage of terminal 15, and capacitance 22 will therefore hold the gate 14 at a negative voltage relative to terminal 15. This will hold transistor 10 on during this half-cycle.

The circuit of Figure 8 thus operates by direct control of transistor 10 by the bias source 57 during alternate half-cycles, with transistor 10 being kept on or off during the remaining half cycles by the capacitance 22. The charge on capacitance 22 does not change appreciably during a supply half-cycle, but will decay sufficiently within a few supply cycles to enable transistor 10 to be fully turned off shortly after a change of the bias voltage from negative to zero. When the bias voltage changes from zero to negative, the new charge on capacitance 22 is of course established very rapidly.

Figure 9 shows a similar circuit using a depletion mode transistor 10'. The parasitic diodes of transistor 10' play no part in the operation of this circuit; instead, the two diodes 17 and 18 are used, being shunted by resistors 58 and 59 as shown, and a battery 54 is included. The diodes 17 and 18 could be integrated in the chip.

There can be situations encountered where the peak voltage of the power supply is greater than the breakdown voltage which can conveniently be achieved in the design of a single field-effect transistor. In such situations, a plurality of these field-effect transistor devices can be connected in series to provide a switch for such a power supply. Such a series circuit is shown in Figure 10. This circuit cannot be provided in a single monolithic integrated circuit chip because of the need for the substrates of the field-effect transistors to be operated at differing voltage levels.

Figure 10 shows two depletion mode p-channel MOSFET's 1 OA and 10B arranged in series. Each has its own bias circuit, consisting of two diodes 1 7A and 18A, a battery 100A, and a resistor 75A for transistor 10A. In addition, the gates of the two transistors 1 OA and 10B are connected, through respective series resistor-diode paths 76A-77A and 76B-77B, to a switch 78 which is connected to the junction of diodes 17A and 18A.

The operation of this circuit is as follows. Consider first what happens if switch 78 is open. For transistor 1 OA, the junction of diodes 1 7A and 1 8A is at the same voltage as the more positive of the two channel terminating regions, and the gate will therefore be more positive than this by the voltage of battery 100A. Transistor 1 OA will therefore be turned off. Transistor lOB will similarly be turned off.

The two diodes 77A and 77B prevent any interar.tion between the voltages on the gates of the two transistors.

Consider now what happens if switch 78 is closed.

If this occurs at the instant that the supply voltage from supply 11 is zero, the voltage at the junction of diodes 17A and 18A will be zero, and hence the voltage at the junction of diodes 77A and 77B will be zero. Resistors 76A and 76B must be omitted or chosen to be small enough, compared to resistors 75A and 75B, for this to bring the voltages on the gates of transistors 1 OA and 1 OB to zero, or sufficiently near zero to be below the threshold voltage for these transistors.

If the voltage at the top end of supply 11 now goes positive, the near zero voltage on the gates of the transistors 10A and lOB will ensure that they are both turned on. If on the other hand the voltage at the top of supply 11 now goes negative, the near-zero bias on the gate of transistor 10A will ensure that this transistor is turned on. This will bring the voltage at the junction of diodes 17A and 1 8B to the voltage at the bottom end of supply 11, and the near-zero bias on the gate of transistor lOB will ensure that this transistor also turns on.

It will be evident that a similar technique may be used for enhancement mode transistors. More specifically, if transistors 10A and 10B in Figure 10 are replaced by enhancement mode transistors, the diodes 17A, 17B, 18A and 18B, and the batteries 100A and 100B should be removed; the individual battery bias is not required for enhancement mode devices, and the diodes may be provided by the inherent parasitic diodes of the transistors. The switch 78 is now connected to either the substrate of the lower transistor 1 OA or to the bottom end of the supply 11, and a single bias battery is connected in series with switch 78 to give a negative bias on the transistor gates when the switch is closed.

The single bias battery may be replaced, in this arrangement, by a diode-capacitor-diode series circuit across the supply 11, with the two diodes both poled so as to be conductive when the bottom end of supply 11 is positive. In this arrangement, the capacitor will become charged with one side positive and the other negative, and the switch 78 must be connected to the negative side of the capacitor and the substrate of the lower transistor 1 OA.

We return now to a further consideration of the circuit of Figure 7. As has previously been stated, it has been assumed hitherto that the supply frequency is low. The parasitic capacitances shown in Figure 4 have therefore been ignored, apart from in the Figure 9 circuit. If the frequency is sufficiently high, however, the various parasitic capacitances shown in Figure 4 can have several deleterious effects.

Considering the circuit of Figure 7, at least three detrimental circuit operation effects of possible significance can occur. First, the charging of parasitic capacitances 28 and 29, and capacitor 30, with transistor 10 off can lead to bipolar transistor action between terminating regions 15 and 16 in the form of an effective pnp transistor tending to provide a more or less conductive pathway between terminating regions 15 and 16, which are intended to be electrically isolated from one another in these circumstances. Second, the charge on these parasitic capacitances may lead to delays in the intended operation of transistor 10 because of the charge in the parasitic capacitors tending to maintain earlier existing conditions about transistor 10 until these parasitic capacitances have been discharged.This can lead to transistor 10 responding slowly, incompletely or not at all to the control signals applied to it.

Finally, the charging of the parasitic capacitances leads to a voltage thereacross which can add to the voltage from power supply 11 as it changes polarity.

This situation can either cause transistor 10 to breakdown or will require the breakdown voltages associated with transistor 10 to be approximately twice as large as the peak voltage from power supply 11.

These undesirable effects are particularly likely to be encountered with the use of a large physical size transistor, such as is usually necessary for controlling the transfer of substantial amounts of power from the power supply 11 to the load. It is thus desirable to be able to eliminate these parasitic effects, and it is also desirable to accomplish this in a way which permits providing constant polarity powerto other circuit components, including auxiliary control components used in controlling the primary transfer control field-effect transistor device, and yet requires only the presence of the alternating power supply as the single electrical power source.

Figure 11 shows an improved version of the circuit of Figure 7 as well as showing the control switch means 32 in more detail.

In the control circuit 43 an AND gate 46 controls transistor 41 directly and controls transistor 42 via an inverting transistor 47. Thus one or other of transistors 41 and 42 will be on, and the other off.

Logic gate 46 is shown with two inputs, although there may well be more in a particular application of the circuit, with one of the inputs shown being unconnected and intended for receiving an external signal provided by the user of the circuit. The other input shown is connected to further circuit components which are used to verify that a sufficient voltage appears on capacitance 30 to operate control circuit 43, as will be discussed below. Of course, other kinds of circuit components could be used in control circuit 43 such as bipolar transistors or even mechanical switches to achieve the same control functions, though in different circuits.

The circuit of Figure 11 includes a pair of bypass transistors 48 and 49. These transistors are used to selectively shunt the parasitic capacitances 28 and 29. As a result, these transistors can also supply the charging current to capacitance 30 to eliminate any bipolar action between terminating regions 15 and 16 of transistor 10. The transistors 48 and 49 have their main channels connected to shunt capacitors 28 and 29 as shown, and have their gates crossconnected to terminals 16 and 15 respectively as shown.

In operation, consider first the situation where transistor 41 is switched fully on. There will be in effect a short between the gate of transistor 10 and its substrate. In this situation, the gate follows the voltage on whichever of terminating regions 15 or 16 of transistor 10 is serving as the source. Under these circumstances, transistor 10 will be switched off.

Suppose also that the voltage on the load site of power supply 11 is positive. Then terminating region 48a of transistor 48, terminating region 31a of transistor 31, terminating region 49b of transistor 49, and terminating region 33b of transistor 33 on the relatively positive side of the channels of these transistors will all be serving as sources for these transistors.

Since gate 48c of transistor 48 and gate 33c of transistor 33 will be negative with respect to the source regions 48a and 33b of transistors 48 and 33, these two transistors will be switched on. The gate regions 49c and 31 c of transistors 49 and 31, will be positive or approximately equal to the voltages appearing on source regions 49b and 31a of these transistors, so that these transistors will be switched off. Transistor 48, in being on, will entirely shunt, or effectively short, parasitic diode 24, parasitic capacitor 28, and the parasitic resistance 26 (Figure 4), so that these will have effectively no role in these conditions. Thus, a charging current will flow through load 12, transistor 48, capacitor 30, and transistor 33 to thereby charge capacitor 30.

Also, a charging current will flow through load 12 and transistor 48 to charge parasitic capacitor 29.

Again, a charging current will flow through transistor 41 to charge the parasitic capacitance 8 between the gate 14 and terminal 16 of transistor 10. In a similar manner, the other parasitic capacitances of transistor 10 will also be more or less charged. Were transistor 48 not present, parasitic capacitance 28 would also be charged and parasitic diode 24 forward biased.

Note that with transistors 48 and 41 both being on, gate region 14 of transistor 10is held at the voltage appearing on both substrate connection 13 and terminating region 15 thereof. Hence, transistor 10 is indeed off.

When the polarity of supply 11 reverses so that the load side of supply 11 is negative, transistors 33 and 48 are switched off and transistors 31 and 49 are switched on.

Switching on transistor 49 rapidly discharges whatever charge has accumulated on parasitic capacitance 29. Such charge otherwise would lead to a voltage thereacross, which would add to the voltage being supplied from supply 11 to increase the reverse voltage appearing across parasitic diode 24 tending to cause breakdown thereof. Furthermore, if the impedance in the charge and discharge paths for the parasitic capacitances of transistor 10 are too large, the charges accumulated on these capacitors may hold gate region 14 relatively negative and tend to keep transistor 10 on when it should be switched off in this situation. Therefore, the discharge paths for these capacitances are assumed to be of a sufficiently low impedance to permit the discharge thereof so that transistor 10 is not switched on.

Circuit means to assure this are discussed below.

Thus, in this half cycle in which the voltage on the load side of supply 11 is negative, a charging current is provided through transistors 31 and 42, to maintain capacitor 30 charged. Further, a charging current will flow through transistor 49 to charge capacitance 28, and through transistor 41 to charge capacitance 9 between gate 14 and terminal 15. The other parasitic capacitances of transistor 10 are not charged because of transistors 41 and 49 being on.

With transistor 41 being on and transistor 49 being switched on, gate region 14 remains at the voltage appearing on both substrate 13 and terminating region 16. This again assumes that there was sufficiently rapid charging and discharging of the parasitic capacitances of transistor 10. Therefore, transistor 10 continues to be switched off.

Consider now switching transistor 10 on by virtue of having transistor 41 off and transistor 42 on, so that the gate 14 of transistor 10 is negative with respect to its substrate 13.

With transistor 10 switched on and the load side of supply 11 positive, little current will flow through transistor 33 even though it is switched on and there will be little charging of capacitor 30. On the other hand, there will not be any tendancy for capacitor 30 to discharge because of reverse biased parasitic diodes 24 and 25, though there may be some discharging leakage current through the parasitic resistances 26 and 27 in parallel with these diodes and control circuit 43. Also, there will be no charging of parasitic capacitances 28 and 29 by supply 11 because terminating regions 15 and 16 will be very close to being at the same voltage. On the other hand, the remaining parasitic capacitances 8, 9 22 and 23 of transistor 10 will all be charged in such a manner as to tend to keep transistor 10 on.This could delay turning off transistor 10, by the control circuit 43 at some later time, unless again the associated discharge paths for these capacitances are of sufficiently low impedance.

When the load side of supply 11 goes negative, transistors 31 and 49 will be on as they were in this power supply condition when FET 10 was switched off, and again transistors 33 and 48 will be switched off. With transistor 49 switched on, terminating region 16 will be at the same voltage as substrate connection 13. Again, this means that with transistor 42 on, the gate region 14 of transistor 10 will be negative with respect to terminating region 16 by the voltage on capacitor 30. Thus, transistor 10 again is switched on.

As before for transistor 33, with transistor 10 switched on, little current will flow in transistor 31 even though it is also switched on and so little charging will occur of capacitor 30. Again, there will be some discharging of capacitor 30 despite parasitic diodes 24 and 25 being reversed biased, this once more being through the parasitic resistances 26 and 27 in parallel with these diodes and control circuit 43.

As a result, there will not be any means for charging capacitor 30 to a voltage substantially in excess of the threshold voltage of transistor 10 during times when transistor 10 is switched on. As discussed with reference to Figure 6, the result is that capacitor 30 will only be charged when it has lost a sufficient voltage to have transistor 10 turn off sufficiently to raise the voltage dropped across it enough to cause a recharging of capacitor 30. This partial on condition of transistor 10 may well become the steady state condition for the circuit of Figure 11 (although it is possible FET 10 will turn off altogether for a half cycle), leading to less than maximum current flowing in the load 12 and causing a considerably larger power dissipation in transistor 10, which is undesirable.

There are at least two possible methods for avoiding this result, one of which is used in Figure 6 and involves locating the load as shown in Figure 6.

The disadvantage of that is the difficulty of having transistor 31 provided in a common substrate of a monolithic integrated circuit along with the other transistors. That is, transistor 31, or an actual diode if used rather than a transistor, must be provided so its substrate is isolated from the substrates of the other circuit components, i.e. from the substrate of the monolithic integrated circuit chip in which the other components are all formed if an integrated circuit version of Figure 6 circuit is to be used.

The other method available permits using load 12 as shown in Figure 11,so that transistor 31 can be integrated along with the other circuit components.

This method is implemented by use of the circuit components shown at the input of logic gate 46. The other input to logic gate 46 is, remember, the input for a control signal, a switch or otherwise to provide for external control of the circuit of Figure 11.

The circuit component shown connected to the first input of logic gate 11 forms a voltage level detector circuit for sensing the voltage level between the positive and negative sides of capacitor 30. This circuit function depends on use of an operational amplifier 45 and a bridge 44 including a voltage reference device (zener diode). Operational amplifier 45 has positive resistive feedback and is fed by the bridge 44. Also, the power connections for operational amplifier 45 and logic gate 46, although not shown, are supplied from across capacitor 30.

One arm of the bridge 44 places the positive operational amplifier input at a more or less fixed voltage below the voltage value on the positive side of capacitor 30 as long as the voltage across capacitor 30 exceeds the voltage reference value of the zener diode. The other arm of the bridge 44 senses the voltage across capacitor 30, and applies a proportion of this negative input to the operational amplifier 45.

Thus if the voyage on capacitor 30 falls below a value determined by the zener diode, the output of operational amplifier 45 switches from the voltage on the negative side of capacitor 30 to the voltage on the positive side of capacitor 30.

The switching of operational amplifier 45 will be quite rapid with voltage changes on capacitor 30, because of the positive feedback, which also provides hysteresis in the switching characteristic to reduce output oscillation.

Thus, insufficient voltage across capacitor 30 will result in the output voltage of operational amplifier 45 beig approximately equal to the voltage on the negative side of capacitor 30. Gate 46, being an AND gate, will then also have its output close to the voltage on the negative side of capacitor 30 thereby switching transistor 47 and 41 on while transistor 42 will be switched off. As indicated earlier, this will result in transistor 10 being switched off for some point in a half cycle of the output voltage of supply 11, thereby permitting capacitor 30 to be recharged by supply 11.

If this recharging of capacitor 30 takes place, the voltage on it will rise until the output of operational amplifier 45 changes, FET 10 will then again turn on if the signal on the input of logic gate 46 used for controlling the circuit of Figure 11 still so commands.

Hence, FET 10 will always be either switched fully on or switched fully off as comanded during operation of the circuit of Figure 11.

The situation may well arise where an assumption made and discussed in the operation of the circuit of Figure 11 does not hold. That is, the charging and discharging of the parasitic capacitances of FET 10 may not be accomplished fast enough with respect to the half cycles of the power supply 11. In these circumstances, further circuit improvements are desirable to obviate the detrimental effects on circuit operation which these undischarged capacitances would otherwise cause.

Figure 12 shows a circuit which has omitted from it the feature of providing constant polarity power for operating any control circuits to be used in the control of the field-effect transistor 10. The primary addition in the circuit of Figure 12 is the addition of a further bypass transistor 82 between the terminating region 15 of transistor 10 and gate region 14 thereof as shown. A switch 83 and a pair of transistors 80 and 81 have been added as shown to the basic portion of the circuit of Figure 12 to control the switching on and off of transistor 10.

To understand the operation of this circuit, consider first the two transistors 80 and 81 and switch 83.

Since their gates are both connected to the top end of the power supply 11, it follows that when the top end of the power supply is negative, both these transistors will be on, while when the top end of the power supply is positive, they will both be off. Hence if switch 83 connects the gate 14 to transistor 80 (which, as will be seen, if for FET 10 to be on), a negative voltage will be applied to gate 14 on negative half-cycles of the power supply; whereas if switch 83 connects the gate 14 to transistor 81, a zero voltage (relative to the bottom end of the power supply) will be applied to the gate 14 during negative half-cvcles of the power supply.

Next, consider transistors 48,49 and 82. When the top end of the power supply 11 is negative, transistor 49 will be on and transistor 48 off; and transistor 82 will be off like transistor 48. When the top end of the power supply 11 is positive, transistors 48 and 82 will be on and transistor 49 will be off.

Consider now what happens if switch 83 connects gate 14 to transistor 81. On the positive half-cycle of the top end of the power supply 11, transistor 82 is on and holds the gate 14 and source terminal 15 of transistor 10 at the same voltage, thus holding transistor 10 off. On the negative half-cycle of the power supply, transistor 81 is on and holds the gate 14 and source terminal 16 of transistor 10 at the same voltage, thus holding transistor 10 off.

On the negative half-cycle of supply 11, with transistor 10,48 and 82 being off, charging currents will flow to charge parasitic capacitances 9 and 28.

For at least some frequencies and kinds of waveforms from supply 11, charge will remain on these capacitances 9 and 28 when supply 11 reverses polarity so that the load side becomes positive.

Thus, the description of the behaviour of the circuit when the load means side of supply 11 becomes positive requires accounting for the stored charge on capacitances 9 and 28.

As the load side of supply 11 swings positive, transistors 48 and 82 will be switched on. Also, transistor 81 will turn off. Terminating region 15 of transistor 10 will serve as a source for that transistor, in being relatively positive with respect to terminating region 16, and so transistor 82 effectively shorts gate region 14 of transistor 10 to terminating region 15 to thereby keep transistor 10 off. However,this is not immediate as parasitic capacitance 9 must be discharged. So far a short time, the voltage across parasitic capacitance 9 is added to the voltage provided by supply 11 between gate region 14 and terminating region 16 of transistor 10.

Similarly, the voltage developed across capacitance 28 is added to the voltage provided by supply 11, reverse biasing parasitic diode 25 until parasitic capacitance 28 is discharged. The discharge of parasitic capacitance 28 is accomplished by both transistor 48 switching on and by transisto r 49 which is held on after the polarity reversal by the voltage across parasitic capacitance 28 until that capacitance has discharged sufficiently.

Hence, the breakdown charcteristics of transistor 10 between its gate region and its terminating region, and between its substrate and its terminating regions, need be only a little more that the peak voltage provided by supply 11 for many waveforms in the output voltage of supply 11 because of the discharging action of transistors 48,49 and 82.

However, higher breakdown voltages would be required oftransistor 10 for su pply 11 output voltage waveforms having characteristics rise times therein which are relatively short compared to the discharge times achieved by use of transistors 48,49 and 82.

Further, no charging of parasitic capacitances 22 and 23 from the channel of FET 10 to the gate 14 and substrate 13 occurs which would tend to switch on transistor 10, as the polarity of the voltage provided by supply 11 changes despite the intention of having transistor 10 switched off. The charge stored on capacitances 9 and 28 are prevented from having this same effect by being discharged. Finally, effective pnp bipolar transistor action between terminating regions 15 and 16 of transistor 10 is prevented by transistors 48 and 49 carrying current that would otherwise flow through parasitic diodes 24 and 25.

Of course, in this second and succeeding supply 11 polarity condition in which the load side thereof is positive, parasitic capacitances 19,8 and 29 between the terminal 16 and the gate 14 and substrate 13 of FET 10 will charge, just as parasitic capacitances 9 and 28 were charged during the previous half-cycle.

Thus on the next following half-cycle, similar discharging of capacitances 8 and 29 will occur.

Consider now having switch 83 connect transistor 80 to gate region 14 of transistor 10 during a half-cycle in which the load side of supply 11 is positive. In this situation, transistor 80 is switched off. This changeover of switch 83 thus has no effect, as transistor 81 was also off. However, when the load side of supply 11 goes negative, transistor 80 will be switched on and transistor 82 switched off. As a result, gate region 14 of transistor 10 is effectively shorted to the negative side of supply 11 by transistor 80, and transistor 10 will then be switched on. With transistor 10 switched on sufficiently so that only a very low voltage dropped between terminating regions 15 and 16, the operation of transistors 48 and 49 is of relatively little significance since they are effectively shorted out by transistor 10.On the other hand, in applications where there is a substantial voltage developed between terminating regions 15 and 16 despite transistor 10 being switched on, transistors 48 and 49 will still serve to discharge parasitic capacitances to thereby continue proper circuit operation. Of course, when transistor 10 is on, power is transferred from supply 11 to load means 12.

Of particular importance for the next half-cycle to come of supply 11, the switching on of transistor 10 leads to parasitic capacitance 22 being charged through transistor 80, such as in the circuit of Figure 8. On that next half-cycle, the accumulated charge on parasitic capacitance 22 will hold transistor 10 on.

Note that transistor 10, once on, cannot be switched off during times when the load side of supply 11 is positive by changing switch 83 from transistor 80 to transistor 81. This is because such a change still does not provide a discharge for capacitance 8,9 and 22 since transistor 81 will be off.

As is evident, the time duration rquired to discharge parasitic capacitances 8,9 and 22 via leakage paths to a point sufficient to cause transistor 10 to turn off is the only significant factor limiting how long the on state of this transistor can be maintained when the load side of supply 11 is positive. For ordinary device structures this duration will typically be hours. External capacitance could be added to increase this time duration as could other kinds of energy storage means. There is no time limit to keeping transistor 10 on in the opposite output voltage polarity condition nor is there any time limit in the off state.

The substrates for all of the transistors shown in Figure 12 can be connected in common without altering the operation of the Figure 12 circuit. As a result, all the field-effect transistors can be provided in a monolithic integrated circuit chip on a common substrate. Further, transistor 82 could be connected between substrate 13 and gate 14 of transistor 10 instead of between gate 14andterminating region 15.

Note that field-effect transistor types could be mixed in a circuit of the Figure 12 type with the primary power transistor control field-effect transistor, transistor 10, being either an n-channel or a p-channel FET and one of more of the other bypass or control field-effect transistors being of the opposite kind. For instance, the terminating regions of transistor 82 could be interchanged with that transistor being an n-channel field-effect transistor rather than the p-channel transistor shown. Similar kinds of changes could be made for some of the other transistors shown in Figure 12, with some additional circuit components required for best operation in at least some instances.

It is also possible to replace the transistors 48 and 49 of the circuit of Figure 12 by resistors, which can provide some of the same functions in that they also provide discharge paths for parasitic capacitances 28 and 29. To accomplish this, the resistances must be substantially less than the resistance of parasitic resistances shunting the parasitic capacitances. On the other hand, these resistors must have considerably larger resistances than the impedance of the load 12 if transistor 10 is to retain full control over power transfer from supply 11 to load 12. Otherwise substantial power dissipation will occur continually in load 12, and substantial power will also be dissipated in the resistors when transistor 10 is off.

However, such resistors cannot provide nearly as good a shunt function across the junctions of parasitic diodes 24 and 25 as do transistors, because the transistors can be switched between very low and very high. Thus, the supply frequency would have to be kept low enough to prevent any parasitic pnp transistor action between the terminating regions 15 and 16 of transistor 10.

It would also be possible to have resistors connected in parallel with the transistors 48 and 49.

It will be realized, in comparing the circuits of Figures 8 and 12, that the transistors 48 and 49 shunting the parasitic diodes 24 and 25 act to some extent to duplicate and substitute for the effects of these parasitic diodes, in charging the parasitic capacitance 22 and in maintaining the voltage of the right-hand side of this capacitance at the proper level relative to the two channel terminating regions 15 and 16 of transistor 10.

A further variation of the circuit of Figure 12 is achieved by using a depletion mode transistor in place of transistor 10. This requires a battery to be connected between the substrate point 13 and the junction of the two transistors 48 and 49 so as to keep the voltage of substrate point 13 positive relative to this junction point.

It will of course be realized that the transistor 82 can be added to the circuit of Figure 11. The active switching, in the Figure 11 circuit, of gate region 14 of transistor 10 to either the transistor 10 substrate or to the negative voltage on capacitor 30 eliminates the need to depend on charging gate capacitance to keep transistor 10 on when the load side of supply 11 is positive. This active switching also would eliminate the function of transistor 82 if the voltage across capacitor 30 were always sufficient to operate the control circuit 43. However, at circuit operating start-up and at times when the voltage on capacitor 30 drops low enough to require recharge of capacitor 30, transistor 82 ensures that transistor 10 is off so capacitor 30 can be charged quickly and fully.

Figure 13 shows an elaboration of the control of Figure 12 which is capaable of providing constant polarity power for the control circuit, like the circuits of Figures 6 and 11 but without use of an energy storage meansforthis purpose. It will be recalled that in the circuit of Figure 12, transistors 80 and 81 were only effective during half-cycles when the power suppy was negative at the load end. For transistor 10 to be on, transistor 80 connected gate 14 to the top end of supply 11; for transistor 10 to be off, transistor 81 connected gate 14 to the bottom end of supply 11. In the circuit of Figure 13, a diode 90 ensures that the control circuit 97 is operative only when the load side of supply 11 is negative.A bridge circuit 99 includes a variable resistor 98 which senses some condition to be controlled by the load 12, and drives an operational amplifier 96 which controls two transistors 94 and 92, transistor 94 controlling a transistor 91. Depending on the resistance of sensor 98, so transistor 91 will be on and transistor 92 off or vice versa during negative half-cycle, of the supply ll,so connecting gate 14 of transistor 10 to one or other side of the supply 11 during such half-cycles.

When the load side of supply 11 becomes positive, power is removed from the control circuit 97 by diode 90 insofar as being supplied directly by supply 11 because diodes 90 and 95 become reverse biased.

Diode 95 prevents transistor 92 from switching on and thereby causing gate region 14 oftransistor 10 to be effectively shorted to the negative side of supply 11, leading to switching on transistor 10. If diode 95 were absent the gate of transistor 92 might be forced negative with respect to its junction with gate 14, serving as a source, by current leakage paths across or around gate region of transistor 94.

Diode 95 prevents any such leakage currents. Further, another kind of input control circuit operating transistor 94, or even the circuit within operational amplifier 96, may provide an impedance between gate region of transistor 94 and the top end of diode 95. In such circumstances, the absence of diode 95 would certainly lead to switching on transistor 10.

This function of diode 95 could equally be performed by including a diode 93 where shown by dashed lines in Figure 13. Actualiy, either diode 95 or diode 93 could be eliminated entirely if the on resistance of transistor 82 were sufficiently low and if there were no substantial leakage paths across or around transistors 91,92 and 94, and if there were no substantial circuit impedances or leakage paths occurring between the output of operation amplifier 96 and the terminating region of transistor 94 or the bottom end of supply 11.

Transistors 91,92 and 94, as well as the sensing circuit associated with operational amplifier 96, are operated only when the load side of supply means 11 is relatively negative because of diode 90. This prevents transistor 10 from being switched off at those times it is intended to be on and the top end of supply 11 is positive. In the absence of diode 90 in these circumstances, transistor 91 would switch on and begin to discharge parasitic capacitance 22, leading to transistor 10 being switched off. Diode 90 may have a reverse bias voltage thereon equal to twice the peak voltage being provided by supply 11 because of stored charge in capacitance 22.

Note that use can be made of the pulsed, constant polarity voltage appearing between the cathode of diode 95 and the anode of diode 90 when the load side of supply 11 is relatively negative to provide power for other electronic circuits possibly provided in the same monolithic integrated circuit chip in which the circuit of Figure 13 is provided. That is, transistors 10,48,49,82,91,92 and 94, could all be provided in the same monolithic integrated circuit chip along with diodes 90 and 95.(which may be transistors connected to behave as diodes). Additionally, the sensing circuit associated with operational amplifier 96 can also be provided in the same monolithic integrated circuit chip, although often sensor 98 would be provided as an external component with respect to the chip.Of course, the functions of the sensing circuit and the control transistors could be provided by other kinds of components such as bipolar transistors in some other circuit electrically energized by the constant polarity pulsed voltage provided in the circuit of Figure 13.

Operational amplifier 96 is powered by the pulsed, constant polarity voltage appearing between diodes 90 and 95, although these power connections are not shown.

In the circuit of Figure 12, the parasitic capacitances 28 and 29 in parallel with the parasitic diodes 24 and 25 were shunted by the two FET's 48 and 49.

In the circuit of Figure 13, these two shunting FET's have been replaced by two resistors 48' and 49', which serve the same purpose, although less effectively since the resistances of these two resistors desired when the corresponding shunting FET would be off and the very low resistance desired when the corresponding shunting FETwould be on.

The resistances of resistors 48' and 49' must also be substantially lower than the parasitic resistances in parallel with the diodes 24 and 25, for these resistors to have a substantial effect. The frequency of the supply 11 at which parasitic pnp transistor action between the terminating regions 15 and 16 of transistor 10 will occur is considerably reduced when resistors 48' and 49' are used instead of transistors 48 and 49.

Claims (16)

1. An AC switching circuit comprising an AC source, a load, and a switch comprising a main FET (field-effect transistor) all connected in series, a pair of diodes connected between the two channel terminals of the main FET and a bias reference point and correspondingly poled towards the bias reference point, and a control circuit connected between the bias reference point and the gate of the main FET.

2. A circuit according to Claim 1, wherein the diodes are formed by the parasitic diodes of the FET.

3. A circuit according to either previous claim, wherein the main FET has two shunting FET's connected in parallel with its parasitic diodes, each of the two shunting FET's having its gate connected to the opposite channel terminal of the main FET.

4. A circuit according to any previous claim, wherein the control circuit includes a capacitor and a rectifying diode connected between the bias reference point and one side of the load or AC source, and switching means which connect the gate of the FET to one or other side of the capacitor.

5. A circuit according to Claim 4, including a second rectifying diode connected between the junction of the capacitor and first rectifying diode and the other side of the AC source.

6. A circuit according to either of Claim 4 and S, wherein the or each rectifying diode is formed by an FET.

7. A circuit according to any one of Claims 4 to 6, wherein the switching means comprise a pair of control FET's connected in series across the capacitor and with their junction connected to the gate of the main FET, and a control circuit energized from the capacitor and controlling the two control FET's so that one is on and the other is off.

8. A circuit according to any one of Claims 4to 7, wherein the control circuit includes a circuit sensitive to the voltage on the capacitor to turn the main FET off if the voltage on the capacitor falls below a predetermined value.

9. A circuit according to any one of Claims 1 to 3, wherein the control circuit includes a switching FET having its channel connected to the bias reference point, one channel terminal connected to the gate of the main FET, its gate connected to one side of the load or AC supply, and a control signal applied to its other channel terminal.

10. A circuit according to Claim 9, wherein the control circuit includes two switching FET's, each having one channel terminal connected to a respective side of the AC supply and both having their gates connected to the same side of the AC supply, and a switch which connects the remaining channel terminal of either switching FET to the gate of the main FET.

11. A circuit according to Claim 9, wherein the control circuit includes two switching FET's and a diode connected in series across the AC supply, with the junction of the two switching FET's being connected to the gate of the main FET, and switching means connected across the two switching FET's which switches one of the switching FET's on and the other off.

12. A circuit according to any one of Claims 9 to 11, wherein the main FET has a shunting FET connected between the gate of the main FET and the channel terminal of the main FET on the same side of the AC supply as the connection of the gates of the two switching transistors, or the channel of the main FET, and having its gate connected to the other side of the AC supply.

13. A circuit according to Claim 1, wherein the control circuit comprises a resistive path and, in parallel therewith, a path including a bias voltage source and a switch.

14. A circuit according to Claim 13, wherein the switch is a further FET.

15. A circuit according to any previous claim, wherein all the FET's are formed in a single semiconductor chip.

16. A circuit according to any one of Claims 1 to 6 and 13, wherein a plurality of main FET'sare connected in series.