GB2039153A - Multilayer electrical circuit boards - Google Patents

Multilayer electrical circuit boards Download PDF

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Publication number
GB2039153A
GB2039153A GB7900047A GB7900047A GB2039153A GB 2039153 A GB2039153 A GB 2039153A GB 7900047 A GB7900047 A GB 7900047A GB 7900047 A GB7900047 A GB 7900047A GB 2039153 A GB2039153 A GB 2039153A
Authority
GB
United Kingdom
Prior art keywords
electrical circuit
circuit board
board
conductive
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB7900047A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
British Broadcasting Corp
Original Assignee
British Broadcasting Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by British Broadcasting Corp filed Critical British Broadcasting Corp
Priority to GB7900047A priority Critical patent/GB2039153A/en
Publication of GB2039153A publication Critical patent/GB2039153A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0286Programmable, customizable or modifiable circuits
    • H05K1/0287Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09609Via grid, i.e. two-dimensional array of vias or holes in a single plane
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09945Universal aspects, e.g. universal inner layers or via grid, or anisotropic interposer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/429Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A multilayer, preferably three- layer, printed circuit board 10 has its central conductive layer 14 apertured with a regular array of apertures 18. Through connections can be made as desired which either do (as Y) or do not (as X) contact the central conductor 14. In an electrical circuit the central layer can be used as the ground plane. <IMAGE>

Description

SPECIFICATION Multilayer electrical circuit boards This invention relates to electrical circuit boards of the type comprising a conductive layer or film fixed to a planar insulating base.
Circuits connections are usually formed on the boards by means of a printing process and for this reason they are almost invariably referred to as "printed circuit boards". The invention is particularly concerned with multilayer boards, that is to say boards in which there are three or more conductive layers separated by insulating layers. The invention is also concerned with the manner of use of such boards.
As attempts are made to use higher and higher densities of interconnections on conventional double-sided printed circuit boards, it becomes increasingly difficult to allow sufficient surface area of conductor, such as copper, on either side to form an effective earth or ground plane. The requirements for this are well known in printed circuit design.
There is therefore a tendency to think in terms of yet a third layer of conductor sandwiched between insulating layers which could be used for this purpose. However multilayer boards are expensive, because special'equipment is required for their manufacture, and the internal layer or layers have to be printed and etched before final lamination of the board. Thus every application requires the manufacture of a special board. Furthermore, once the board is made up, with the ground plane within the laminate, these become inviolate and cannot be modified or altered without complete reconstruction.
Precisely similar reasoning applies in. respect of power planes.
This invention provides a multilayer electrical circuit board, comprising at least three conductive layers separated by insulating layers, in which the or at least one of the internal conductive layers which is sandwiched between insulating layers consists over at least a substantial portion of the board of a substantially continuous conductor with a regularly spaced array of apertures.
The circuit board thus provided can be used as a general purpose board. Connections can be made through the board either with or without contacting the said internal layer, by selectively going through the board either in# an area where the internal conductor exists, or through one of the apertures. The apertures are large enough to allow the through-connection, such as by plated-through holes or through-pins, without danger of contacting the internal layer.
The internal layer can then very conveniently form a ground plane in the final circuit, with at least half and preferably more than two-thirds of its surface over the said portion conductive.
The invention will now be described in more detail by way of example with reference to the drawing, in which: Figure 1 is a sectional view through a portion of a printed circuit board embodying the invention; and Figure 2 is a plan view of the internal conductive layer in the board.
The board 10 shown in Fig. 1 comprises two insulating layers 12 and three conductive layers. One conductive layer 14 is sandwiched between the two insulating layers 12, and the other two layers 16 are on the outer surfaces of the insulating layers 12.
The outer conductive layers 16 are continuous, but the inner layer 14 is apertured as shown in Fig. 2 with a regular array of circular holes 18 across its surface. As shown, the holes occupy approximately 25% of the surface area, so that the conductor occupies 75%.
Two sorts of through connections are now possible. If the connection is made through one of the holes 18, as shown as X, then the two outer layers 16 will be connected together. If the connection is made elsewhere, as shown at Y, then all three layers 14 and 16 will be connected together. If it only desired to connect one of the outer layers 16 to the inner layer 14, then an island is left round the connection with the other outer layer.
In developing circuits for use with this form of board it is of course necessary to ensure that any through connections are at the correct pitch or multiple thereof and are correctly aligned on the array of holes 18. Likewise connections to the central layer must be correctly positioned. To assist in correctly locating the board, an indication of where the aperture pattern is within the board can be provided by printing this positional information on either or both of the two outer surfaces of the laminate. Alternatively, two widely separated holes could be made through the laminate, these holes each conveniently coinciding with the centre of a particular aperture.
It is possible to make any desired number of through connections, and furthermore to alter the connections subsequently without having to open the laminate to reach the central conductive layer 14.
The construction is particularly suitable for use with the central plane as a ground or earth plane, as indicated at 20 on Fig. 1. The outer surfaces of the board may now both be entirely devoted to circuit interconnections.
Part of the surface area of the inner conductive layer 14 could include lines or strips for power connections, for example, to a predetermined arrangement.
The array of holes 18, which is in a collander or sieve pattern, in one example had holes at a pitch of 0.1 inch (approx. 2.5 mm). The hoses are of sufficient size to clear any thr < #ugh-pins or plated-through holes which may be made through them. The conductive layers 14 and 16 will usually be copper, and the insulating layers 12 can be of any oF the currently-used materials, for example a fibre-epoxide resin material.
The three-layered board illustrated would be of real practical use to research and development concerns, and could usefully form a standard products. It can be processed by the user with the same equipment as a normal double-sided board.
It would be possible to extend the concept to the provision of for example a four-layered board which provided in addition an internal power plane.

Claims (7)

1. A multilayer electrical circuit board, comprising at least three conductive layers separated by insulating layers, in which the or at least one of the internal conductive layers which is sandwiched between insulating layers consists over at least a substantial portion of the board of a substantially continuous conductor with a regularly spaced array of apertures.
2. An electrical circuit board accusing to Claim 1, wherein the said internal layer is conductive over at least half of the area of the said portions of the board.
3. An electrical circuit board according to Claim 1, wherein the said internal layer is conductive over at least two-thirds of the area of the said portion of the board.
4. An electrical circuit board according to any preceding Claim, including externally visible position markers for indicating the position of the aperture array.
5. An electrical circuit board according to any preceding Claim, wherein there are three conductive layers and two insulating layers.
6. A multilayer electrical circuit board substantially as herein described with reference to the drawings.
7. An electrical circuit formed on a circuit board in accordance with any of the preceding Claims, in which the said internal layer constitutes a power or ground plane for the circuit.
GB7900047A 1979-01-02 1979-01-02 Multilayer electrical circuit boards Withdrawn GB2039153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB7900047A GB2039153A (en) 1979-01-02 1979-01-02 Multilayer electrical circuit boards

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB7900047A GB2039153A (en) 1979-01-02 1979-01-02 Multilayer electrical circuit boards

Publications (1)

Publication Number Publication Date
GB2039153A true GB2039153A (en) 1980-07-30

Family

ID=10502262

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7900047A Withdrawn GB2039153A (en) 1979-01-02 1979-01-02 Multilayer electrical circuit boards

Country Status (1)

Country Link
GB (1) GB2039153A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4524239A (en) * 1981-09-02 1985-06-18 Francois Rouge Multi-layer electric circuit board and blanks therefor
US4973799A (en) * 1988-09-02 1990-11-27 Konica Corporation Printed circuit board for use with an image forming apparatus
US5365407A (en) * 1992-02-07 1994-11-15 Sony Corporation DC power supply device with printed-circuit board having ground pattern
EP1507448A1 (en) * 2003-08-12 2005-02-16 Elmicron AG Base material, substrate and connection module

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4524239A (en) * 1981-09-02 1985-06-18 Francois Rouge Multi-layer electric circuit board and blanks therefor
US4973799A (en) * 1988-09-02 1990-11-27 Konica Corporation Printed circuit board for use with an image forming apparatus
US5365407A (en) * 1992-02-07 1994-11-15 Sony Corporation DC power supply device with printed-circuit board having ground pattern
EP1507448A1 (en) * 2003-08-12 2005-02-16 Elmicron AG Base material, substrate and connection module

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)