GB2036479A

GB2036479A - Improvements in or Relating to Devices for Determining Steady- State Values of Analogue Signals

Info

Publication number: GB2036479A
Application number: GB7847628A
Authority: GB
Original assignee: INST KIBERNETIKI AKAD NAUK UKRAINSKA SSR; INST KIBERNETIKI AN
Current assignee: INST KIBERNETIKI AKAD NAUK UKRAINSKA SSR; INST KIBERNETIKI AN
Priority date: 1978-12-07
Filing date: 1978-12-07
Publication date: 1980-06-25
Also published as: DE2853161A1; FR2444373B1; FR2444373A1; DE2853161C2; GB2036479B

Abstract

A device for determining the steady-state value of an analogue signal comprises an analogue-to- digital converter 1 which produces first and second pulses corresponding to positive and negative increments in the analogue signal. First and second counters 5 and 4 count both the first and second pulses but in different directions, each being inhibited in counting substantially at zero count and reset a timer 8 upon reaching a predetermined count. An up/down counter 9 counts up and down the first and second pulses, respectively, and a display 10 displays the contents of the up/down counter 9 when the steady-state value has been determined. When the timer 8 reaches a preset time without having been reset, it stops the first and second counters 5 and 4 and the up/down counter 9 and starts each of the first and second counters counting down clock pulses until the contents thereof reaches zero. If the second counter 4 reaches zero before the first counter 5, the up/down counter 9 counts up half the clock pulses between second and first counters reaching zero. If the first counter 5 reaches zero before the second counter 4, the up/down counter 9 counts down half the clock pulses between the first and second counters reaching zero. <IMAGE>

Description

SPECIFICATION Improvements in or Relating to Devices for Determining Steady-state Values of Analogue Signals The present invention relates to devices for determining steady-states value of analogue signals.

The present invention may be employed for preliminary processing of information received from sensors during production processes, for instance, for digital representation of the molten steel temperature measured by means of an immersion thermocouple.

In preliminary processing of information there exists a problem of estimating against a noise background, a steady-state value with a final result to be represented in a digital form.

A problem of such a type exists in measuring the temperature of molten metal, for example steel, by means of a temperature sensor which is immersed in the melt for a short period of time, when it is required to determine in a digital form the signal value received from the sensor, which is set after termination of a transient process caused by the drift of the temperature sensor.

Known in the art is a digital computing device designed for checking parameters of a molten metal.

This known device can be employed for determining in a digital form a steady-state value of the analogue signal, for example, for determining a molten metal temperature measured by means of an immersion thermocouple.

Said device comprises an analogue-to-digital converter for converting an analogue signal into a numerical pulse code, having an output for code pulses corresponding to a positive increment of the analogue signal and an output for code pulses corresponding to a negative increment of the analogue signal, a clock pulse generator, a synchronization unit for distribution in time of code and clock pulses, connected to the outputs of the analogue-to-digital converter and to an output of the clock pulse generator. For determining local increments of the analogue signal there are provided first and second threshold counters, digit outputs of which are connected to inputs of zero state decoders of the threshold counters, outputs of the decoders being connected to subtract count blocking inputs of the respective threshold counters.The device also comprises a time interval discriminator designed for selecting time intervals between sequence instants of time when a local increment of the analogue signal assumes a predetermined value.

Initial setting inputs of the time interval discriminator are connected to overflow outputs of the threshold counters. A synchronized clock pulse output of the synchronization unit is electrically connected to a count input of the time interval discriminator. Synchronized code pulse outputs of the synchronization unit are electrically connected to the threshold counters and to a reversible counter designed for generating a parallel code of result. A register connected with its information input to digit outputs of the reversible counter, and with its control input to the output of the time interval discriminator provides for a storage of the computed result which is displayed in a digital form in a digital display unit.

During the process of determining temperature of molten metal, in the reversible counter there is formed a code proportional to the current readings of the analogue signal received from the temperature sensor. If positive or negative increments of the signal exceed a predetermined threshold EO of non-sensitivity (hysteresis) to the signal deviations from its steady-state value, caused by interference effects, there appear pulses at the overflow outputs of the threshold counters. Each such pulse sets into the initial state the time interval discriminator which counts up a number of synchronized clock pulses.If within a predetermined time interval TO set with the aid of the time interval discriminator, an increment of the signal does not exceed the predetermined threshold EO, there appears a signal at the output of the time interval discriminator, which indicates that the analogue signal has assumed its steady-state value. The parallel code contained in this instant of time in the reversible counter enables said ready-state value of the analogue signal to be estimated. The signal, which is fed to the control input of the register from the output of the time interval discriminator, contains information indicative of the steady-state value of the analogue signal.

It should be noted that the parallel code fed to the register may vary from the code of the steadystate value of the analogue signal by a value of +0.5 EO. Thus, the maximum error in determining a steady-state value of the analogue signal with the aid of the above device cannot be less than 0.5ego.

With the increase of the noise level the nonsensitivity threshold EO has to be increased, which brings about an increase in the maximum error in determining the steady-state value of the analogue signal. Thus, an accuracy in determining the steady-state value of the analogue signal by means of the above device considerably depends on the noise level.

According to one aspect of the present invention, there is provided a digital device for determining the steady-state value of an analogue signal, comprising: analogue-to-digital converter for converting an analogue signal into a numerical pulse code, having a first output for code pulses corresponding to a positive increment of the analogue signal and a second output for code pulses corresponding to a negative increment of the analogue signal; a clock pulse generator; a synchronization unit for distribution in time of code and clock pulses having first and second inputs connected to the first and second outputs respectively of the analogue-to-digital converter, a third input connected to the output of the clock pulse generator, a first output for synchronized code pulses corresponding to a positive increment of the analogue signal, a second output for synchronized code pulses corresponding to a negative increment of the analogue signal and an output for synchronized clock pulses; three inverters; seven AND gates; a time interval discriminator for selecting intervals between two sequence instants of time when a local increment of the analogue signal assumes a #redetermined value, said discriminator having a count input, first and second initial setting inputs and an information output connected to first inputs of the first, second, third and fourth AND gates and through the first inverter to the first input of the fifth AND gate; first and second threshold counters for determining local increments of the analogue signal, each having an add input, a substract input, an additional subtract input, a subtract count blocking input, an overflow output and digit outputs; zero state decoders for the first and second threshold counters whose inputs are connected to the digit outputs of the respective threshold counters, the outputs of the decoders being connected to the subtract count blocking inputs of the respective threshold counters, and the overflow outputs of the first and second threshold counters being connected to the first and second initial setting inputs, respectively, of the time interval disciminator, respectively; a reversible counter for generating a parallel code corresponding to the analogue signal steady-state value having an add input, a subtract input and digit outputs; a digital display unit for displaying the calculated result, having an information input electrically connected to the digit outputs of the reversible counter, and a control input; and a frequency halver having an input connected to the output for synchronized clock pulses of the synchronization unit, and an output, the output for synchronized clock pulses of the synchronization unit also being connected to the second inputs of the first and fifth AND gates, the outputs for synchronized code pulses of the synchronization unit corresponding to positive and negative increments of the analogue signal being connected to the first inputs of the sixth and the seventh AND gates, respectively, second inputs of which are connected to the first input of the fifth AND gate, second inputs of the second and the third AND gates being connected to the frequency halver output; the output of the zero state decoder of the first threshold counter being connected to a third input of the third AND gate, to a second input of the fourth AND gate and through the second inverter to a third input of the second AND gate, the output of the zero state decoder of the second threshold counter being connected to a fourth input of the second AND gate, to a third input of the fourth AND gate, and through the third inverter to a fourth input of the third AND gate, an output of the first AND gate being connected to the additional subtract inputs of the first and second threshold counters outputs of the second and the third AND gates being connected to the additional subtract and add inputs, respectively, of the reversible counter, an output of the fourth AND gate being connected to the control input of the digital display unit, an output of the fifth AND gate being connected to the count input of the time interval discriminator, an output of the sixth AND gate being connected to the add inputs of the first threshold counter and of the reversible counter and to the subtract input of the second threshold counter, and an output of the seventh AND gate being connected to the subtract inputs of the first threshold counter and of the reversible counter and to the add input of the second threshold counter.

According to another aspect of the invention, there is provided a device for determining the steady-state value of an analogue signal, comprising an analogue-to-digital converter arranged to produce first pulses corresponding to positive increments in the analogue signal and second pulses corresponding to negative increments in the analogue signal, a first counter arranged to count the first pulses, a second counter arranged to count the second pulses, a timer arranged to be reset when the first and second counter reaches a predetermined count, an up/down counter arranged to count up the first pulses and to count down the second pulses, a clock pulse generator, and display means arranged to display the contents of the up/down counter, the timer being arranged, upon reading a preset time without having been reset, to prevent the first and second counters and the up/down counter from counting the first and second pulses, and to cause the first and second counters count down until their contents are zero, the up/down counter being arranged, if the second counter reaches zero before the first counter, to count up substantially half the clock pulses between the second counter reading zero and the first counter reaching zero and, if the first counter reaches zero before the second counter, to count down substantially half the clock pulses between the first counter reaching zero and the first counter reaching zero.

The invention will be further described, by way of example, with reference to the accompanying drawings wherein: Fig. 1 is a block diagram of a preferred digital device for determining the steady-state value of an analogue signal; Fig. 2 illustrates a representative portion of the analogue signal variation curve for the case when the point of the representative portion of the curve, at which the time interval discriminator is triggered, is located on the midline between the maximum and minimum values of the analogue signal; Fig. 3 illustrates substantially the same portion of curve as in Fig. 2 but for the case when the point of the representative portion of the curve, at which the time interval discriminator is triggered, is located above the midline between the maximum and minimum values of the analogue signal; and Fig. 4 illustrates substantially the same portion of curve as in Fig. 2 but for the case when the point of the representative portion of the curve, at which the time interval discriminator is triggered, is located below the midline between the maximum and minimum values of the analogue signal.

A digital device for determining a steady-state value of an analogue signal as illustrated in Fig. 1 comprises an analogue-to-digital converter 1 for converting an analogue signal into a numerical pulse code, a clock pulse generator 2, a synchronization unit 3 for distribution in time of code and clock pulses, threshold counters 4 and 5 a decoder 6 for decoding the zero-state of the threshold counter 4, a decoder 7 for decoding the zero-state of the threshold counter 5, a time interval discriminator 8, a reversible (up/down) counter 9, a digital display unit 10, three NOT circuits (inverters) 11, 12, 13, seven AND gates 14,15,16,17,18, 19, 20 and frequency halver 21.

The converter 1 for converting an analogue signal into a numerical pulse code has an input 22, an output 23 for transmitting code pulses corresponding to a positive increment of the analogue signal, and an output 24 for transmitting code pulses corresponding to a negative increment of the analogue signal. The outputs 23 and 24 are connected to the synchronization unit 3. An output 25 of the clock pulse generator 2 is also connected to the synchronization unit 3. An output 26 of synchronized clock pulses of the synchronization unit 3 is connected to an input of the AND gate 14, to an input of the AND gate 15 and to an input of the frequency halver 21. An output 27 of the synchronization unit 3, intended for transmitting synchronized code pulses corresponding to a positive increment of the analogue signal at the input 22 of the converter 1, is connected to an input of the AND gate 19.An output 28 of the synchronization unit 3, intended for transmitting synchronized code pulses corresponding to a negative increment of the analogue signal at the input 22 of the converter 1, is connected to an input of the AND gate 20.

Inputs 29, 30 and 31 of the respective AND gates 20, 1 9 and 14 are connected together. An output 32 of the AND gate 14 is connected to a count input of the time interval discriminator 8. An output 33 of the AND gate 15 is connected to additional subtract inputs of the threshold counters 4, 5. An output 34 of the AND gate 19 is connected to an add input of the threshold counter 5, to a subtract input of the threshold counter 4 and to an add input of the reversible counter 9. An output 35 of the AND gate 20 is connected to a subtract input of the threshold counter 5, to an add input of the threshold counter 4 and to a subtract input of the reversible counter 9. Digit outputs 36 of the threshold counter 4 are connected to the inputs of the decoder 6.An overflow output of the threshold counter 4 is connected to an initial setting input 37 of the time interval discriminator 8. An output of the decoder 6 is connected to subtract count blocking input 38 of the threshold counter 4, to an input 39 of the AND gate 1 6, to an input 40 of the inverter 13 and to an input 41 of the AND gate 18. Digit outputs 42 of the threshold counter 5 are connected to inputs of the decoder 7. An overflow output of the threshold counter 5 is connected to an initial setting input 43 of the time interval discriminator 8. An output of the decoder 7 is connected to a subtract count blocking input 44 of the threshold counter 5, to an input 45 of the inverter 12, to an input 46 of the AND gate 1 7 and to an input 47 of the AND gate 18.An information output of the time interval discriminator 8 is connected to an input 48 of the inverter 11 and to inputs 49, 50 and 51 of the AND gate 1 6, 1 7 and 18 respectively. An output of the inverter 11 is connected to the input 31 of AND gate 14, an output of the inverter 12 is connected to an input 52 of the AND gate 16 and an output of the inverter 13 is connected to an input 53 of the AND gate 1 7. An output of the frequency halver 21 is connected to inputs 54 and 55 of the AND gates 16 and 17, respectively.

An output 56 of the AND gate 1 6 is connected to an additional subtract input of the reversible counter 9 whereas an output 57 of the AND gate 17 is connected to an additional add input of the reversible counter 9. An output 58 of the AND gate 1 8 is connected to a control input of the digital display unit 1 0. Digit outputs 59 of the reversible counter 9 are connected to an information input of the digital display unit 10.

The threshold counters 4 and 5 are scaling circuits set to a scaling factor corresponding to a predetermined threshold EO of non-sensitivity to the signal deviations from a steady-state value, caused by interference.

The time interval discriminator 8 is a scaling circuit whose scaling factor corresponds to a duration of the predetermined time interval.

The foregoing digital device for determining the steady-state value of the analogue signal functions as follows. The analogue signal is fed to the input 22 of the converter 1. Depending on the increment sign of the analogue signal, code pulses are formed either at the output 23 or at the output 24 of the analogue-to-digital converter 1, the number of the code pulses being proportional to the increment of the analogue signal. The code pulses from the outputs 23 and 24 are fed to the first and second inputs of the synchronization unit 3, while to the third input of the synchronization unit 3 are fed clock pulses from the output 25 of the clock pulse generator 2. In the synchronization unit 3 the code and clock pulses are distributed in time. The synchronized code and clock pulses are formed at the outputs 26 and 27 and at the output 28, respectively, of the synchronization unit 3.

At the moment of starting the device, the time interval discriminator 8 is set in its initial state either with the initial setting key (not shown) or automatically, in response to which a blocking potential is formed at the information output of the time interval discriminator 8, which blocks the AND circuits 1 5, 16, 17 and 18 and opens, through the inverter 11, the AND gates 14, 1 9 and 20.

From the synchronization unit 3 the synchronized code pulses are fed, through the AND gates 19 and 20, either to the add input or to the subtract input of the reversible counter 9 to generate a parallel code of the analogue signal current value. The same code pulses are fed to the add and subtract inputs of the threshold counters 4 and 5. In this case, if an increment of the analogue signal is positive, the code pulses from the output 34 of the AND gate 19 are fed to the add input of the threshold counter 5 and the subtract input of the threshold counter 4. If the increment of the analogue signal is negative, the code pulses from the output 35 of the AND gate 20 are applied to the subtract input of the reversible counter 9, the subtract input of the threshold counter 5 and at the add input of the threshold counter 4.When the contents of the threshold counter 4 are zero, further subtract counting in the said counter is blocked by the 4* decoder 6. Similarly, when the contents of the threshold counter 5 are zero, further subtract counting in this counter is blocked by the decoder 7. Thus, the threshold counter 5 generates a code proportional to a local positive increment of the analogue signal relative to the local minimum of the variation curve of said signal, whereas threshold counter 4 generates a code proportional to a local negative increment of the analogue signal relative to the local maximum on the variation curve of said signal. If either of said local increments exceeds a predetermined threshold EO, at the overflow output of the respective threshold counter there is formed a pulse setting the time interval discriminator 8 in its initial state.

The count input of the time interval discriminator 8 is fed with synchronized clock pulses through the AND gate 14. A release voltage at the information output of the time interval discriminator 8 can be formed only if within a preset time interval EO said discriminator is not reset to its initial state by a pulse received from the overflow output of either of the threshold counters 4 or 5. Thus, as the analogue signal varies, the time interval discriminator 8 is set to its initial state each time when the increment of the analogue signal within a preset time interval TO exceeds value EO. When the analogue signal assumes it steady-state value, its negative and positive increments do not exceed the value EO.

As soon as the time interval TO calculated from the moment of the last initial resetting of the time interval discriminator 8 terminates at the information output of said discriminator there appears a release potential. In this case a blocking potential formed at the output of the inverter 11 blocks the AND gates 14, 19 and 20, which in turn blocks passage of the code pulses to the reversible counter 9 and to the threshold counters 4 and 5. Simultaneously, feeding the clock pulses to the count input of the time interval discriminator 8 ceases so that the release potential at the information output thereof is maintained until the next cycle determining the steady-state value of the analogue signal.Also, the permitting potential formed at the information output of the time interval discriminator 8 opens the AND gate 15, and the synchronized clock pulses from the output 26 of the synchronization unit 3, are fed through said AND gate 15, to the additional subtract inputs of the threshold counters 4 and 5.

If a value of the analogue signal, at which the reversible counter 9 and the threshold counters 4 and 5 have been blocked by a signal of the time interval discriminator 8, is found midway between the maximum and minimum values of the analogue signal on the representative portion of the curve representing a time dependence of the analogue signal value (Fig. 2), the contents AX1 of the threshold counter 5 at the moment of blocking are equal to the contents AX2 of the threshold counter 4. Clock pulses, which are fed through the AND gate 15 to the additional subtract inputs of the threshold counters 4 and 5, cause the contents of said threshold counters to vary.As soon as zero is present in said threshold counters, the zero-state decoders 6 and 7 of the threshold counters 4 and 5 block the subtract inputs of said counters simultaneously applying release potentials to the inputs 41 and 47 of the AND gate 18. In so far as the AND gate 18 is also fed through its input 51 with the release potential from the information output of the time interval discriminator 8, at its output 58 there is formed a release potential which, being fed to the control input of the digital display unit 1 0, causes transmission of information from the reversible counter 9 to said digital display unit 10 wherein a steady-state value of the analogue signal is numerically displayed corresponding to the average between the maximum and minimum values of the analogue signal on said representative portion of the variation curve of said analogue signal.

If the point on the variation curve (Fig.3) of the analogue signal, at which the reversible counter 9 has been blocked by a potential at the information output of the time interval discriminator 8, is located above the midline between the maximum and minimum values of the analogue signal on a representative portion of the curve, the contents AX, of the threshold counter 5 at the moment of signal formation at the information output of the time interval discriminator 8 will be greater than the contents AX2 of the threshold counter 4, and the value AX'O of the blocking point deviation relative to the midline between the maximum and minimum values of the analogue signal of the representative portion of the curve may be determined by relation

Synchronized clock pulses fed from the output 33 of the AND gate 1 5 to the additional subtract inputs of the threshold counters 4 and 5 cause the contents of said threshold counters 4 and 5 to vary in a manner similar to that described above.

However zero is first present in the threshold counter 4 while in the threshold counter 5 there is a code correspond to the difference between values AX1 and AX2. At the moment when a zero appears at the output of the threshold counter 4, the zero-state decoder 6 thereof blocks the threshold counter 4 and sends release potentials to the AND gates 16 and 18. The zero-state decoder 7 of the threshold counter 5 sends through the inverter 12 release potential to the input 52 of the AND gate 16.In so far as at the input 49 of the AND gate 16 there also exists a release potential formed at the information output of the time interval discriminator 8, synchronized clock pulses, whose frequency is divided in two by the frequency halver 21, are fed through the AND gate 16 to the additional subtract input of the reversible counter 9, said pulses being fed to said additional subtract input of the reversible counter 9 9 until a zero is formed in the threshold counter 5 as in the threshold counter 4. At this time, a release potential at the output of the decoder 7 passing through the inverter 12 blocks the AND gate 16.The number of pulses being fed to the reversible counter 9 corresponds to the value AXOT determined by the expression (1), which enables the contents of the reversible counter 9 to be corrected automatically to a required value corresponding to the average between the maximum and minimum values of the analogue signal on the representative portion of the curve.

As soon as a zero appears in the threshold counter 5 the AND gate 18 is released so as to transmit information indicative of the steady-state value of the analogue signal to the digital display unit 10.

In case the point, at which the reversible counter 9 has been blocked by a potential at the information output of the time interval discriminator 8, is located below the midline between the maximum and minimum values of the analogue signal on the representative portion of the curve (Fig. 4), the contents AX1 of the threshold counter 5 at the moment of signal formation at the information output of the time interval discriminator 8 will be smaller than the contents AX2 of the threshold counter 4.The value AXO/ of the blocking point deviation from the midline between the maximum and minimum values of the analogue signal on the representative portion of the curve, is determined by the following relation:

Synchronized clock pulses fed to the additional subtract inputs of the threshold counters 4 and 5 cause the contents thereof to vary. As soon as zero is present in the threshold counter 5, in the threshold counter 4 there will be a code corresponding to the difference between values AX2 and AX1. At this instant of time the decoder 7 blocks the subtract input of the threshold counter 5 and opens the AND gate 17. Synchronized clock pulses are fed through the frequency halver 10 and AND gate 17 to the additional add input of the reversible counter 9 until zero is present in the threshold counter 4 as in the threshold counter 5.

In this case, the decoder 6 blocking the subtract input of the threshold counter 4 blocks the AND gate 17 through the inverter 13. Simultaneously, the decoder 6 opens the AND gate 18. Thus, the reversible counter 9 will be fed with a number of pulses corresponding to the value AX0,, determined by expression (2), which causes the contents of the reversible counter 9 to be automatically corrected to a required value corresponding to the point on the midline between the maximum and minimum values of the analogue signal on the representative portion of the curve. On receiving a signal from the output 58 of the AND gate 18, the corrected contents of the reversible counter 9 are transmitted to the digital display unit 10 to be numerically displayed therein.

The above design of a digital device for checking a steady-state value of the analogue signal enables to be determined more accurately.

In this device an error in determining the steadystate value of the analogue signal depends exclusively on the resolution ability of the converter of analogue signal into numerical pulse code and not on the noise level. The use of simple elements and units of digital-computing in the device ensures a high reliability, as well as a low cost and small, dimensions thereof. The use of the device for determining the steady-state value of the analogue signal, for example, for determining in numerical form a temperature of molten steel, measured by means of a thermocouple which is dipped in the melt for a short time, provides for a high accuracy of measurements.

For example, when said device incorporates an analogue-to-digital converter for converting an analogue signal into a numerical pulse code, having resolution ability 1 OC, the maximum error caused by this device in the measuring system does not exceed +0.5 C.

While the invention has been described herein in terms of the preferred embodiments, it will be readily understood by those skilled in the art that numerous variations may be made in the digital device for checking a steady-state value of the analogue signal herein described without departing from the invention as set forth in the

Claims

appended claims. Claims

1. A digital device for determining the steadystate value of an analogue signal, comprising; an analogue-to-digital converter for converting an analogue signal into a numerical pulse code, having a first output for code pulses corresponding to a positive increment of the analogue signal and a second output for code pulses corresponding to a negative increment of the analogue signal; a clock pulse generator; a synchronization unit for distribution in time of code and clock pulses having first and second inputs connected to the first and second outputs respectively, of the analogue-to-digital converter, a third input connected to the output of the clock pulse generator, a first output for synchronized code pulses corresponding to a positive increment of the analogue signal, a second output for synchronized code pulses corresponding to a negative increment of the analogue signal and an output for synchronized clock pulses; three inverters; seven AND gates; a time interval discriminator for selecting intervals between two sequence instants of time when a local increment of the analogue signal assumes a predetermined value, said discriminator having a count input, first and second initial setting inputs and an information output connected to first inputs of the first, second, third and fourth AND gates and through the first inverter to the first input of the fifth AND gate; first and second threshold counters for determining local increments of the analogue signal, each having an add input, a subtract input, an additional subtract input, subtract count blockings input, an overflow output and digit outputs; zero state decoders for the first and second threshold counters whose inputs are connected to the digit outputs of the respective threshold counters, the outputs of the decoders being connected to the subtract count blocking input of the respective threshold counters, and the overflow outputs of the first and second threshold counters being connected to the first and second initial setting inputs, respectively, of the time interval discriminator, respectively; a reversible counter for generating a parallel code corresponding to the analogue signal steady-state value having an add input, a subtract input, an additional add input, an additional subtract input and digit outputs; a digital display unit for displaying the calculated result, having an information input electrically connected to the digit outputs of the reversible counter, and a control input; and a frequency halver having an input connected to the output for synchronized clock pulses of the synchronization unit, and an output, the output for synchronized clock pulses of the synchronization unit also being connected to the second inputs of the first and the fifth AND gates, the outputs for synchronized code pulses of the synchronization unit corresponding to positive and negative increments of the analogue signal being connected to the first inputs of the sixth and the seventh AND gates, respectively, second inputs of which are connected to the first input of the fifth AND gate, second inputs of the second and the third AND gates being connected to the frequency halver output; the output of the zero state decoder of the first threshold counter being connected to a third input of the third AND gate, to a second input of the fourth AND gate and through the second inverter, to a third input of the second AND gate, the output of the zero-state decoder of the second threshold counter being connected to a fourth input of the second AND gate, to a third input of the fourth AND gate, and through the third inverter to a fourth input of the third AND gate, an output of the first AND gate being connected to the additional subtract inputs of the first and second threshold counters, outputs of the second and the third AND gates being connected to the additional subtract and add inputs, respectively, of the reversible counter, an output of the fourth AND gate being connected to the control input of the digital display unit, an output of the fifth AND gate being connected to the count input of the time interval discriminator, an output of the sixth AND gate being connected to the add inputs of the first threshold counter and of the reversible counter and to the subtract input of the second threshold counter, and an output of the seventh AND gate being connected to the subtract inputs of the first threshold counter and of the reversible counter and to the add input of the second threshold counter.

2. A digital device for determining the steadystate value of an analogue signal, substantially as hereinbefore described with reference to and as shown in the accompanying drawings.

3. A device for determining the steady-state value of an analogue signal, comprising an analogue-to-digital converter arranged to produce first pulses corresponding to positive increments in the analogue signal and second pulses corresponding to negative increments in the analogue signal, a first counter arranged to count the first pulses, a second counter arranged to count the second pulses, a timer arranged to be reset when the first or second counter reaches a predetermined count, an up/down counter arranged to count up the first pulses and to count down the second pulses, a clock pulse generator, and display means arranged to display the contents of the up/down counter, the timer being arranged, upon reaching a preset time without having been reset, to prevent the first and second counters and the up/down counter from counting the first and second pulses, and to cause the first and second counters count down until their contents are zero, the up/down counter being arranged, if the second counter reaches zero before the first counter, to count up substantially half the clock pulses between the second counter reaching zero and the first counter reaching zero and, if the first counter reaches zero before the second counter, to count down substantially half the clock pulses between the first counter reaching zero and the first counter reaching zero.