GB2033697A - Display control for operator's desks - Google Patents

Abstract

A display control arrangement for an operator's desk in a telephone exchange, such as a private automatic branch exchange, is used to display information relating to calls to be set up by the operator, and other information to be displayed. Information from the exchange's central control (10) is displayed alpha-numerically on an LED display in two parts, one (19) for alphabetical information and the other (20) for numerical information. This uses a switch (18) controlled in accordance with the information to be displayed, and uses either addresses supplied with the information or internally generated addresses. It is also possible by a simple code conversion to enable information to be displayed in different languages. <IMAGE>

Description

SPECIFICATION Display control for operator's desks This invention relates to a display control arrangement for operator's desks, e.g., for operator's desks of computer-controlled exchange systems, comprising at least one display for information from a central control in the exchange, which information includes an address part, a data part, and an instruction part, the data part being stored in a memory of the control arrangement according to the associated address and subsequently read out by internal addressing. Although the present invention is described herein as applied to a private branch exchange (PBX), it should be borne in mind that it is applicable to other forms of telecommunication exchange.

In PBX systems, incoming calls-so-called central-office calls - are connected to a desired internal extension set. Outgoing calls or internal calls between extensions can also be set up in such exchanges. The individual extension sets usually differ in their classes of service. Thus from partially restricted sets, for example, toll calls can be made only by calling the exchange. In conventional PBX systems, such a demand to set up a connection, or other states of a call, are displayed at the operator's desk by push-button-assigned switchboard lamps.

The number of the internal extension is displayed in such systems by a lamp panel.

The life of the small lamps used in such systems is short, so high maintenance costs are incurred.

Further, the wiring needed is costly, since one wire per lamp is used from the central control to the operator's desk. A particular disadvantage is that these exchanges are extremely inflexible in construction, and so cannot be adapted to different requirements regarding their use. Note that similar problems can arise in the case of an operator's desk for a public exchange, where there is still a substantial number of operator-assisted calls to be handled.

German Offenlegungsschrift No. 2,741,768 discloses a telephone control desk, which may be a subscriber set and particularly the operator's desk or switchboard position of a PABX, and which includes a display unit in which at least individual symbols are activated due to the received data and data entered into an input unit.The display on the visual display unit (VDU) is controlled by a microprocessor.

To keep the displayed data up to date, this desk has a read/write memory which must be ableto receive data from the central unit and to write such data into suitable memory locations. The data to be displayed on the VDU are continuously "refreshed". An address decoder is needed to decode an address for the read/write memory and to prepare a read/write logic for subsequent reading or writing. The signal from this decoder must be linked with a signal from the central unit to the read/write logic, so that the read/write memory can read incoming input data.

Control of this is very complex and hence need com plex and costly circuitry.

An object of the invention is to avoid the above mentioned disadvantages of conventional systems and provide a system in which the information associated with a call to be handled and pertaining to the status of the call orto a request for a call can be displayed alphabetically and/or numerically at the operator's desk at minimum cost.

According to the invention, there is provided a display control arrangement for operator's desks and particularly for operator's desks of computercontrolled exchange systems, including at least one display which shows information from a central control in the exchange system, which information consists of an address part, a data part, and an instruction part, the data part being stored in a memory of the display control arrangement according to the associated address and subsequently read out by internal addressing, wherein the display is divided into several groups each consisting of a number of display elements, wherein each said group has a memory assigned thereto, a location in the associated memory being assigned to each display element of a group, and wherein the address part is divided into an element address, designating a display element or a memory location, and a group address, designating the group.

The display advantageously consists of several elements whose individual segments are lightemitting diodes (LED's). With these display elements, the information from the central control to the operator's desk can be displayed alphanumerically. It is also possible for the information to be displayed in a desired language by suitably changing the code in the central control. Merely by rearranging the sequence of characters in the stored character set can the display be adapted to different requirements - e.g. other languages -, which is impossible in conventional systems because of the permanent wiring. The wiring required for the transfer of information in coded form from the central control to the memories associated with the display elements is kept to a minimum.

Note that although the invention is described in its application to a PBX or PABX it is not so limited.

An embodiment of the invention will now be explained with reference to the accompanying drawings, in which: Fig. lisa simplified block diagram of a display control arrangement embodying the invention; Fig. 2 is an example of a display control arrangement embodying the invention, and Fig. 3 is a part of the arrangement of Fig. 2.

The block diagram of Fig. 1 illustrates the interaction of the individual subassemblies used to display the information from a central control.

The central control 10 is of the same design as that in a conventional computer-controlled switching system and can feed information through a buffer memory 11 to a receive unit 12. The information in the buffer memory 11 is applied to the input of the receive unit 12 until the memory 11 is reset via the transmitter 13, i.e., until the contents of the memory 11 are erased. The data representing an information unit are transferred serially, but byte by byte, from the control unit 10 to the memory 11, which feeds them to the receive unit 12 in parallel. Such an information unit consists of an address part 1 2A, a data part 12D, and an instruction part 12B. The instruction in the instruction part 12B specified the processing to be performed in the display control AS.

The display control AS also includes a read/write control 14, an address logic 15, and two memories 16 and 17. If, for example, a "write" instruction is in the instruction part 12B, the read/write control 14 provides at its output i/e a control signal which sets the switch 18 in the address logic 15 to the position shown. The address in the receive unit 12 is applied via this switch 18 to the memories 16 and 17. According to a further item of information in the address part 12A, an enable signal is applied via the address logic 15 to the enable input EN of the memory into which the data in the data part are to be written.In the memory so selected by the enable signal, the data in the data part can thus be written into the address selected via the memory input A, with the read/write control 14 applying a signal indicating a write operation to the read/write input R/W in response to the instructions fed to it. At the end of the write operation, the buffer memory 11 is reset via the transmitter 13, which resetting ends the write operation, and the read/write control 14 automatically begins its read operation and causes the information in the memories 16, 17 to be indicated on displays 19, 20, see below. Note thatthe writing rate per letter or digit is so high that when old information is overwritten with new information, no undefined expressions visible to the human eye can result.

During a read operation, the data part and the address part of the receive unit 12 are disabled by the read/write control 14 via a control line R. A signal indicating a read operation is presented to the memory inputs R/W, and the switch 18 is set to its other position by a control signal from the output i/e of the control 14. Over the connection shown as a solid line, control 14 applies an internally-generated address sequence via the switch 18 to the address inputs A of the memories 16, 17. At the same time, an enable signal appears at the inputs EN of both memories. Through the addresses generated in the read/write control 14, all addresses of the memories 16, 17 are cyclically interrogated, and the data stored therein are decoded and indicated alphabetically and/or numerically on the displays 19, 20.Note that the decoding may be done, in known manner, in a decoder (not shown) associated with the display.

The displays 19 and 20 and the associated memories 16 and 17 may be divided into an alphabetic portion (S,z, A) and a numeric portion (Sn, An), as shown.

Fig. 2 is a more detailed representation of the display control of Fig. 1. The receive unit 12 consists of an address part 12A, a data part 12D, and an instruction part 12B. Each of these parts has a line-assigned receiver LE for each bit to be received, i.e., the address part 12A has six such receivers LE so as to be able to receive six incoming bits simultaneously.

The address part 12A is subdivided into the parts E and G. If the display 19, 20 consists of, e.g., six groups of display elements, and each group, in turn, consists of six display elements, the address part E may specify which element of a group is to be "activated", the address part G specifying the group desired. This will be further explained below. Shown on the left of the receive unit are examples of bit patterns which initiate the operations "read", "write", and "erase alpha". "Erase alpha" means thatthe alphabetic display 19 is to be erased.

The different instructions are recognized by two OR gates 21,22 and an inverter 23, which are logic elements in the read/write control 14. The control 14 also has a clock generator 24, whose clock signal is applied to a programme counter 25, which, in turn, delivers the internally generated address sequence in binary-coded form to the switch 18. The internal address is formed by the counts appearing at the counter output, which are incremented by one on every pulse from the clock generator 24 until the highest order address is reached, whereupon the counter 25 is reset and incremented from the initial address. Thus, a cyclic addressing mode is obtained.

Connected to the outputs of the receivers of the instruction part 12B is a recognition circuit 26 which sends a reset signal via the transmitter 13 to the buffer memory 11 after an instruction has been executed. The memory 11 is now prepared to receive the next instruction.

On receipt of a "read" instruction, the three receivers of the instruction part 12B are all set toO. A reset signal is applied through the inverter 23 to the receivers of the address part 1 2A and of the data part 12D. At the same time, the input S of the switch 18, a multi-position switch or so-called multiplexer, is fed with a control signal which sets the switch 18 to its position in which the outputs of the counter 25 are connected to the outputs of the switch 18. The designation "3L" indicates that the switch 18 also has three outgoing lines. This representation has been chosen for clarity. The address sequence from the counter 25 (internal address) is thus applied to the address inputs A of the memories S1 to S6.At the same time, a 0 signal, indicating a read operation, is applied via the OR gates 21,22 to the read/write inputs RNV of the memories S1-S6. The decoder 27 in the address logic 15 receives 0 bits over three lines (3L): itis a 1-out-of-8 decoder all of whose output lines are at 1 when its three input lines are at O. Note that, in the embodiment shown, only six outputs of the decoder 27 are used. The enable signal is thus applied to all enable inputs EN of the memories S1 -S6simultaneously. Assuming that the memories S1-S6 each have six locations, and the internally generated address 001 is applied, which specifies the first location, the contents of all locations 1 of the memories S1-S6 will be read in parallel. The information stored in these locations is fed through decoders D1-D6 to the display 19,20. The design and operation of the memories S1 -S6, the decoders Df-D6, and the display 19,20 will be explained below with the aid of Fig. 3.

In the receiver connected to the inverter 23, the "write" instruction contains a 1. Thus no reset signal is applied to the input R of the address part 12A and of the data part 12D, and the switch 18 connects the lines E of the address part 12A to its output. The internal addressing has no effect. Both OR gates 21, 22 provide a 1, indicating a write operation, to the read/write inputs Rev of the memories S1-S6. A memory to which an enable signal isto be applied is selected by the decoder 27. As shown, the input of the decoder 27 is fed with the bit pattern 010, which causes an enable signal to be applied to the memory S2.

The "erase alpha" instruction results in a 1 at the output of the OR gate 22, which prepares the memories S1-S3 for a write operation. At the same time, the receivers of the address part 12A and of the data part 12D are disabled via the inverter 23. The switch 18 is switched to "internal addressing". As during "read", all memories are enabled via the decoder 27, and the internally generated address is presented simultaneously to the address inputs A.

Since all receivers of the data part 12D were set 0 by the disable signal, this "0-information" is written into the memories S1-S3, so that memories S1-S3, and, hence the display 19, are erased. The erasure of the display may also be caused by another item of information, which can be achieved by suitable decoding.

If the numeric display 20 and the associated memories S4-S6 are to be erased, the instruction 010 is required instead of the instruction 001 ("erase alpha"). The memories S4-S6 are then prepared, via the OR gate 21, for a subsequent write operation which corresponds to the above-described write operation caused by an "erase alpha" instruction.

Fig. 3 shows part of the block diagram of Fig. 2 in greater detail. The displays 19, 20 of Fig. 2 consist of six groups G1-G6, each having six display elements E1-E6, of which Fig. 3 shows group G1, in which the letter K is displayed on the element E2 as an example. The group address G of the data part 12A determines in which group G the information in the data part 12D is to be displayed. The element address E specifies the element of the selected group to be used.

In the example shown, the address in the address part 12A specifies a display in the group G1 on the element E2. The bit pattern in the data part 1 2D is written into the location 2 of the memory S1, which is assigned to the group G1. The location 2 is assigned to the element E2. When the location 2 is read, the data contained therein are transferred in parallel to the decoder D1. In the present example, the stored bit pattern 01011 corresponds to the number 11 in the binary code. An allocator 28 in the decoder D1 with its output connected to a read-only memory (ROM) 29 causes the contents of the eleventh location of the ROM 29 to be transferred in parallel to all display elements of the group G1. In this case, this eleventh location corresponds to the eleventh letter of the alphabet.To prevent the letter K from being displayed on all display elements at the same time, the element E2, corresponding to the location 2 of the memory S1, is selected by a decoder 30. In this case, decoder 30 is a 1-out-of-8 decoder fed with the element address, which in this case, causes the display element E2 to be activated.

If the address 000 is presented to the input of the decoder 30, all elements of the group G1 remain off.

Note that the decoder D1 and, of course, the other decoders D2-D6 may be designed without a ROM 29, in which case the data read from the memories S1-S6 are applied to the displays via a suitable decode logic in known manner It is also possible to use in the decoders D1-D6 programmable memories which contain entire words in specified locations, i.e., a memory location holds the entire information for one of the groups G1-G6. To identify a centraloffice call, for example, the information "AMT-AR" may be displayed. If this display is to be possible in different languages, the information in the central control 10 in coded form may be rearranged there in a suitable manner. It is also possible, however, to perform such a rearrangement in the decoders D1-D6. This may be done by storing entire words in the ROMs 29, the words being assigned to a desired language and written in coded form. To this end, the ROM 29 may be programmable (PROM), or use is made of ROMs assigned to a desired language.

Claims (15)

1. A display control arrangement for operator's desks and particularly for operator's desks of computer-controlled exchange systems, including at least one display which shows information from a central control in the exchange system, which information consists of an address part, a data part, and an instruction part, the data part being stored in a memory of the display control arranged according to the associated address and subsequently read out by internal addressing, wherein the display is divided into several groups each consisting of a number of display elements, wherein each said group has a memory assigned thereto, a location in the associated memory being assigned to each display element of a group, and wherein the address part is divided into an element address, designating a display element or a memory location, and a group address, designating the group.

2. An arrangement as claimed in claim 1, wherein the information transferred from the central control to the display control is binary-coded and byte-organized and is temporarily stored serially, but byte by byte, in a buffer memory which transfers words - (consisting of address, data, and instructions) -to a receive unit of the display control in parallel, the receive unit being correspondingly divided into an address part, a data part, and an instruction part.

3. An arrangement as claimed in claim 2, wherein the address part has its outputs connected to the input of an address logic whose outputs are respectively coupled to the enable inputs of the memories, wherein the data part is coupled to the data inputs of all memories, said data inputs being connected in parallel, and wherein the instruction part is coupled to a read/write control which controls the addressing and the data transfer from the data part to the memories.

4. An arrangement as claimed in claim 1,2 or3, wherein the element address is applied to a switch in the address logic whose output is coupled to the address inputs of the memories, wherein either the element address in the address part and applied at the input of the switch or an internally generated address can be transferred to the output of the switch, and wherein the group address is applied to a 1-out-of-n decoder having its n outputs coupled to respectively enable inputs of the memories.

5. An arrangement as claimed in claim 4, and wherein the internal addresses are provided by a counter whose count input is fed with clock pulses from a clock generator.

6. An arrangement as claimed in claim 1, 2,3,4 or 5, wherein the display includes an alphabetic dis play for presenting texts, and a numeric display for presenting data, and wherein the memories and the decoders associated therewith, are divided into an alphabetic portion and a numeric portion.

7. An arrangement as claimed in claim 1,2,3,4, 5 or 6 wherein the instruction part consists of three line-assigned receivers each receiving a bit from the buffer memory, one of said receivers having its output connected via an OR gate to the read/write inputs of the memories associated with the numeric display, another said receiver being correspondingly connected via an OR gate to the memories associated with the alphabetic display, and wherein the third said receiver, which receives the bit indicating a write operation, has its output connected via an inverter to the disable inputs of said receivers of the address part and of the data part and to the control input of the switch.

8. An arrangement as claimed in claim 1,2,3,4, 5, 6 or 7, which includes a recognition circuit connected to the outputs of said receivers of the instruction part and to a clock generator, and whose output signal is applied via a transmitter to the reset-input of the buffer memory such that, after an instruction transferred from the buffer memory to the receiver unit has been executed, the buffer memory is reset and thus enabled to receive a new instruction from the central control.

9. An arrangement as claimed in claim 4 or any claim appendantthereto,wherein each of the decoders connected between the memories and the displays contains a read-only memory in which a given character set is stored in coded form under addresses which are read by the data stored in the memories.

10. An arrangement as claimed in claim 9, wherein entire words each representing a complete unit of information are stored in given locations of the read-only memories.

11. An arrangement as claimed in any one of the preceding claims wherein the displayed information such as type of call, subscriber status, wrong operation, cut in on busy connection, etc., indicates the respective status of a call.

12. An arrangement as claimed in any one of the preceding claims wherein a simple rearrangement of the display sequence provided in the central control or in the read-only memories permits a presentation of information in different languages.

13. An arrangement as claimed in claim 12, wherein said rearrangement is made in the central control or accomplished by rearranging the words stored in the read-only memories, which may be programmable or replaceable.

14. An arrangement as claimed in any one of the preceding claims, wherein the writing rate between the central control and the display control is chosen to be so high-e.g. 666Hz-that, when old information is overwritten, i.e. new information is written, no visible, undefined expressions orfrag- ments of existing expressions can be produced.

15. A display control arrangement for an operator's desk in a telephone exchange, substantially as described with reference to the accompanying drawings.