GB2032150A

GB2032150A - Digital frequency synthesizer

Info

Publication number: GB2032150A
Application number: GB7931027A
Authority: GB
Original assignee: Raytheon Co
Current assignee: Raytheon Co
Priority date: 1978-09-11
Filing date: 1979-09-07
Publication date: 1980-04-30
Also published as: IT1120565B; US4240034A; FR2435860B1; DE2936250C2; JPS5538800A; DE2936250A1; FR2435860A1; JPH0215407Y2; IT7950222A0; JPH01175028U; GB2032150B; CA1112767A

Description

1 GB 2 032 150 A 1

SPECIFICATION Digital Frequency Synthesizer

This invention relates generally to digital frequency synthesizers and more particularly to digital frequency synthesizers adapted to produce radio frequency signals.

As is known in the art, one type of digital frequency synthesizer includes a plurality of highly stable oscillators coupled to a plurality of counters or frequency multipliers to produce subharmonic frequency signals. These signals are then selectively combined using heterodyning mixers and filters to produce a signal having the desired frequency. Such apparatus is relatively expensive and not generally suited to produce signals having relatively short time durations such as pulses used in radar and pulse 10 communication systems. ' In accordance with the present invention, there is provided a digital frequency synthesizer adapted to produce a signal having a frequence f, comprising a counter responsive to clock pulse signals having a pulse repetition frequency f. to produce a first digital word representative of the P number of counted clock pulses, adding means arranged to cumulatively add to a second digital word a value representative of fc 15 nf (where n is an integer) each time the whole number portion of the second digital word equals the first digital word, under the control of a comparator means which produces a control signal indicative of whether the whole number portion of the cumulatively added digital word is equal to or unequal to the first digital word, and output means responsive to the control signal for producing a signal having a frequency related to the frequency f.

The invention will be described in more detail, by way of example, with reference to the 20 accompanying drawings, in which:

Figure 1 is a block diagram of a frequency synthesizer embodying the invention; and, Figure 2A-2L are timing diagrams useful in understanding the invention.

Referring now to Figure 1, a digital frequency synthesizer 10 is shown to include an intermediate frequency synthesizer section 12 adapted to produce "in phase" and "quadrature" intermediate 25 frequency signals and a radio frequency section 14 adapted to heterodyne the "in phase" and "quadrature" intermediate frequency signals to a radio frequency signal. The radio frequency section 14 includes a conventional radio frequency oscillator 16 adapted to produce a radio frequency signal having a frequency fc, here 9900 MHz, which is fed to a first mixer 18 as shown and to a second mixer 20 through a 900 phase shifter 22 as shown. The "in phase" intermediate frequency signal is also fed 30 to the first mixer 18 as shown and the "quadrature" intermediate frequency signal is also fed to the second mixer 20, as shown. The outputs of first and second mixers 18, 20 are fed to bandpass filters 24, 26, respectively, as shown, here having bandpass frequencies of fc+f., here 9900 MHz+ 150 MHz.

That is, each one of the bandpass filters 24, 26 has a centre frequency of f.=9900 MHz and a bandwidth of 2 f.=300 MHz. The signals passed by the filters 24, 26 are summed together in a conventional RF summing network 28. The output of such summing network 28 is fed to a conventional travelling wave tube amplifier (TVVT) 30, and the amplified radio frequency signal is transmitted through a conventional antenna 32, as shown.

Referring now to the intermediate frequency synthesizer section 12, a digital computer 34 is provided to produce a digital word on bus 35 which represents the number of clock pulses produced by 40 a conventional clock pulse generator 36 on line cp in a quarter cycle of the intermediate frequency signal to be produced by section 12 and to produce a binary control signal on line 37 indicative of whether the desired radio frequency signal to be transmitted has a frequency above or below the frequency fr of the local oscillator 16. It is first pointed out that the clock pulse generator 36 produces clock pulses on line cp at a frequency of f., here 320 MHz. Therefore, if the desired frequency of the 45 p radio frequency signal to be transmitted is f, then the digital word produced by the computer on bus is determined as follows:

digital word on bus 35- f.p (1) where the frequencies f.

P, f, and f,, are entered into the computer 34 by any convenient means, such as a conventional key board, not shown. Further, if the desired frequency fT is above (or equal to) the local 50 oscillator frequency f., the signal on line 37 is high, representing a logical 1, and, if the desired frequency fT is lower than the local oscillator frequency f, then the signal on line 37 is low, representing a logical 0. By way of example, if it is desired to transmit a radio frequency signal of frequency fr=9930 MHz, the digital word on bus 35 (from Eq. 1) is 320 MHz -9.67 clock pulses per quarter cycle; 55 4(30) MHz the intermediate frequency signal has a frequency f1F=fT-f,=30 MHz and the control signal on line 37 2 GB 2 032 150 A 2 is high (logical 1), indicating the radio frequency signal has a frequency above the local oscillator frequency. It should be noted that the digital word on bus 35 has a whole number portion, here 2, and a decimal number portion, here 67.

In response to a start signal on line---START",J-K flip/flop 40 is placed in a set condition and output Q thereof goes high, producing a high signal on enable line EN. In response to such high signal on line EN, the digital word on bus 35 becomes stored in a register 42. The output of register 42 is fed to a conventional adder 44. Also fed to adder 44 is a digital word on a bus 45 produced at the output of a selector 46. The sum of the digital word stored in the register 42 and the digital word on bus 45 becomes stored in an accumulator 48 which is initially reset to 0... 0 by a signal on line RESET prior to the start signal. The entire digital word stored in the accumulator 48 is fed to the selector 48 while just10 the whole number portion of the digital word stored in the accumulator 48 is fed to a comparator 50. That is, the upper bits of the digital word stored in accumulator 48 which represents the whole number portion of such digital word are fed to the comparator 50. Also fed to comparator 50 is a conventional digital counter 52. Counter 52 is initially reset to 0.. . 0 by a signal on line RESET prior to the start signal. When enabled by the signal on line EN, counter 52 counts the clock pulses fed thereto on line cp by clock pulse generator 36. The contents of the counter 52 therefore represents the number of clock pulses fed to such counter 52 after such counter 52 is enabled by the signal on line EN.

Comparator 50 compares the counted number of clock pulses counted by counter 52 with the whole number portion of the digital word stored in the accumulator 48, and when such are equal, a "high" or logical 1 signal is produced by comparator 50, whereas if such are unequal or "low", a logical 20 0 is produced. That is, if:

(a) contents of counter 52=integer contents of accumulator 48, comparator 50 output=l; whereas if:

(b) contents of counter 520contents of accumulator 48, comparator 50 output=0.

The output of comparator 50 is fed to selector 46 and a pair of -D- type flip/f lops 54, 56 via line 25 58, as shown. The signal on line 58 provides a control signal for selector 46 and, in particular, when the signal on line 58 is logical 0, the digital word fed to terminal "A" of such selector 46 is passed to adder 44 via bus 45, whereas if the signal on line 58 is logical 1, the digital word on terminal -B- becomes fed to adder 44 via bus 45. A conventional register 60 having 0... 0 stored therein is here coupled to the terminal "A" of selector 48.

The signal on line 58 is also fed to the -clock- or c terminals of the D type flip/flops 54, 56, as shown. The M- output of flip/flop 54 (here labeled QA) is fed to the M- terminal of the flip/f lop 56, to the J terminal of J-K flip/flop 6 1, and to the input terminal of a shift register 62 through AND gate 63, as shown. Also connected to AND gate 63 is enable line EN, as shown. The U terminal of flip/flop 56 (here labeled U.) is fed to the D terminal of flip/flop 54, as shown. The -Q- output of flip/flop 56 (here 35 labeled Q,3) is fed to the input terminal of shift register 64 through AND gate 66, OR gate 68 and AND gate 7 1, as shown, and output 5,, is fed to the input of such shift register 64 through OR gate 68, AND gate 70 and AND gate 7 1, as shown. The control signal on line 37 is fed to AND gate 66 to enable the output Q. to be coupled to the '1npuV terminal of shift register 64 through OR gate 68 when AND gate 71 is enabled by the signal on line EN when the control signal on line 37 is "high" or logical 1, and such control signal is fed to AND gate 70 through inverter 74 to enable the output U,, to be coupled to the input terminal shift register 64 through OR gate 68 when the signal on line 37 is -lowor logical 1 when AND gate 71 is enabled by the enable signal on line EN.

As will be discussed hereinafter, flip/flops 54, 56 are initialized to produce "low" or logical 0 signal at outputs QA, Q,, Further, the J-K flip/flop 61 is placed in a reset condition by the enable signal 45 on line EN, thereby producing a 1ow- or logical 0 signal on line 72 in response to a "high" signal on line EN. When the signal at output QA Of fl'P/flop 54 first goes high (logical 1) for the first time after start, flip/flop 61 is placed in a set condition and the signal on line 72 goes---high---. The signal on line 72 is fed to AND gate 78 as shown. Also fed to such AND gate 78 is the enable line EN, as shown. The output of AND gate 78 is fed through OR gate 80 to the "enable" terminals of shift registers 62, 64, as 50 shown. When enabled, the signal on the input terminals of shift registers 62, 64 become stored in the shift registers in response to the clock pulses fed to such shift registers 62, 64 via line cp. As will be discussed hereinafter, after a predetermined number of clock pulses have been counted by counter 52, here a number equal to the number of stages in the shift registers 62, 64, a "high" signal is produced on line 84 by decoder 86. The signal on line 84 places the J-KEip/flop 40 in the reset state, producing 55 a "low" orlogical 0 signal on line EN and a high signal on line EN disabling further storage by the shift register 62, 64. After such shift registers 62, 64 have become full, a read signal is applied to line READ which passes through AND gate 88 to the J terminal of J-K flip/flop 90, producing a high signal on line RE. This enables the data stored in the shift registers 62, 64 to be read therefrom in response to clock pulses on line cp and hence at a rate fCP. The data read from the shift registers 62, 64 is fed to the radio 60 frequency section 14 for connection to the desired radio frequency signal. After the data has been read, a stop signal is applied to line RE to disable the shift registers 62, 64.

Referring now also to Figures 2A-21-, the operation of the intermediate frequency section 12 3 GB 2 032 150 A 3 c will be discussed. Figure 2A shows the clock pulses on line cp at a frequency f, here at a frequency f.p=320 MHz. In response to a start signal on line START at time tSTART, the signal on enable line EN goes "high" as shown in Figure 2B, thereby enabling storage of the digital word on line 35 into register 42. Here, for example, the digital word is (2.67), as discussed above. The digital word also becomes stored in the accumulator register 48 as shown in Figure 2C. In response to the first clock pulse after 5 the enable signal, the counter 52 produces a digital word (1),, as shown in Figure 2D. Comparator 50, in response to the whole number portion of the digital word stored in the accumulator 48 (here (2)10) and the digital word produced by counter 52 (here (1)10) produces a logical 0 on line 58. Selector 46, in response to the logical 0 signal, couples the contents of register 60 (here 0) to line 45, and hence the accumulator 48 continues to store (2.67),0. In response to the next clock pulse, counter 52 produces a 10 digital word (2)10. Comparator 50, in response to the whole number portion of the, digital word stored in the accumulator 48, here (2),,,, and the digital word now stored in counter 52, here (2),,, produces a logical 1 on line 58 as shown in Figure 2E. In response to such logical 1 signal the contents of accumulator 48 (here (2.67)j passes through selector 46 to adder 44 and becomes added to the digital word stored in register 42 (here (2.67),,), the sum (here (5.33),, ) becoming stored in accumulator register 48 as shown in Figure 2C, thereby returning the output of comparator 50 on line 58 to a logical 0 as shown in Figure 2E. The output of such comparator remains at logical 0 until counter 52 produces a digital word representative of (5)10. Then the comparator 50 output, Le., line 58, goes "high" (as shown in Figure 2E), the contents of accumulator 48 (now (5.33),()) become added to the contents in register 42 (i.e., (2.67)j.) to produce (8.0),, which becomes stored in the accumulator 20 48, returning the output of comparator 50 (i.e., line 58) to a logical 0 as shown in Figures 2C, 2D and 2E. It follows, then, that the digital word stored in register 42 (i. e., here (2.67),,,) becomes cumulatively added and stored in accumulator 48 each time the whole number portion of the digital word stored in accumulator 48 becomes equal to the digital word stored in counter 52. Further, the output of comparator 50 (i.e., line 58) changes from a logical 0 to a logical 1 each time the digital word stored in counter 52 is equal to the whole number portion of the digital word stored in accumulator 48, producing a series of pulses on line 58 as shown in Figure 2E. These pulses on line 58 are fed to the 11 c" or "clock" terminal of D-type flip/flops 54, 56, as shown. As discussed above, such flip/f lops are initialized to produce logical O's at outputs QA, Q, Hence, the outputs Q, QE, U, produce the following logical signals in response to the pulses on line 58:

Pulse on line 58 (See Figure 2E) OA UB OB A 1 1 0 B 1 0 1 35 c 0 0 1 D 0 1 0 E 1 1 0 F 1 0 G 0 0 40 H 0 1 0 1 1 1 0 j 1 0 1 K 0 0 1 The outputs QA, a, and Q, are shown in Figures 2F, 2G and 2H, respectively.

Considering first the signal produced at output QA (Figure 2F), when such output first goes to a 50 logical 1 (in response to pulse A), the output of flip/flop 61 (Figure 1) goes high (logical 1) and hence a logical 1 is produced at the output of AND gate 78 on line ENSR as shown in Figure 21. Hence, the data at output GA passes through enabled AND gate 63 and becomes stored in shift register 62 in response to the clock pulses on line cp as shown in Figure 2J as a series of logical 1's and O's, until such shift register 62 is full, at which time flip/flop 40 becomes reset by the signal on line 84 because then a low signal is produced on line EN. Considering now the outputs of flip/flop 66, either the signal at output QB or the signal at output-OB will become stored in shift register 64 depending on the logical signal on line 37. Here in the example being considered, the desired radio frequency signal has a frequency above the frequency of the local oscillator 16 and, hence, as discussed above, the signal on line 37 is -high" or logical 1. Hence, the signal at output QB becomes sequentially stored as a series of logical 1's 60 and logical O's in shift register 64 in response to clock pulses on line cp as shown in Figure 2K.

After the shift registers 62, 64 have become full, a read signal is applied to line READ, producing -a iogi-cal 1 or high signal in line RE. The bits stored -in shift-registers 62, 64 become sequentially read 4 GB 2 032 150 A 4 therefrom irtresponse to clock signals on line cp. The outputs of shift registers 62, 64 are fed to mixers 18, 20, respectively. Such outputs appear as binary signals having "high" and "low" levels as indicated by the dotted lines in Figures 2J and 2K, respectively. It should be noted that, to a 1 -bit quantization, the signal at the output of shift register 62 (Figure 2J) may be represented as sin 2.?r f[Ft and, likewise, the output of shift register 64 may be represented as -cos 27r f,Ft, where flF is the intermediate frequency, here 30 MHz. Further, the signal produced by the local oscillator 16 may be represented as sin 27r fct. Hence the signal produced at the output of summing network 28 may be represented as -cos 27r(fc+f1F)tl that is, a signal having a frequency, fTfc+fiF, here 9930 MHz. If, on the other hand, the desired radio frequency signal to be transmitted was to have a frequency 9870 MHz, the control signal on line 37 would have been "low" and the output Q. shown in Figure 2G would have been 10 stored in the shift register 64 (instead of output QJ. Hence, the data stored in the shift register 64 would be a series of logical l's and logical O's as shown in Figure 2L. The envelope, shown by the dotted line, may be considered as representing cos 27rf,Ft. Hence, the output of summing network 28 may be represented in such case as cos 27(fc-fip)t, that is, a signal having a frequency fT=fC+flF, here 9870 MHz.

The half-periods of the flip-flops 54 and 56 are necessarily composed of integral numbers of clock periods and, from inspection of Figure 2, it can be seen that some half periods are 5 clock periods long and other are 6 clock periods long. The flip-flop waveforms thus have instantaneous frequencies fluctuating between 320/11 =29.09 MHz and 310/1 0=32 MHz. However, 11 clock period cycles will occur 2.2 more frequently than 10 clock period cycles and the average frequency of the flip-flop 20 waveforms is thus exactly 30 MHz.

Claims

1. A digital frequency synthesizer adapted to produce a signal having a frequency f, comprising a counter responsive to clock pulse signals having a pulse repetition frequency fc p to produce a first digital word representative of the number of counted clock pulses, adding means arranged to cumulatively add to a second digital word a value representative of f.

p/rlf (where n is an integer) each time the whole number portion of the second digital word equals the first digital word, under the control of a comparator means which produces a control signal indicative of whether the whole number portion of the cumulatively added digital word is equal to or unequal to the first digital word, and output means responsive to the control signal for producing a signal having a frequency related to 30 the frequency f.

2. A digital frequency synthesizer according to claim 1, wherein the output means includes means for producing a binary signal level in response to each clock pulse, the binary state of such binary signal level changing at a frequency related to the frequency f.

3. A digital frequency synthesizer according to claim 2, wherein the output means includes at 35 least one bistable flip/flop fed by the control signal, the state of flip/flop changing in response to the control signal.

4. A digital frequency synthesizer according to claim 3, wherein there are two bistable flip-flops so coupled that the control pulses switch the states of the two flip- flops alternately.

5. A digital frequency synthesizer according to claim 1, 2, 3 or 4, wherein the adding means operated in each clock pulse period to add to the contents of an accumulator holding the second digital word either the value zero or the contents of a register storing the said value representative of fcp/nt as controlled by the comparator means.

6. A digital frequency synthesizer according to any of claims 1 to 5, wherein the number n is an 45. even integer.

7. A digital frequency synthesizer substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1980. Published by the Patent Office. 25 Southampton Buildings, London, WC2A 1 AY, from which copies may be obtained.

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