GB2024572A

GB2024572A - Reconstituting digital signals

Info

Publication number: GB2024572A
Application number: GB7924337A
Authority: GB
Original assignee: Marconi Co Ltd
Current assignee: BAE Systems Electronics Ltd
Priority date: 1978-04-19
Filing date: 1979-07-12
Publication date: 1980-01-09
Also published as: GB2024572B

Abstract

In apparatus for receiving and decoding digital data signals, an incoming signal R is fed to a discriminator 10 the output of which is fed by way of an integrating filter 1 to a slicer 13 which is arranged to slice the signal to digital levels. The output of the slicer is divided into n timeshifts under control of a clock pulse generator 4 running at n times the incoming data rate. Selection circuitry is arranged to select the one of the n timeshifts which gives a predetermined value of the integrated signal and to clock this timeshift to an output 6. <IMAGE>

Description

SPECIFICATION Receiving apparatus This invention relates to receiving apparatus and more particularly to apparatus for receiving and reconstituting digital signals. The invention is also concerned with methods for receiving and reconstituting digital signals.

Digital signals are transmitted by, for example, frequency modulation of a carrier wave which is subsequently propagated by radio transmission to a receiving aerial. The signal is then demodulated and presented to digital decoding apparatus to reconstitute the original message. Unfortunately, as is well known, the received signal is often subject to interference, transmission losses etc.

and is received in a distorted or diminished form.

Where it is desired to transmit a very long message a series of synchronising signals can be transmitted followed by a start signal and then by the message. This enables the digital decoder in the receiver to be synchronised so that it is clocked only for example at the certain instants of time corresponding to the centre part of each expected digital pulse. The presence of a pulse thus being easily detected by the received signal being above a predetermined threshold at those instants of time.

For short transmissions, however, it is not possible to send out a synchronising signal and a start signal since these would not leave sufficient transmission time for the message. It is therefore an object of the present invention to provide a method and apparatus for reconstituting transmitted data which method and apparatus are particularly advantageous in respect of short transmissions.

According to the present invention there is provided a method of receiving and decoding a digital message from a received signal in which the signal is integrated and sampled in n time shifts of a clock pulse train, and the time shift giving a predetermined value of the integrated signal is selected for decoding.

The present invention also provides apparatus for receiving and decoding a digitally coded signal comprising means for integrating and sampling an incoming digitally coded signal in n time shifts of a clock pulse train, and means for selecting for decoding the time shift giving a predetermined modulus value of the integrated signal.

Preferably there are eight time shifts and the means for integrating the incoming digitally coded signals comprises an integrating filter. When the incoming digitally coded signals comprise substantially rectangular bits immersed in white Gaussian noise the integrating filter may have a frequency response given by (sin x)/x.

The predetermined modulus value of the integrated signal may be the highest value or may be the lowest value thereof. In this latter case the time shift to be used for decoding will be four time shifts later than the time shift found.

The invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1 is a block schematic diagram of a receiving and decoding apparatus in accordance with the invention; Figure 2 is a more detailed block schematic diagram of the receiving and decoding apparatus shown in Figure 1; Figures 3 and 4 are block schematic diagrams of a selector shown in Figure 2; Figure 5 is a block schematic diagram of a modification of the receiving and decoding apparatus shown in Figure 2; Figure 6 shows various waveforms which will be used to explain the operation of the receiving and decoding apparatus shown in Figures 2 and 3.

Referring to Figure 1, the receiving and decoding apparatus comprises an integrating filter 1 to which a digitally coded input signal R is applied. The output of the integrating filter 1 is applied to the input of a shift register 2 by way of a slice and sample circuit 3. An eight times clock pulse generator 4 is arranged to supply a train of clock pulses 8CP at a pulse repetition frequency of say eight times the bit rate of the incoming signal R.

The clock pulses 8CP are applied to the shift register 2 and the slice and sample circuit 3. The output signals of the shift register 2 are applied to an output strobe circuit 5 arranged to provide data output signals on an output lead 6. The output signal from the integrating filter 1 is also applied to a timeshift selector 7 which is arranged to provide a clock output signal on an output lead 8 and to provide an enable signal via a lead 9 to control the output of the output strobe 5. The data lead 6 and the clock lead 8 may be connected to display apparatus (not shown) for example.

The slice and sample circuit 3 samples the output of the integrating filter 1 in eight time periods or time shifts governed by the output pulses 8CP of the clock pulse generator 4 and provides eight digital data streams interleaved in time. The eight digital data streams are stored in the shift register 2 and are stepped through the shift register 2 under control of the clock pulses 8CP. The timeshift selector 7 determines the most suitable timeshift, that is the timeshift most likely to occur nearest the end of the bit time of the bits of the data stream, and at that time passes an enable signal via lead 9 to the output strobe 5, the same signal being applied as a clock output via lead 8. The output strobe 5 is thus enabled to pass the most relevant data stream to the data output 6.

If the digitally coded signal R is assumed to comprise subseq uentially rectangular bits immersed in white Gaussian noise the integrating filter 1 is of the type having a frequency response given by Sin x/x where x is related to the frequency of the incoming signal. For other shapes of signal bits the required frequency response of the integrating filter 1 may be calculated in known manner.

The timeshift selector 7 may be arranged to select the timeshift which gives the highest value of the integrated signal or may be arranged to select the time shift which gives the lowest value of the integrated signal. If the timeshift selected is the one which gives the lowest value of the integrated signal then the enable to the output strobe 5 is arranged to select the data stream four timeshifts later than the timeshift found.

Referring also to Figure 2 the input signal R is fed to a discriminator 10 the output of which is connected to the integrating filter 1. The output signal of the integrating filter 1 is fed to the shift register 2 by way of a slicer 13 and a sampling AND gate 11. The clock pulse train 8CP from the eight times clock pulse generator 4 is fed to an enable input of the AND gate 11 and to the shift register 2. The output signals from the shift register 2 are applied to an AND gate 1 5 which corresponds to the output strobe 5 of Figure 1.

When the AND gate 1 5 is enabled the selected data stream is applied to the data output 6.

The timeshift selector 7 may be seen to comprise substantially a linear full wave rectifier 12, eight integrators 21 to 28 (only two of which are shown) and an eight input maximum detector 18 the outputs of which are fed via respective AND gates 31 to 38 (only two of which are shown) and by way of an eight input OR gate 19 to supply the clock output 8 and the enable signal 9 to the AND gate 1 5. Each integrator 21 to 28 comprises an analogue gate 1 6 and a capacitor 17. Each gate 16 is enabled in a respective one of the eight timeshifts by a respective signal from a 1 out of 8 selector or switch 51 under control of the clock pulse train 8CP.

The output signals from the integrating filter 1 pass by way of the linear rectifier 12 and an associated resistor 14 to the inputs of the integrators 21 to 28 in which respective samples of the eight timeshifts are integrated on the associated capacitors 1 7. The eight respective output signals from the capacitors 1 7 are connected to respective inputs of the maximum detector 18 which compares the signals and passes a signal to one of its eight outputs corresponding to the timeshift giving the maximum integrated value. The output signal from the maximum detector 1 8 corresponding to the selected timeshift passes via a respective one of the AND gates 31 to 38 and by way of the OR gate 1 9 to enable the AND gate 15 and supply the clock output 8.

Referring now to Figure 3 the maximum detector 18 comprises eight transistors 45 having a common emitter load 46. Eight input terminals 47 are connected to the respective bases of the transistors 45 and eight output terminals 48 are connected to the respective collectors of the transistors 45. If the voltage applied to any one of the input terminals 47 is sufficient to cause the respective transistor 45 to conduct the increased voltage drop across the common emitter ioad will cut off the other seven transistors 35. Thus only the respective one of the eight outputs 48 corresponding to the selected timeshift will fall in voltage. The threshold voltage required at the inputs 47 to cause any one of the transistors 45 to conduct may be adjusted by means of a variable resistor 42 provided in parallel with the transistor 45.

Referring to Figure 6, if the output of the discriminator 10 comprises substantially rectangular bits as illustrated in waveform 55 then the output signal from the integrating filter 1 will be substantially triangular as shown in waveform 56 and the output signal from the linear rectifier 12 will comprise substantially triangular pulses as illustrated in waveform 57 at twice the frequency of the output signal of the integrating filter 1. The parts 61 to 68 of the waveform 57 show approximately the respective magnitudes of the eight signals which are applied to the inputs 47 of the maximum detector 18. The signal 61 which has the highest magnitude will determine the timeshift at which the AND gate 1 5 is enabled to pass the selected data stream from the shift register 2 to the data output 6.

If the output signals from the integrating filter 1 are more nearly as shown in waveform 58 such that the output signals of the linear rectifier 12 as illustrated in waveform 59 do not have a clearly defined maximum then the minimum point 75 may be selected. In this case, the maximum detector is replaced by a minimum detector as for example the minimum detector shown in Figure 4.

The timeshift to be used must be the one which is four bits later than the timeshift in which the minimum point is detected.

Referring to Figure 5 the modified receiving and decoding apparatus functions in a similar manner to that hereinbefore described with reference to Figure 2 except in so far as the selection of the particular one of the eight timeshifts to be used is concerned.

Timeshift selection circuitry comprises a comparator 102 arranged to compare the value of the integrated voltage developed by the resistor 14 with each of the capacitors 1 7 in their respective timeshift with the value of the integrated voltage of a previous timeshift held in a sample and hold circuit 100.

If the voltage of one input 103 of the comparator 102 is nearer a minimum than the voltage on the other input 104 the comparator 102 forwards an enable signal to an AND gate 101. If the enable signal from the comparator 102 is still present when the AND gate 101 is clocked by the next clock pulse 8CP the AND gate 101 enables the sample and hold circuit 100 to sample Eand hold the integrated voltage at that timeshift.

The output signal from the AND gate 101 also resets a 3 bit binary counter 106 by way of a further AND gate 105. The sample and hold circuit 100 therefore continues to sample the integrated voltage until a minimum value of that voltage is reached at which time the comparator 102 removes the enable signal from the input of the AND gate 101. The counter 106 then cyclically counts the clock pulses 8CP and each time the counter 106 reaches the binary value 4 (i.e. 1 00) a decode circuit 107 outputs a clock signal on the clock lead 8 and clocks the AND gate 1 5 to enable the data bit occuring in the selected timeshift (i.e.

the time shift 4 clock pulses later than the minimum value of the integrated signal) to the output lead 6.

The AND gate 105 is provided to permit a user to disable the resetting of the counter 106 by means of a clamp selection input of the AND gate.

Thus once the apparatus is synchronised with the incoming signal a disable signal may be applied to the clamp selection input and the counter 106 runs under the control of the clock pulse train 8CP and the decode circuit 107 enables the AND gate 15 in the same timeshift of each cycle of eight timeshifts.

Claims

1. A method of receiving and decoding a digital message from a received signal in which the signal is integrated and sampled in n time shifts of a clock pulse train, and the time shift giving a predetermined value of the integrated signal is selected for decoding.

2. A method of receiving and decoding a digital message as claimed in Claim 1 in which the value of is 8.

3. Apparatus for receiving and decoding a digitally coded signal comprising means for integrating and sampling an incoming digitally coded signal in n time shifts of a clock pulse train, and means for selecting for decoding the time shift giving a predetermined modulus value of the integrated signal.

4. Apparatus for receiving and decoding a digitally coded signal as claimed in Claim 3 in which the value of n is 8.

5. Apparatus for receiving and decoding a digitally coded signal as claimed in Claim 3 or Claim 4 in which said means for integrating the incoming digitally coded signals comprises an integrating filter.

6. Apparatus for receiving and decoding a digitally coded signal as claimed in Claim 5 in which said integrating filter has a frer,uancy response given by sin Vx.

7. Apparatus for receiving and decoding a digitally coded signal as claimed in any one of Claims 3 to 6 in which said predetermined modulus value is the highest value thereof.

8. Apparatus for receiving and decoding a digitally coded signal as charmed in any one of Claims 3 to 6 in which said predetermined modulus value is the lowest value thereof.

9. Apparatus for receiving and decoding a digitally coded signal as claimed in Claim 8 in which the time shift used for decoding said incoming digitally coded signals is four timeshifts later than the timeshift giving the lowest modulus value.

10. Apparatus for receiving and decoding a digital message as claimed in Claim 8 or Claim 9 wherein said means for selecting the timeshift includes a comparator arranged to give an output when the modulus value of the signal in the current timeshift is nearer a minimum than the modulus value of the signal in a previous timeshift

11. A method of receiving and decoding a digital message from a received signal substantially as hereinbefore described with reference to the accompanying drawings.

12. Apparatus for receiving and decoding a digital message substantially as hereinbefore described with reference to Figures 1, 2, 3 and 6 of the accompanying drawings.

13. Apparatus for receiving and decoding a digital message substantially as hereinbefore described with reference to Figures 1, 5 and 6 of the accompanying drawings.

14. Apparatus for receiving and decoding a digital message substantially as hereinbefore described with reference to Figures 1, 2, 4 and 6 of the accompanying drawings.