GB1605247A - Phase-lock loop systems - Google Patents
Phase-lock loop systems Download PDFInfo
- Publication number
- GB1605247A GB1605247A GB364877A GB364877A GB1605247A GB 1605247 A GB1605247 A GB 1605247A GB 364877 A GB364877 A GB 364877A GB 364877 A GB364877 A GB 364877A GB 1605247 A GB1605247 A GB 1605247A
- Authority
- GB
- United Kingdom
- Prior art keywords
- frequency
- phase
- output
- signal
- discriminator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001228 spectrum Methods 0.000 claims description 9
- 230000003534 oscillatory effect Effects 0.000 claims description 6
- 238000013459 approach Methods 0.000 claims description 4
- 230000002401 inhibitory effect Effects 0.000 claims description 4
- 230000000694 effects Effects 0.000 description 2
- 230000001427 coherent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
(54) IMPROVEMENTS IN OR RELATING TO PHASE-LOCK LOOP SYSTEMS
(71) We, THE MARCONI COMPANY
LIMITED, of Marconi House, New Street,
Chelmsford CMl 1PL, Essex, a British
Company, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:
This invention relates to phase-lock loop systems.
A phase-lock loop basically comprises a controllable-frequency oscillator, a phasecomparison circuit for performing a comparison between the output of the oscillator and an incoming oscillatory signal, and means for automatically adjusting the frequency of the oscillator in response to the result of that comparison, in such a manner as to tend to lock the oscillator into a predetermined frequency and phase relationship with the incoming signal.
It is known to use such a phase-lock loop for coherent reception and frequency tracking of a signal. For example, the loop may be used in a radio receiver for receiving and tracking a radio signal which undergoes a doppler shift as a result of relative motion between the receiver and the source of the radio signal. Such phase-lock loops find applications, for example, in spacecraft tracking systems and in missile guidance systems.
In operation of such a phase-lock loop, if frequency and phase lock is lost at any time (e.g. because of excessive noise in the system), causing the frequency of the oscillator to diverge substantially from the incoming signal frequency, the loop may not be able to regain lock. Some means must therefore be provided to enable the loop to "acquire" an incoming signal. This may be achieved by applying a bias to the loop such as to cause the oscillator to scan through a predetermined range of frequencies until it approaches the abovementioned predetermined frequency relationship with the incoming signal, whereupon the phase-lock loop will operate to pull rapidly into frequency and phase lock with the incoming signal.
Such a signal acquisition means is suitable for use in cases where the incoming signal consists of only a single frequency component.
However, it would be desirable to provide a signal acquisition means suitable for use where the incoming signal consists of a plurality of frequency components and where it is required to lock on to a specific one of those components. For example, the incoming signal may be pulsed, and therefore have a frequency spectrum comprising a main line and plurality of side lines of lower intensity, spaced symmetrically about the main line, and in such a case it may be desired to lock on to the main line, and not to the side lines.
One object of the present invention is therefore to provide a phase-lock loop system having signal acquisition means suitable for use with an incoming signal having a plurality of frequency components.
According to the present invention there is provided a phase-lock loop system, for receiving and frequency tracking an incoming oscillatory signal having a plurality of frequency components comprising: a local oscillator producing an output signal which is controllable in frequency; a mixer for multiplying together the output of said oscillator and said incoming signal so as to produce an I.F. signal containing a plurality of
I.F. components; band-pass filter means through which said I.F. signal is passed; a reference oscillator producing a reference signal output; a phase-sensitive detector for measuring the instantaneous phase difference between said reference signal and the I.F.
signal from said filter means; means for automatically adjusting the frequency of said local oscillator in response to said phase difference as measured by said phase-sensitive detector so as to tend to lock one of said I.F.
components to the reference signal frequency, and thereby establish a predetermined frequency and phase relationship between the local oscillator frequency and one of the frequency components of the incoming signal; and signal acquisition means comprising: means for causing said local oscillator to scan through a predetermined range of frequencies, so as to tend to bring said I.F. components into the pass-band of said filter; inhibiting means responsive to a rise in the output from said filter, indicating that at least some of said I.F.
components have been brought into said pass band, to inhibit said scanning means so as to prevent further operation thereof; and frequency discriminating means including a phase shifting network connected to the output of said reference oscillator the output of which is connected to a further phase-sensitive detector in which it is compared with the I.F.
signal, the output from the further phasesensitive detector being compared with the differentiated output of the phase-sensitive detector in a yet further phase-sensitive detector, the output of said yet further phase-sensitive detector being the output of said frequency discriminating means, said frequency discriminating means operating to further scan the frequency of said local oscillator in such a manner as to substantially reduce the output of said further discriminating means to zero and thereby cause the phase-lock loop system to lock on to a predetermined one of said frequency components.
A phase-lock loop system in accordance with the invention will now be described, by way of example, with reference to the accompanying drawing in which the single Figure is a schematic block circuit diagram of the system.
Referring to the drawing, an incoming radio signal is received by means of an aerial 10, and is combined in a mixer 12 with a signal from a radio-frequency local oscillator 14 to produce an intermediate frequency (I.F.) signal. If the incoming signal has a plurality of frequency components, the I.F. signal will also consist of a plurality of respective components. The I.F.
signal is fed through an I.F. amplifier 16 and a band-pass filter 18. The signal from the filter 18 is detected by a diode 20, and fed back to the amplifier 16 in such a manner as to form an automatic-gain-control (A.G.C) loop, which tends to maintain the total power appearing at the output of the filter 18 at a constant level.
Thus, the output from the filter 18 is, in effect, a normalised version of the output from the mixer 12.
The output from the filter 18 is compared, in a phase-sensitive detector 22, with a reference signal generated by a reference oscillator 24, having a frequency lying approximately in the centre of the pass band of the filter 18. The output from the detector 22 is in turn applied to an integrator 26, the output of which is used to control the frequency of the local oscillator 14.
The components described so far form a phase-lock loop, which controls the frequency of the local oscillator 14 in such a manner as to tend to reduce any D.C. components in the output from the phase-sensitive detector 22 to value such as to maintain the output of the integrator 26 at a constant value. The effect of this is to tend to lock the frequency of one of the I.F. signal components to the frequency of the reference signal. In other words, the loop tends to lock the local oscillator 14 into a predetermined frequency and phase relationship with one of the frequency components of the incoming signal from the aerial 10, such that the frequency difference between that component and the local oscillator frequency is equal to the reference oscillator frequency.
To enable the phase-lock loop to lock on to a predetermined one of the frequency components of the incoming signal, the system contains a signal acquisition circuit, which will now be described.
A D.C. bias signal is applied from a voltage source 28, by way of a gate 30, to the integrator 26. This bias signal causes the output of the integrator to vary linearly with time, and thereby causes the frequency of the local oscillator 14 to be swept through a predetermined range of values. This in turn causes the frequency components of the I.F.
signal from the mixer 12 to be swept in frequency. Thus. if the I.F. frequency components initially lie outside the pass band of the I.F. filter 18, they will be swept into the pass band when the bias signal is applied. As the I.F. frequency components are swept through the pass band of the filter, the phase-lock loop will attempt to lock on to each one in turn as it approaches the frequency of the reference oscillator 24. However the bias signal is set at a value higher than the phaselock loop can overcome, so that the loop does not remain in lock with any of the components, but continues to sweep in frequency.
The output of the reference oscillator 24 is also phase-shifted by 90 by means of a phase-shifter 42, and is compared in a second phase-sensitive detector 44 with the output from the I.F. filter 18. The output from the first phase-sensitive detector 22 is differentiated in a differentiator circuit 46, and then compared with the output from the second phase-sensitive detector 44, by means of a third phase-sensitive detector 48. Finally, the output of the phasesensitive detector 48 is filtered by a low-pass filter 50, and is applied to the input of the integrator 26.
The operation of the system is best appreciated by considering what happens when a single frequency signal is applied to its input from the I.F. filter 18. In this case, the low-frequency outputs from the first and second phase-sensitive detectors 22 and 44 are respectively equal to V sin A wt and V cos A wt, where Aw is the difference between the reference frequency and the input frequency, and V is the maximum D.C. output of the two phase-sensitive detectors. The output from the differentiator 46 is thus equal to:
T. d . (V. sin A wt) = T.V. A w. cos A wt
dt where T is the time constant of the differentiator. Thus, the output from the third phase sensitive detector 48 is equal to:
2 T.V.Aw 8 i.e. is directly proportional to the frequency difference between the input signal and the reference frequency.Thus, it will be seen that the circuit arrangement comprising the phase-shifter 42, phase-sensitive detector 44, differentiator circuit 46, phase-sensitive detector 48 and low-pass filter 50 effectively acts as a frequency discriminator 40 having a centre frequency equal to that of the reference oscillator 24. If the loop is locked on to the main line, the spectrum of the I.F. signal will be disposed symmetrically about the centre frequency of the discriminator 40, and the output of the discriminator will therefore be zero. If however the loop is locked on to one of the sidebands, the spectrum will be asymmetrical relative to the centre frequency of the discriminator 40, and the output will be positive or negative depending on whether the sideband locked on to is higher or lower in frequency than the centre frequency.
The output from the discriminator 40 is applied to the integrator 26, and therefore acts as a bias signal to cause the frequency of the local oscillator 14 to be swept further, in such a manner as to tend to position the I.F. spectrum symmetrically with respect to the centre frequency of the discriminator, so reducing the output of the discriminator to zero. Thus, it will be seen that the discriminator 40 forms, along with the local oscillator 14, mixer 12, amplifier 16, filter 18 and integrator 26, and automaticfrequency-control loop, which controls the frequency of the local oscillator in such a manner as to tend to sweep the main line of the
I.F. spectrum into frequency coincidence with the frequency of the reference oscillator.As the main line approaches the reference oscillator frequency, the phase-lock loop comes strongly into operation, and pulls rapidly into lock with the main line.
One advantage of the discriminator 40 is that if the frequency of the reference oscillator 24 is variable, the discriminator centre frequency varies with the reference frequency. Thus, the circuit effectively provides a variable-centrefrequency. Thus, the circuit effectively provides a variable-centre-frequency discriminator.
Another phase-locked-loop system which, utilises a frequency discriminator to control the frequency of a local oscillator so as to form an automatic-frequency-control loop and thereby cause the phase-locked-loop system to lock onto a frequency component of an incoming oscillatory signal is described and claimed in our co-pending application no.3647/77. Serial
No. 1605246.
WHAT WE CLAIM IS:
1. A phase-lock loop system, for receiving and frequency tracking an incoming oscillatory signal having a plurality of frequency components comprising: a local oscillator producing an output signal which is controllable in frequency; a mixer for multiplying together the output of said oscillator and said incoming signal so as to produce an I.F. signal containing a plurality of
I.F. components; band-pass filter means through which said I.F. signal is passed; a reference oscillator producing a reference signal output; a phase-sensitivite detector for measuring the instantaneous phase difference between said reference signal and the I.F.
signal from said filter means; means for automatically adjusting the frequency of said local oscillator in response to said phase difference as measured by said phase-sensitive detector so as to tend to lock one of said I.F.
components to the reference signal frequency, and thereby establish a predetermined frequency and phase relationship between the local oscillator frequency and said one of the frequency components of the incoming signal; and signal acquisition means comprising: means for causing said local oscillator to scan through a predetermined range of frequencies, so as to tend to bring said I.F. components into the pass-band of said filter; inhibiting means responsive to a rise in the output from said filter, indicating that at least some of said I.F.
components have been brought into said pass band, to inhibit said scanning means so as to prevent further operation thereof; and frequency discriminating means including a phase shifting network connected to the output of said reference oscillator the output of which is connected to a further phase-sensitive detector in which it is compared with the I.F.
signal, the output from the further phasesensitive detector being compared with the differentiated output of the phase-sensitive detector in a yet further phase-sensitive detector the output of said yet further phasesensitive detector being the output of said frequency discriminating means, said frequency discriminating means operating to further scan the frequency of said local oscillator in such a manner as to substantially reduce the output of said frequency discriminating means to zero and thereby cause the phase-lock loop system to lock on to a predetermined one of said frequency componenents.
2. A phase-lock loop system as claimed in
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (4)
- **WARNING** start of CLMS field may overlap end of DESC **.reference frequency and the input frequency, and V is the maximum D.C. output of the two phase-sensitive detectors. The output from the differentiator 46 is thus equal to: T. d . (V. sin A wt) = T.V. A w. cos A wt dt where T is the time constant of the differentiator. Thus, the output from the third phase sensitive detector 48 is equal to:2 T.V.Aw8 i.e. is directly proportional to the frequency difference between the input signal and the reference frequency. Thus, it will be seen that the circuit arrangement comprising the phase-shifter 42, phase-sensitive detector 44, differentiator circuit 46, phase-sensitive detector 48 and low-pass filter 50 effectively acts as a frequency discriminator 40 having a centre frequency equal to that of the reference oscillator 24.If the loop is locked on to the main line, the spectrum of the I.F. signal will be disposed symmetrically about the centre frequency of the discriminator 40, and the output of the discriminator will therefore be zero. If however the loop is locked on to one of the sidebands, the spectrum will be asymmetrical relative to the centre frequency of the discriminator 40, and the output will be positive or negative depending on whether the sideband locked on to is higher or lower in frequency than the centre frequency.The output from the discriminator 40 is applied to the integrator 26, and therefore acts as a bias signal to cause the frequency of the local oscillator 14 to be swept further, in such a manner as to tend to position the I.F. spectrum symmetrically with respect to the centre frequency of the discriminator, so reducing the output of the discriminator to zero. Thus, it will be seen that the discriminator 40 forms, along with the local oscillator 14, mixer 12, amplifier 16, filter 18 and integrator 26, and automaticfrequency-control loop, which controls the frequency of the local oscillator in such a manner as to tend to sweep the main line of the I.F. spectrum into frequency coincidence with the frequency of the reference oscillator.As the main line approaches the reference oscillator frequency, the phase-lock loop comes strongly into operation, and pulls rapidly into lock with the main line.One advantage of the discriminator 40 is that if the frequency of the reference oscillator 24 is variable, the discriminator centre frequency varies with the reference frequency. Thus, the circuit effectively provides a variable-centrefrequency. Thus, the circuit effectively provides a variable-centre-frequency discriminator.Another phase-locked-loop system which, utilises a frequency discriminator to control the frequency of a local oscillator so as to form an automatic-frequency-control loop and thereby cause the phase-locked-loop system to lock onto a frequency component of an incoming oscillatory signal is described and claimed in our co-pending application no.3647/77. Serial No. 1605246.WHAT WE CLAIM IS: 1. A phase-lock loop system, for receiving and frequency tracking an incoming oscillatory signal having a plurality of frequency components comprising: a local oscillator producing an output signal which is controllable in frequency; a mixer for multiplying together the output of said oscillator and said incoming signal so as to produce an I.F. signal containing a plurality of I.F. components; band-pass filter means through which said I.F. signal is passed; a reference oscillator producing a reference signal output; a phase-sensitivite detector for measuring the instantaneous phase difference between said reference signal and the I.F.signal from said filter means; means for automatically adjusting the frequency of said local oscillator in response to said phase difference as measured by said phase-sensitive detector so as to tend to lock one of said I.F.components to the reference signal frequency, and thereby establish a predetermined frequency and phase relationship between the local oscillator frequency and said one of the frequency components of the incoming signal; and signal acquisition means comprising: means for causing said local oscillator to scan through a predetermined range of frequencies, so as to tend to bring said I.F. components into the pass-band of said filter; inhibiting means responsive to a rise in the output from said filter, indicating that at least some of said I.F.components have been brought into said pass band, to inhibit said scanning means so as to prevent further operation thereof; and frequency discriminating means including a phase shifting network connected to the output of said reference oscillator the output of which is connected to a further phase-sensitive detector in which it is compared with the I.F.signal, the output from the further phasesensitive detector being compared with the differentiated output of the phase-sensitive detector in a yet further phase-sensitive detector the output of said yet further phasesensitive detector being the output of said frequency discriminating means, said frequency discriminating means operating to further scan the frequency of said local oscillator in such a manner as to substantially reduce the output of said frequency discriminating means to zero and thereby cause the phase-lock loop system to lock on to a predetermined one of said frequency componenents.
- 2. A phase-lock loop system as claimed inClaim 1, wherein said means for automatically adjusting the frequency of said local oscillator comprises an integrator.
- 3. A phase-lock loop system as claimed in Claim 1 or Claim 2, wherein said scanning means comprises a source of d.c. voltage for application to said integrator and including a gate which said inhibiting signal disables so as to disconnect said d.c. voltage source from said integrator.
- 4. A phase-lock loop system substantially as hereinbefore described with reference to the accompanying drawing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB364877A GB1605247A (en) | 1973-07-24 | 1973-07-24 | Phase-lock loop systems |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB364877A GB1605247A (en) | 1973-07-24 | 1973-07-24 | Phase-lock loop systems |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1605247A true GB1605247A (en) | 1986-01-22 |
Family
ID=9762299
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB364877A Expired GB1605247A (en) | 1973-07-24 | 1973-07-24 | Phase-lock loop systems |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB1605247A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0357080A2 (en) * | 1988-09-02 | 1990-03-07 | Sanyo Electric Co., Ltd. | Phase synchronizing circuit in video signal receiver and method of establishing phase synchronization |
-
1973
- 1973-07-24 GB GB364877A patent/GB1605247A/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0357080A2 (en) * | 1988-09-02 | 1990-03-07 | Sanyo Electric Co., Ltd. | Phase synchronizing circuit in video signal receiver and method of establishing phase synchronization |
| EP0357080A3 (en) * | 1988-09-02 | 1990-11-07 | Sanyo Electric Co., Ltd. | Phase synchronizing circuit in video signal receiver and method of establishing phase synchronization |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| PCNP | Patent ceased through non-payment of renewal fee |