GB1599465A - Line processor - Google Patents

Abstract

In telex exchanges, the telex signals arriving via input lines (1) are diverted to output lines (2) according to the respective existing connections. For this purpose, the input lines (1) are cyclically scanned by a multiplexer (3) and the scan results are combined in a first processing stage (I) to form counting code words and stored in a memory (5). Each counting code word indicates the number of scan values obtained consecutively with no change in polarity during a pre-defined number of scans. In a second processing stage (II), the counting code words are combined to form signal elements and furthermore to form code-addressed words and these words are forwarded to a multiplex bus (15). In the opposite direction, code-addressed words are sent from the multiplex bus (15) via a memory (22) to a transmission processor (18) which converts these words in steps into transmission code words. The transmission code words stored in a transmission counting memory (6) are forwarded in steps via a demultiplexer (4) to the output lines (2). <IMAGE>

Description

(54) A LINE PROCESSOR (71) We, HASLER AG, a Swiss Company of, Belpstrasse 23, 3000 Bern 14, Switzerland, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to a method of multiplexing and demultiplexing binary coded signals such as telegraph code words.

From US patent No. 3,627,945 an arrangement is known for retransmitting asynchronously-arriving binary signals synchronously. The arriving signals are sampled, redundancy in the samples is reduced by logic circuits and the signal words obtained are retransmitted synchronously. Such an arrangement is useful for the input circuits of a telex exchange having a plurality of subscriber lines. It is advantageous to carry out the sampling and logical processing of several signals by first time-division-multiplexing the parallel incoming signals.

In the Hasler Review Vol. 7 (1974) No. 4 three papers are presented, describing a fully electronic telex exchange using the above-mentioned arrangement. In the processing of each sample semipermanently stored line data is used, that is, data representative of the said subscriber line characteristics. Such data includes e.g. the code and the speed used on the line. Temporary data stating the momentary state of the logical processes is also stored.

The data is stored in memories containing storage rows which are each associated with one of the subscriber lines. At each processing step the content of a row is read out and then, after processing, rewritten into the row unaltered or altered.

In this known apparatus, the number of extension lines which can be successively sampled is limited by the time required for processing each sample. Therefore, in the case of a large number of lines, only relatively simple processing steps are possible. Further it is known to select certain samples directly at the sampler and to process further only those selected samples. However, in doing this, some of the received information is lost, especially information indicative of the distortion in the received signals.

It is object of this invention to provide a method whereby the processing time can be reduced considerably compared with the known arrangement.

According to this invention, there is provided a method of multiplexing and demultiplexing binary coded signals, wherein for multiplexing the method comprises: receiving the signals on a plurality of input lines; cyclically scanning the input lines to generate samples for each line, the scanning rate being such that, for each line, a predetermined number (n) of samples is produced during each digital bit of the respective received signal; feeding the samples to a counting circuit which produces a counting code word for each group of n successive samples from each line, which word characterises the group of n samples in terms of blocks of successive samples of the same polarity; converting successive counting code words of each input line to code-addressed words, the conversion process being dependent on stored line data representative of the input line characteristics; and transmitting the code-addressed words onto a bus line; and wherein for demultiplexing the method comprises: receiving code-addressed words from the bus line; splitting each code-addressed word into a succession of counting code words associated with that output line corresponding to the address embodied in the code-addressed word, the splitting process being dependent on stored line data representative of the output line characteristics; transmitting onto the output lines signal elements, each element being prescribed by the corresponding counting code word, the transmitting rate being such that, for each line, n successive elements form one digital bit of a binary coded signal to be transmitted.

The invention will now be described by way of example with reference to the accompanying drawings in which: Figure 1 is a block diagram of a line processor operable in accordance with the invention; Figure 2a is a diagram illustrating the format of a counting code word formed in the line processor, with an example of such a word; Figure 2b is a diagram of a number (18) of successive samples from which the counting code word of Figure 2a is produced; Figure 3 is a flow diagram showing the processing steps for forming a counting code word; and Figure 4 is a flow diagram showing the mode of operation of the line processor as a whole.

The line processor shown in Figure 1 transfers binary-coded characters received from input lines 1 to a multiplex bus line 15 and transfers characters for transmission from the bus line 15 onto the output lines 2.

The line processor consists of two stages, namely the collecting and distributing stage I and the signal processing stage II. Stage I contains a multiplexer 3 and a demultiplexer 4, both of which are connected, via line connection units contained in them, to the lines 1 and 2. Separate lines are shown for transmitting (1) and receiving (2), but the lines can be combined to two-wire line pairs.

The line processor comprises a reception counting store 5 and a transmission counting store 6, both of which have a store row for each input or output line. An address generator 7 constantly produces address signals on the address line 8. Each address is associated with a pair of input and corresponding output lines and the corresponding store rows of the counting stores 5 and 6. Also provided is a reception counting circuit 9, and a transmission counting circuit 10. In each collecting and distributing step an address is called up.

Therewith the corresponding sample value from the multiplexer 3 and the content of the corresponding store row of the reception counting store 5 are transferred to the reception counting circuit 9 for processing. Furthermore the content of the corresponding store row of transmission counting store 6 is transferred to the transmission counting circuit 10 and a character partial element is transferred from this to the demultiplexer 4. At the end of the processing step, changed counting code words are written into the two store rows. These counting code words (the content of the counting stores 5 and 6) represent, on the reception side, the received signal samples obtained since a specific point in time or, on the transmission side the step partial elements of the signals to be transmitted up to a certain point in time.

In this preferred embodiment, 18 samples or step partial elements respectively form a group of samples or elements and each counting code word corresponds to one of these groups in a manner which will be described below with reference to Figures 2a and 2b. Once formed, the counting code words are transferred to a reception buffer store 11 or a transmission buffer store 12 respectively. These two buffer stores form the connection between the collecting and distributing stage I and the signal processing stage II. The transfer of the counting code words to the buffer stores 11 and 12 during a sampling and distributing pause is controlled by a second address generator 13 via a second address line 16.The address generator 13 is synchronised via address line 8 by the first address generator, in such a way that during each eighteen processing steps of stage I one work step of stage II takes its course, for which accordingly a correspondingly longer time is available.

The signal processing stage II contains on the reception side: a reception processor 17 for converting the counting code words into character formats; a character build-up store 19 for the intermediate storage during the building-up the character formats; a character store 21 for the intermediate storage of the finished character formats and an output buffer store 23 for the intermediate storage of the characters, to be fed onto the bus 15. The buffer store 23 works on the principle of a waiting queue.

The transmission side of the signal processing stage II contains: a transmission processor 18 for converting the character formats into counting code words; a character completion store 20 for the intermediate storage during the breaking-down of the character formats; a character store 22 for the intermediate storage of the character formats which have arrived, and an input buffer store 24 for the storage of the character formats, arriving via the bus line 15. The buffer store 24 works on the principle of a waiting queue and transfers the character formats to the character store 22.

Common to both the transmission and reception sides is, apart from the second address generator 13, a line data store 14, which stores on a semipermanently basis the data representing the characteristics of the lines 1 and 2. Apart from the buffer stores 23 and 24, all stores of the signal processing stage II have one store row for each input (1) or output (2) line respectively.

A numerical example will be given hereinunder to make the operations clearer. Let the number of input (1) and output (2) lines be 256. Let each have a transmission speed of 200Bd. Therefore each digital bit of the received or transmitted signals has a duration of 5 ms. If each bit is sampled n times and n = 18, then there are effected during this time, taking together for all channels: 18 x 256 = 4608 samplings, that is 921,600 samples per second. Thus on average one sample is generated every 1.085 Fs. Eighteen successive samples from the same line form a group of samples from which one counting code word is formed. The counting code words are transferred in parallel to the signal processing stage II, so that 18 x 1.085 us = 19.53 Fs are available for processing each counting code word.

The same times apply for the conversion of counting code words into the output signals transmitted onto the output lines 2.

Figure 2a shows the format of a completed counting code word, being completed after eighteen sampling steps. The element values within the boxes are digital 1's and 0's.

Indicated at the top are the location numbers of the counting code word. The time for one group of eighteen samples is equal to the time for one character element. Therefore during this time not more than two polarity changes can occur, even with the highest occurring signal distortion level.

Each completed counting code word has at location number 0 The polarity (A3) of the last sample of the sample group; 1...6 : The binary number (Z3) of samples in the block of samples of the same polarity at the end of the group; 7 The polarity (A2) of the penultimate block of ) samples (this is of opposite sign to A3); 8.. 13 : The binary number (Z2) of samples in the penultimate block; 14 The polarity (Al) of the antepenultimate g if present block; ) 15.20 : The binary number (Z1) of samples in the ) ante-penultimate block. ) Figure 2b shows the group of samples (first sample to the right, last to the left), from which the counting code word of Figure 2a is obtained. The group contains only one polarity change.Accordingly two polarities are entered, the first with seven, the second with eleven bits. Building-up the corresponding counting code word is effected as follows (see flow diagram Figure 3).

Upon each sampling, the sampling value A of one line in the multiplexer 3 and the not yet completed counting code word stored in the corresponding store row of the reception counting store 5 are transferred to the reception counting circuit 9. From the transferred counting code word and the sampling value a new counting code word is formed. This is written back into the same row of the reception counting store 5. In the example of Figures 2a and 2b, the first sampling step (Z3 = 0) produces a polarity value (1) in location 0 and the binary number 1 in locations 1-6 (counting field Z3).With each successive sample of the same polarity (1) from the same line, the number in this counting field is increased by 1 (Z3+1oZ3). If the polarity changes (A 76 A3), then the first polarity (1) is transferred from location 0 to location 7, the binary number from the first counting field (Z3) is transferred into the second counting field (Z2) locations 8 - 13. The new polarity (0) is written into location 0. The digital coded number 1 is written in the first counting field (Z3).

Further samples of the second polarity are counted in the first counting field Cm3). In the case of a possible second polarity change, there is effected once more a shift by seven locations to the left and the counting begins again in the first field (Z3). This is continued until eighteen samples have been counted and thus the counting code word is completed.

This word then is transferred to the reception buffer store 11 and the store counter is set to 0. In each case simultaneously, but in the reverse direction, there is effected the conversion of the counting code words which have been transferred from the transmission buffer store 12 to the transmission counting store 6.

In the signal processing stage II the line data store 14 stores semipermanently the characteristic data of each line. Such data relates to the line speed, the code used (5, 7 or 8 bits per character) etc. The character build-up store 19 and the character completion store 20 store the data which varies with processing. Examples of such data are the indication of a momentary line activity, the line indication of the sampling number (from the start character), the number of the samples taken since the beginning of the last character step, the number of this step in the character, and so forth. During each processing step for one row a counting code word corresponding to that row is transferred from the reception buffer store to the processor 17 together with the corresponding rows of the line data store 14 and the character build-up store 19.Thus a new character format is acquired, and then written back into the same row of the character build-up store 19. If this character format contains a complete character, it is transferred to the character store 21. From there it is transferred via the output buffer store 23 to the bus line 15. In a corresponding manner, characters are transferred via the input buffer store 24 and the character store 22 to the character completion store 20, and converted to counting code words by the transmission processor 18. The timing of the individual steps and the collaboration between stages I and II are shown in the flow diagram of Figure 4. In the first signal processing stage, initially the number m = 0 is entered into a step counter and the address L in the address generator 7 is increased by 1.Then the line associated with the new address is sampled and the word altered in the reception store 5 as described with reference to Figure 3. Similarly, on the transmission side, a character partial element of the polarity determined by the counting code word is sent out on the output line of the same number and the counting code word present in the transmission counting store 6 is correspondingly altered. The m is increased by 1. This happens 18 times.

Simultaneously with the sampling of eighteen rows in the collecting and distributing stage I, one counting code word is processed in the reception and transmission channels respectively of the signal processing stage II. After that there is effected one transfer of a row from the reception counting store 5 to the reception buffer store 11 and from the transmission buffer store 12 to the transmission counting store 16. The rows in the reception counting store 15 are cleared and the address in the second address generator 13 is increased by one, so that in the next processing step the next line is handled.

If the connected lines operate at different speeds the handling of the addresses does not necessarily have to be effected cyclically. The speeds can vary from 50 to 400 Bd. Also the number of samples for one character element may be different for different speeds.

WHAT WE CLAIM IS: 1. A method of multiplexing and demultiplexing binary coded signals, wherein for multiplexing the method comprises: receiving the signals on a plurality of input lines; cyclically scanning the input lines to generate samples for each line, the scanning rate being such that, for each line, a predetermined number (n) of samples is produced during each digital bit of the respective received signal; feeding the samples to a counting circuit which produces a counting code word for each group of n successive samples from each line, which word characterises the group of n samples in terms of blocks of successive samples of the same polarity; converting successive counting code words of each input line to code-addressed words, the conversion process being dependent on stored line data representative of the input line characteristics; and transmitting the code-addressed words onto a bus line; and wherein for demultiplexing the method comprises: receiving code-addressed words from the bus line; splitting each code-addressed word into a succession of counting code words associated with that output line corresponding to the address embodied in the code-addressed word, the splitting process being dependent on stored line data representative of the output line characteristics; transmitting onto the output lines signal elements, each element being prescribed by the corresponding counting code word, the transmitting rate being such that, for each line, n successive elements form one digital bit of a binary coded signal to be transmitted.

2. A method according to Claim 1 wherein each counting code word contains for each said block, elements representative of the polarity of the block and the number of samples in the block.

3. A method according to claim 1 or claim 2 wherein each counting code word comprises three groups of bits, each group corresponding to a said block of samples of the same polarity and having (a) a first portion representing a number and (b) a second portion representing a polarity.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (6)

1. **WARNING** start of CLMS field may overlap end of DESC **.

   12 to the transmission counting store 6.

   In the signal processing stage II the line data store 14 stores semipermanently the characteristic data of each line. Such data relates to the line speed, the code used (5, 7 or 8 bits per character) etc. The character build-up store 19 and the character completion store 20 store the data which varies with processing. Examples of such data are the indication of a momentary line activity, the line indication of the sampling number (from the start character), the number of the samples taken since the beginning of the last character step, the number of this step in the character, and so forth. During each processing step for one row a counting code word corresponding to that row is transferred from the reception buffer store to the processor 17 together with the corresponding rows of the line data store 14 and the character build-up store 19.Thus a new character format is acquired, and then written back into the same row of the character build-up store 19. If this character format contains a complete character, it is transferred to the character store 21. From there it is transferred via the output buffer store 23 to the bus line 15. In a corresponding manner, characters are transferred via the input buffer store 24 and the character store 22 to the character completion store 20, and converted to counting code words by the transmission processor 18. The timing of the individual steps and the collaboration between stages I and II are shown in the flow diagram of Figure 4. In the first signal processing stage, initially the number m = 0 is entered into a step counter and the address L in the address generator 7 is increased by 1.Then the line associated with the new address is sampled and the word altered in the reception store 5 as described with reference to Figure 3. Similarly, on the transmission side, a character partial element of the polarity determined by the counting code word is sent out on the output line of the same number and the counting code word present in the transmission counting store 6 is correspondingly altered. The m is increased by 1. This happens 18 times.

   Simultaneously with the sampling of eighteen rows in the collecting and distributing stage I, one counting code word is processed in the reception and transmission channels respectively of the signal processing stage II. After that there is effected one transfer of a row from the reception counting store 5 to the reception buffer store 11 and from the transmission buffer store 12 to the transmission counting store 16. The rows in the reception counting store 15 are cleared and the address in the second address generator 13 is increased by one, so that in the next processing step the next line is handled.

   If the connected lines operate at different speeds the handling of the addresses does not necessarily have to be effected cyclically. The speeds can vary from 50 to 400 Bd. Also the number of samples for one character element may be different for different speeds.

   WHAT WE CLAIM IS: 1. A method of multiplexing and demultiplexing binary coded signals, wherein for multiplexing the method comprises: receiving the signals on a plurality of input lines; cyclically scanning the input lines to generate samples for each line, the scanning rate being such that, for each line, a predetermined number (n) of samples is produced during each digital bit of the respective received signal; feeding the samples to a counting circuit which produces a counting code word for each group of n successive samples from each line, which word characterises the group of n samples in terms of blocks of successive samples of the same polarity; converting successive counting code words of each input line to code-addressed words, the conversion process being dependent on stored line data representative of the input line characteristics; and transmitting the code-addressed words onto a bus line; and wherein for demultiplexing the method comprises: receiving code-addressed words from the bus line; splitting each code-addressed word into a succession of counting code words associated with that output line corresponding to the address embodied in the code-addressed word, the splitting process being dependent on stored line data representative of the output line characteristics; transmitting onto the output lines signal elements, each element being prescribed by the corresponding counting code word, the transmitting rate being such that, for each line, n successive elements form one digital bit of a binary coded signal to be transmitted.
2. 2. A method according to Claim 1 wherein each counting code word contains for each said block, elements representative of the polarity of the block and the number of samples in the block.
3. 3. A method according to claim 1 or claim 2 wherein each counting code word comprises three groups of bits, each group corresponding to a said block of samples of the same polarity and having (a) a first portion representing a number and (b) a second portion representing a polarity.
4. 4. A method according to any preceding claim, wherein the said conversion of each

   counting code word is performed in a single processing step which occurs simultaneously with, and in the same time interval allocated to the formation of another counting code word from n samples of one input line.
5. 5. A method according to any preceding claim, wherein the binary coded signals are telegraph code words,
6. 6. A method of multiplexing and demultiplexing binary coded signals substantially as herein described with reference to the drawings.