GB1596335A - Differential charge transfer device - Google Patents

Description

(54) A DIFFERENTIAL CHARGE TRANSFER DEVICE (71) We, THOMSON-CSF, a French Body Corporate, of 173, Boulevard Haussmann, 75008 Paris-France, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to devices utilising the transfer of charges in a semiconductor.

More particularly, the invention relates to the use of these devices for the construction of a differential stage and its use in particular for constructing the output stage of a charge-transfer transversal filter.

In a certain number of charge transfer devices (or CTD's), it is necessary to have a differential stage, as is particularly the case with the output stage of transversal filters.

This output stage is conventionally formed by an external differential amplifier or even by MOS-transistors integrated on the same substrate as the filter itself. However, these constructions are attended by various disadvantages, including their bulkiness in cases where the differential stage is not integrated on the same substrate, their high power consumption, the consumption of MOS-transistors being very much greater than that of CTD's, and the non-linearities which can be introduced by the MOStransistors.

In order to obviate these disadvantages, it has been proposed to construct the differential stage by means of CTD's. In particular, it is known to integrate the differential output stage of a filter in the filter (as described for example in the British Patent no 1536020 this integration consisting in the parallel connection of two filters operating in phase opposition. The disadvantages of this solution are chiefly its bulkiness (it necessitates two identical filters) and its special adaptated nature.

According to the present invention there is provided a charge transfer device capable of operating in a differential mode to establish the difference between two electrical input signals, comprising: a semiconductor substrate in which electrical charges can be transferred, at least two channels formed in said substrate and electrically insulated one from the other, arranged for receiving respective ones of said two input signals in use, first means, comprising parallel electrodes arranged for receiving periodic transfer potentials, for producing in each of the channels packets of charges representing samples of the respective signals and for propagating them in the channels in phase opposition when the device is operating in the differential mode, a common electrode positioned on both channels parallel to the electrodes of the first means for detecting a resultant signal proportional to the difference between the two input signals when the device is operating in the differential mode, and means for reading the resultant signal.

For a better understanding of the invention and to show how it can be carried into effect reference will be made to the following description in conjunction with the accompanying drawings, wherein: Figure 1 illustrates one embodiment of the differential device according to the invention, Figures 2a, 2b, 2c show diagrams of signals capable of being applied to the device according to the invention, Figures 3a and 3b are two diagrams illustrating the operation of the device shown in Figure 1, Figure 4 shows one embodiment of an element of the device illustrated in Figure 1, Figure 5 shows a second embodiment of the device according to the invention, Figures 6a, 6b, 6c, 6d show diagrams illustrating the operation of the device illustrated in Figure 5, Figures 7a and 7b show diagrams of signals capable of being applied to the device illustrated in Figure 5, Figure 8 illustrates the application of the device according to the invention to the construction of the reading stage of a charge transfer filter, Figures 9a, 9b, 9c, 9d and 9e show diagrams of signals capable of being applied to the device illustrated in Figure 8, Figure 10 illustrates the application of the device according to the invention to the construction of a charge transfer filter.

In these various Figures, the same reference numerals denote the same elements.

A first embodiment of the device according to the invention is shown in Figure 1.

As is normally the case with CTD's it is formed by a semiconductor substrate (for example silicon) coated with a layer of insulating material (for example silicon oxide) on which electrodes are deposited, substantially parallel with each other.

The semiconductor substrate comprises two channels 1 and 2 which are parallel to and electrically insulated from one another and in which electrical charges are capable of being longitudinally transferred. The insulation of these channels may be obtained by any known means and, in particular, by increasing the thickness of the insulating layer or by locally increasing the doping of the substrate.

In this embodiment, each of the channels 1 and 2 successively comprises a first diode (Dl and D2 respectively), a first electrode (11 and 21, respectively), a second electrode (3) which is deposited onto both channels, a third electrode (12 and 22, respectively) and, finally, a second diode (D3 and D4, respectively). The first diodes Dl and D2 are used for injecting the signals (Sl and S2), the difference between which has to be established, into each of the channels. To this end, they are connected to a common biassing source Vp which is modulated for each of them by the signals Sl and S2, respectively.

Figure 2 (a) shows one example of a potential 81 applied to the electrodes 11 and 22, whilst Figure 2 (b) shows one example of a potential 2 applied to the electrodes 21 and 12 and Figure 2 (c) one example of a potential Vi applied to the common electrode 3 by means of an element L.

The diagram (a) of Figure 2 represents the variation in the potential 8, as a function of time. The function is question is of the square wave type, except that the leading edges of the pulses are for example oblique.

It is a periodic function (period T) and its amplitude varies from V between 81, (low level) and 8,, (high level).

Diagram (b) of Figure 2 shows the variation in the potential 2 as a function of time. The function in question is of the same type and its amplitude varies between 8,, (low level) and 2H (high level). It is preferably identical with l, but phaseshifted by T/2 relative thereto.

Diagram (c) of Figure 2 shows the potential Vl, constant as a function of time and substantially equal to the mean of the upper and lower values of l or 2, that is to V/2 in the case where the amplitude of the signals 8, and Q is equal to V.

The operation of the device illustrated in Figure 1 will be explained with reference to Figure 3 a-b which are sectional views illustrating the transfer of the electrical charges in the channel 1 during the various phases of operation.

Figures 3 show the semiconductor substrate (5) covered by an insulating layer (6) and three electrodes 11, 3 and 12. The substrate 5 is formed with two zones of which the conductivity is opposite to that of the substrate and which form the diodes Dl and D3 with the substrate. The substrate is brought to the most negative potential of the device which forms the reference potential (earth), in relation to which the other potentials are expressed.

It is assumed throughout this description that the semiconductor substrate is of Ptype conductivity and that the charges transferred from electrode to electrode are minority carriers (electrons). Of course, for a substrate of N-type conductivity where the charges are formed by moving holes, the polarity of all the potentials applied must be reversed.

In this embodiment, the charges are injected into the semiconductor as follows.

The diode Dl receives a biassing potential + Vp modulated by the input signal Sl. The corresponding potential level is represented by the line 30 in Figures 3. In a first phase, illustrated by Figure 3a and corresponding to the instant t. in Figu-es 2, the electrode 11 is brought to the potential 0, equal to IH represented by a dotted line 31 in the substrate 5 below the electrode 11.

Simultaneously, the electrode 3 is kept at the constant potential Vl=V/2, represented by a dotted line 33 below the electrode 3.

During this same phase, the potential 2 applied to the electrode 12 is equal to 2B (dotted line 32), as shown in Figures 2a and 2b. The charge carriers supplied by the diode Dl are thus transferred into the adjacent zones under the electrodes 11 and 3 (hatched zone in the diagram) by a process typical of CTD's. The quantities of charges thus present below these electrodes are dependent upon the potential differences between, on the one hand, the potential applied to each of the electrodes and on the other hand, the signal Vp+Sl applied to the injection diode D,. A quantity of charges (denoted by the letter A in the diagram) dependent upon the input signals S, is thus obtained below the electrode 3.

In a second phase illustrated in Figure 3b and corresponding to the instant tb in Figures 2, the potential l is at the low level (#1=#1B, line 32) and the potential Q at the high level (z=QH line 31). The effect of the potential iH applied to the electrode 11 is to prevent the transfer of charges from the diode Dl towards the rest of the device. The effect of the potential Qli applied to the electrode 12 is to transfer the quantity of charges (A) dependent upon the input signal Si and, previously below the electrode 3 to below the electrode 12. These charges may then be collected by the diode D3 to be evacuated.

It can be seen that, by this process, the charges representing the input signal S1 are stored below the electrode 3 during a half period (T/2).

The same injection and charge transfer process takes place in channel 2, but in phase opposition to the preceding process because the electrode 21 is controlled by the signal 02.

The result is that the charges of the channel 1 leave the common electrode 3 when the latter receives the charges of the channel 2. Accordingly, reading of the evolution of the potential or of the current applied to electrode 3 by means of a device L, gives a signal proportional to the difference between the charges propagated in the channels 1 and 2 and, hence between the signals Si and S2.

Figure 4 shows one embodiment of the reading element L in Figure 1. This element enables the potential V,=V/2 to be established at the common electrode 3 and the signal S representing the difference between the signals S, and S2 to be read. This reading is of the voltage reading type. In other words the electrode 3 has to be kept insulated during the arrival of the charges and the signal is obtained from the observation of the evolution of the potential of that electrode.

This element comprises three transistors of the MOS-type (MOST) Tl, T2 and T3 which are connected as follows: one terminal of Tl receives the potential V,; the other terminal of T1 and one terminal of T2 receive the voltage from the electrode 3; the other terminal ofT2 is connected to the gate of T3; the drain of T3 receives an external voltage VD: the source of Ti on the one hand supplies the signal S and, on the other hand, is connected to earth through a resistor R; the gates of Tl and T2 respectively receive a signal Q and its complement If the signal Q is identical with B,, the electrode 3 is brought to the potential Vi during a half period T 2 only. That is not exactly what is shown in Figure 3b, although this does not in any way affect the operation of the device. During the following half period, the electrode 3 is kept insulated from V, and the quantity of charges present below that electrode is read through the sampling MOST T2 (which is controlled by Q). The following MOST T3 provides for a low-impedance output.

In this case where L=I' S=SI-S2. If a signal identical with Q is selected for LX then S=S2-S1.

The device L may even be formed by any means capable of reading a quantity of charges, by current or voltage reading methods. In particular, it may be formed by the device for current reading of charges which is described in British Patent Application No 17578-78 (Serial No ) in the name of THOMSON CSF.

Figure 5 shows a second embodiment of the device according to the invention in which the charges representing the signal are injected by the potential equilibration method.

Figure 5 again shows the two parallel and insulated channels 1 and 2 comprising a diode at each of their ends, namely Dl and D3 in the case of the channel 1 and D2 and D4 in the case of the channel 2. The common electrode 3 is also shown in Figure 5 except that, on this occasion, it is preceded by three electrodes in each channel, namely the electrodes 13, 14 and 15 in the channel 1 and the electrodes 23, 24 and 25 in the channel 2, and followed by one electrode in each channel, namely the electrodes 16 and 26, respectively.

The operation of this device is illustrated in diagrams (a) to (e) of Figure 6 which are each sectional views illustrating the transfer of electrical charges in the channel 1 during the various phase of operation.

These various diagrams show the semiconductor substrate (5) covered by an insulating layer (6) and five electrodes 13, 14, 15, 3 and 16 and also the two diodes D and D3 formed in the substrate 5.

A signal VD5 is applied to the diode Dl, one example of this signal being illustrated in Figure 7b, Figure 7a corresponding to Figure 2a in the interests of clarity. The signal VDS is roughly a square wave, of which the amplitude varies between VB and VH, which has the same duration T as 8,, its lower level (VD5=VDH) being in phase with , and its duration being less than T/2.

Figure 6a corresponds to the instant ti illustrated in Figure 7, where 8,=B,, and VD5=VB and during which the charges are injected into the device. The levels of the potentials are represented by dotted lines: the line 40 corresponding to the level VB of the potential VDS applied to the diode Dl; the line 41 corresponding to a d.c.

potential V X applied to the electrode 13; the line 42 corresponding to the sum of a d.c. potential Vp2 and the input signal Si (t) applied to the electrode 14; the line 43 corresponding to the level IB of the potential l applied to the electrode 15.

In the same way as before, the electrode 3 is common to the two channels and receives the potential V, through the element L. The electrode 16 is connected to l.

During the phase (a), the charge carriers are therefore injected below the electrodes 13 and 14.

Figure 6b corresponds to the instant t2 where l is still at the level 8,,, but where VD assumes the value VN higher than V The effect is that charges only remain below the electrode 14 (hatched zone B in Figure 6b), in a quantity which depends upon the potential difference (Vp2+S1Vp1 and hence upon the input signal Si.

Figure 6c corresponds to the instant t3 where VD5=V and 81=81, (line 45 in Figure 6c). The effect of the increase in the potential of the electrode 15 is to attract the packet of charges B below that electrode by the creation of a depletion zone. Their progression towards the following electrode (3) is not possible because this electrode is kept at the potential Vi (line 46).

Figure 6d corresponds to an instant t4 equal to tl+T. The potential of the electrode 15 returns to the value 8,,, resulting in transfer of the packet B towards the following common electrode 3.

It should be noted that means are provided in the device according to the invention, both in this variant and in the other variants, for ensuring that the charges are propagated in one direction only and for preventing their return in the reverse direction. Means such as these are known: they consist in creating an asymetry at the level of each electrode.

Finally, the propagation of the packet B in this phase Is stopped by the following electrode (16) which is also brought to the potential 01=0,,.

In addition, this phase (d) also represents a charge injection phase for producing another sample C of the signal Si.

During a subsequent phase which is not shown in the Figures, but which takes at a time t,=t3+T, the sample B is transferred from the electrode 3 to the electrode 16, the electrode 16 being returned to the potential 01=0,,.

Accordingly, the injection of charges and the sampling of the signal Si in the channel 1 have just been described. These operations take place similarly in the channel 2, but with a phase shift of T/2 of all the signals applied so as to obtain every half period, the arrival of charges below the common electrode 3 from channel 1 or channel 2.

It should be noted that the relative values of the constant potentials Vpl and Vp3 on the one hand and Vp2 and Vp4 on the other hand are adjusted in order to balance the channels 1 and 2.

The device shown in Figure 5 is therefore a variant of Figure 1 in regard to injection of the charges and sampling of the signals Sl (t) and S2 (t). These two embodiments have of course been described by way of nonlimiting example and any other method of injection and sampling is possible within the scope of the invention.

Figure 8 illustrates the application of the device according to the invention to the construction of the output stage of a CTD filter.

The filter illustrated in Figure 8 is a transversal filter which uses the chargecoupled technique (CCD's). Such filters are described for example in "Transversal Filtering using CTD's" by BUSS et al (IEEE) journal of Solid-State circuits, April 1973, vol. SC 8 No 2p 138.

It is formed on the same semiconductor substrate as the differential device according to the invention and is situated on the left of the line XX in the Figure, the differential stage being situated on the right of that line.

The filter is conventionally formed by an input and sampling stage (not shown) which supplies packets of charges representing the signal to be filtered, to the filter proper, of which the last elements have been illustrated. The filter is for example a two phase filter comprising and array of parallel electrodes split into two parts (82-83, 85-86, 88-89) alternating with an array of parallel unsplit electrodes (81, 84, 87, 90).

The filter terminates in a diode DF formed in the substrate, of which the function is to remove the charges. The unsplit electrodes are connected to a periodic potential0,, whilst the split electrodes are connected to a potential 0,2 in phase opposition to the preceding potential, by means of two elements LF- and LF+, respectively for the upper and lower parts of these split electrodes. The elements LF and LF+ are reading devices for the quantities of charges located below the split electrodes. Like the device L shown in the preceding Figures, it may be formed by any known means and, in particular, as described in British Patent Application No 17578/78 (Serial No ) THOMSON CSF). Each of these elements LF and Lp+ supply a reading signal, S and S+ respectively, which is directed to a differential stage so that the output signal SF of the filter is obtained.

The differential stage may therefore be formed by any of the embodiments described above, the signals S and S+ replacing the signals Si and S2.

Figure 8 shows a variant of the differential device according to the invention which has exactly the same structure as shown in Figure 5, but to which slightly different signals are applied: the diodes Di and D2 are kept at a constant potential VREF; the electrodes 15, 16 and 23 receive the periodic potential 0,; the electrodes 13, 25 and 26 receive the periodic potential Q; the common electrode 3 receives the d.c.

potential Vi through the element L which is formed for example in the same way as shown in Figure 4. But it is no longer controlled by the signal L and its complement, but instead by two separate signals Q1 and Q2. The element L supplies the output signal SF of the filter.

Figure 9 (a to e) illustrates by way of example the shape of the signals which can be applied to the device shown in Figure 8.

In the interests of clarity of the diagrams, the signal l has again been shown: diagram (a) of Figure 9.

Diagram (b) shows the periodic potential . The signal in question is a square wave signal of which the amplitude varies between FIB and ill and which has twice the period (2T) of and is in phase with l.

Diagram (c) shows the periodic potential F2; it is preferably identical with 0,,, but phase shifted by T relative thereto; Diagram (d) shows the periodic potential 0,1. Once again, the signal in question is substantially a square wave signal of duration 2T and in phase with . However, the duration of the high level (LIH) is close to T/2.

Diagram (e) relates to the signal L2- This signal is preferably identical with (d,, but with a phase lag equal to T/2.

By a process typical of charge transfer filters, the packets of charges are transferred from one elctrode to the other in each half period (T) of the signals 0,, and #F2.

It should be noted that, in this device as in the preceding devices, the charges must always be transferred in the same direction both in the filter and also in the differential stage. This result may be obtained by an asymmetry at the level of each electrode.

It will be recalled that the ratio between the surface areas of the split electrodes expresses a weighting coefficient applied to the signal to ensure that the desired filtering is obtained. The quantity of charges present below the split electrodes therefore has to be read by the blocks LF- (electrodes 82, 85 and 88) and LF+ (electrodes 83, 86 and 89).

The signals S and S+ supplied by these blocks are directed towards the differential stage according to the invention. In a manner similar to that described above, the differential stage samples the signal S- in the channel 1 and the signal S+ in the channel 2 in phase opposition. The differential output signal Sp of the filter is obtained at the output end of the element L.

Figure 10 shows another application of the device according to the invention to the construction of filters in which the differential stage comprises a plurality of channels in parallel with one another.

It will be recalled that, to construct a filter by means of a CTD's it is necessary to sample the signal, to pass it through a delay line with discrete stages, to extract it at the level of each stage and to assign it a weighting coefficient dependent upon the required filtering, and then algebraically to add the signals thus obtained to obtain the filtered signal.

Figure 10 shows a CTD delay line 4, an assembly of weighting circuits 8 and then a signal combining stage 7 which supplies the output signal S of the filter.

The delay line 4 is conventionally formed by a semi-conductor substrate covered by an insulating material and then by electrodes 48. One electrode (48) of two is connected to the periodic potential 8,, (shown in Figure 9). The other electrode-is connected to an assembly 50 which, before the phase FI' precharges the capacitances formed by each of electrodes 48, the insulating material and the substrate and then, after the phase 8,,, resets these capacitances to zero. The charges are propagated transversely of the electrodes 48 along an axis OX.

The assembly 50 is formed for example by MOS transistors 49 in series. The electrodes 48 in question are each connected to one common point (51) on two of these transistors 49, the other common point (52) being alternately connected to earth and to the potential V. The gates of the transistors 49 which have a common point 52, are connected one another, the groups thus formed being alternately connected to a periodic zeroing signal (RAZ) and a periodic precharging signal (0,,).

In the Figure, the weighting elements 8 are simple rheostats. They may of course be formed by any other known means, for example of the capacitive type. These elements 8 are connected to that of the electrodes 48 which do not receive the signal Q1.

The stage 7 is constructed in accordance with the diagram shown in Figure 1, but comprises as many insulated and parallel channels 70 as there are weighting elements.

Each of the channels 70 comprises a charge injection diode 72 which receives the signal coming from a weighting element 8, and an electrode 73 to which one of the periodic potentials l and 8, (not shown) is applied, depending on whether the weighting coefficients are positive or negative. The charges which pass through the stage 7 in a direction OZ, subsequently encounter a common electrode 76. Like the electrode 3 of the preceding Figures, this electrode 76 is connected to the element L which receives the signals Vl, Q, and Q2 (see Figure 9) and supplies the output signal S. The channels terminate in an electrode 74 fed by the potential (8, or 8,) (not shown) which does not feed the corresponding electrode 73, and a diode 75 for removing the charges.

The stage 7 may of course be constructed in accordance with another of the embodiments described above.

WHAT WE CLAIM IS: 1. A charge transfer device capable of operating in a differential mode to establish the difference between two electrical input signals, comprising: a semiconductor substrate in which electrical charges can be transferred, at least two channels

Claims (10)

**WARNING** start of CLMS field may overlap end of DESC **. electrode 73 to which one of the periodic potentials l and 8, (not shown) is applied, depending on whether the weighting coefficients are positive or negative. The charges which pass through the stage 7 in a direction OZ, subsequently encounter a common electrode 76. Like the electrode 3 of the preceding Figures, this electrode 76 is connected to the element L which receives the signals Vl, Q, and Q2 (see Figure 9) and supplies the output signal S. The channels terminate in an electrode 74 fed by the potential (8, or 8,) (not shown) which does not feed the corresponding electrode 73, and a diode 75 for removing the charges. The stage 7 may of course be constructed in accordance with another of the embodiments described above. WHAT WE CLAIM IS:

1. A charge transfer device capable of operating in a differential mode to establish the difference between two electrical input signals, comprising: a semiconductor substrate in which electrical charges can be transferred, at least two channels formed in said substrate and electrically insulated one from the other, arranged for receiving respective ones of said two input signals in use, first means, comprising parallel electrodes arranged for receiving periodic transfer potentials, for producing in each of the channels packets of of charges representing samples of the respective signals and for propagating them in the channels in phase opposition when the device is operating in the differential mode, a common electrode positioned on both channels parallel to the electrodes of the first means for detecting a resultant signal proportional to the difference between the two input signals when the device is operating in the differential mode, and means for reading the resultant signal.

2. A device as claimed in claim 1, wherein said first means comprise for each channel a charge injection diode, which receives one of said input signals, and a first electrode positioned between said diode and said common electrode, receiving a first of said transfer potentials said common electrode receiving a constant potential which is lower than the amplitude of said first transfer potential.

3. A device as claimed in claim 2, wherein each of said channels further comprises, in the path of said charges after said common electrode, a second electrode and a further diode, said second electrode receiving a second of said transfer potentials, in phase opposition to said first transfer potential.

4. A device as claimed in claim I, wherein said first means comprise for each of said channels a charge injection diode and three electrodes which are placed parallel to one another between said injection diode and said common electrode, said common electrode receiving a constant potential which is lower than the amplitude of a first of said transfer potential received by the electrode preceding it.

5. A device as claimed in claim 4, wherein each of said channels further comprises, in the path of said charges after said common electrode, a fourth electrode and a further diode, said fourth electrode receiving said first transfer potential.

6. A device as claimed in claim 4, wherein in each channel, said injection diode receives a first periodic potential of period T, the second of said three electrodes receives one of said input signals, and the third of said three electrodes receives said first transfer potential.

7. A device as claimed in claim 4, wherein in each channel, the first of said three electrodes receives a second of said transfer potentials, which is in phase opposition to said first transfer potentials the second of said three electrodes receives one of said input signals, and the third of said three electrodes receives said first transfer potential.

8. A devices claimed in claim 1, wherein said means for reading said differential signal are formed by first and second transistors of the MOS type connected in series, the common terminal of these transistors being connected to said common electrode, the gates of these transistors each receiving a periodic potential, of which the one is phase-shifted in relation to the other, the other non-common terminal of said first transistor receiving a substantially constant potential and the ocher non-common terminal of said second transistor being connected to the gate of a third transistor of the MOS type, which supplies said output signal.

9. A charge transfer filter comprising: a semiconductor substrate; an insulating layer deposited on the substrate; electrodes deposited on the insulating layer which are alternately split into two parts and non-split and which, according to the application of defined periodic potentials ensure the transfer of charges in the semiconductor; means for reading the quantities of charges present below said parts of the split electrodes; a differential device of the type claimed in claim 1 formed on the same said semiconductor substrate as the rest of the filter, the said two input signals being supplied to said differential device by said reading means.

10. A charge transfer filter for filtering an

input signal, comprising: a charge transfer delay line comprising a semiconductor substrate covered with an insulating layer which carries electrodes ensuring, by the application of defined periodic potentials, the transfer in the substrate of charges which represent said input signal; weighting elements which are connected to different points of said delay line and each of which multiplies the signal existing at one of those points by a given coefficient; a charge transfer device of the type claimed in claim 1, comprising as many insulated channels as there are weighting elements, said channels being connected by said common electrode.

Il. A charge transfer filter substantially as herein before described with reference to Figures 1 to 4 or Figures 5 to 7 or Figures 8 and 9 or Figure 10 of the accompanying drawings.