GB1595778A - Frequency response equalizer - Google Patents

Description

(54) FREQUENCY RESPONSE EQUALIZER (71) We, AMPEX CORPORATION, a Corporation organised and existing under the laws of the State of California, United States of America, of 401 Broadway, Redwood City, State of California, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The invention relates to a frequency response equalization circuit particularly suitable for magnetically recorded and reproduced signals where phase linearity over a wide frequency range is required.

According to the present invention, a frequency response equalizer includes a differentiating means and integrating means that are coupled to receive a reproduced signal provided by a reproduce head. The differentiating means provides a differentiated signal having a substantial 90" phase lead with respect to the reproduce signal, while the integrating means provides an integrated signal having a substantial 90" phase lag with respect to the reproduce signal. A differential means provides a difference signal of the differentiated and integrated signals. The resulting difference signal is amplitude and phase-equalized with respect to the reproduce signal for all reproduce signal frequencies.

In one embodiment of the frequency response equalizer, a signal from a reproducing head and preamplifier combination is fed as an input signal to a parallel combination of an integrating and differentiating circuit. The integrating circuit provides an output signal having a phase lag of 90" while the differentiating circuit provides an output signal having a phase lead of 90" with respect to the input signal. A difference of the respective output signal is provided by a subtraction circuit. The signal at the output of the subtraction circuit is either in phase with respect to the originally recorded signal or inverted with respect thereto, depending on the particular polarities of the respective output signals from which the difference signal is obtained.

Because of the well-known property of magnetic reproducing heads that the reproduced signal is a time differential of the recorded flux, the output voltage from the reproduce head and associated preamplifier circuit has a substantial 90" phase lead with respect to the phase of the magnetic flux recorded on the storage medium. Thus, the difference signal provided by the frequency response equalization circuit has a constant phase shift of O" or 1800 that is, it is in phase or inverted with respect to the recorded magnetic flux depending on the direction of the 90" phase shift introduced by the equalizer. Consequently, the overall phase response of the resulting equalized frequency channel exhibits the required phae linearity over the entire frequency range of the channel.

Simultaneous with providing phase equalization, the frequency response equalizer also provides amplitude equalization of the signal transmitted through the recording/reproducing channel. It is well known in the art that the amplitude response of a reproducing head follows a 6dB/octave rise which decreases at both low and high frequency ends of the amplitude characteristic due to various signal losses (refer to Figure 4 of the drawings). The present equalizer compensates for the above-mentioned non-constant amplitude response and losses by providing a complementary frequency response as follows. The integrating circuit of the equalizer provides a low frequency boost at a rate of 6dB/octave while the differentiating circuit provides a high frequency boost at the same rate. By linearly subtracting the amplitude response of one of the circuits from the other one, a resulting characteristic (see diagram of Figure 5) is obtained which, combined with the reproduce head characteristic (see diagram of Figure 4), yields a resulting flat overall amplitude response throughout the entire frequency range of the channel.

In the accompanying drawings: Figure 1 is a block diagram of a reproducing circuit which includes the frequency response equalization circuit of the invention; Figure 2 is a block diagram including a preferred embodiment of the invention; Figure 3 is a block diagram including another preferred embodiment of the invention; Figure 4 is a graph showing the playback response of a conventional reproduce head and preamplifier combination circuit; Figure 5 is a graph showing an equalization characteristic provided by the frequency response equalization circuit of the invention which characteristic compensates for the playback response of Figure 4; and Figures 6A and 6B are two consecutive parts of a detailed schematic electrical circuit diagram of still another preferred embodiment of the invention.

Various features of the recording and reproducing system in which the present invention may be, though not necessarily, employed are described and claimed in our copending applications Nos. 8018055 (Serial No. 1595771); 8018056 (Serial No. 1595772); 8018191 (Serial No 1595773); 8018192 (Serial No. 1595774); 8018193 (Serial No. 1595775); 8018385 (Serial No. 1595776); 8018386 (Serial No. 1595777); 8018563 (Serial No. 1595779) and 8018564 (Serial No. 1595780); (likewise divided out of 45195/76, now abandoned).

Figure 1 shows a portion of of the record/playback channel, including a reproduce head 1008 coupled to a preamplifier 1009, the combination of elements 1008 and 1009 being designated as block 1001. The magnetic flux patterns recorded on a disc surface are picked-up by the reproduce head 1008 and amplified by the preamplifier 1009. Due to the differentiating action of the reproduce head, which is well known in the magnetic recording art, the output signal of block 1001 at terminal 1006 is a voltage proportional to the time-derivative of the recorded flux. Hence. the transfer function of block 1001 in the conventional symbolic notation of the Laplace transformation is k1s kls (1) where G; is a complex transfer function k1 is a gain constant. and s is the complex Laplace variable.

Note: With respect to the above-indicated symbolic notations G; k; s: these will be maintained throughout the specification while only the indexes thereof will be changed, indicating specific circuits to which the notations pertain. In the following equations symbolic notations R,C with indexes attached thereto indicate respective resistance and capacitance values pertaining to corresponding circuit elements indicated by identical notations and indexes in the specification and drawings.

To the output of block 1001 of Figure 1, an equalization circuit 1000 is coupled, the latter circuit being shown in an idealized form suitable for theoretical explanation of the equalization operation which follows. The equalization circuit 1000 has an input terminal 1006, to which the output signal of block 1001 is fed. To the input terminal 1006, inputs of an integrating circuit 1002 and a differentiating circuit 1003 are coupled, respectively. The transfer function of the integrating circuit is G2 k2/s (2) and the transfer function of the differentiating circuit is G3 k3s (3) In the differentiating signal path, a variable gain control circuit 1004 is shown which enables to change linearly the high frequency boost effected by the differentiating circuit 1003, as it will be explained later in more detail. The difference of the respective output signals of the integrating and differentiating circuit is taken, as it is schematically shown by a subtraction circuit 1005. The resulting difference signal at output terminal 1007 of the equalization circuit 1000 is the required amplitude and phase-equalized signal with respect to the input signal at terminal 1006. The resulting record/playback channel has an overall flat amplitude response and linear phase response for all transmitted signal frequencies, as will be seen from the more detailed description below.

The overall transfer function of the portion of the record/playback channel shown in Figure 1 comprises block 1001 and the equalization circuit 1000 coupled thereto is Govern = G1 (G2 - G3) (4) and after substituting for G1, G2 and G3 from (1), (2) and (3) Goverall = kls (k2/s - k3s) = klk2 (1 - k3 S2) (5) 2 When substituting s = jw, the following is obtained Goveraii (jw) = k1k2 (1 + k3 w2) (6) 2 The overall phase shift introduced by the portion of the record/playback channel shown in Figure 1 is determined by phase of G(jw) = arctan Im go (j G (jw) Re U (jw) (7) Since the expression on the right side of equation (6) is a real number (the imaginary part being zero), the overall phase shift determined by equation (7) is zero. At zero phase shift, the requirement of a linear phase response for all frequencies transmitted through the channel is satisfied.

It is essential for the equalization circuit to provide a difference signal at the output terminal 1007, rather than a sum of the respective output signals of the integrating and differentiating circuit. Each of the latter circuits introduces an equal phase shift of 90" but opposite in sense, lagging in the integrator and leading in the differentiator. Thus, the respective output signals of circuits 1002 and 1003 in Figure 1 are out of phase by exactly 1800 with respect to each-other and a difference signal yields a resulting signal combination, for which the respective signal amplitudes are added together, rather than subtracted from each other. Besides that, a 900 phase shift of the integrator output signal combined with the +90 phase shift of the differentiating action of the reproduce head yields an 0 overall phase shift. On the other hand, the +90 phase shift of the differentiator output signal combined with the + 90" phase shift of the differentiating head yields a 1800 overall phase shift which is simply an inversion. Whether the resulting overall phase shift of the record/reproduce channel is 0 or 1800, that is, whether the output signal at the terminal 1007 is in phase or inverted with respect to the polarity of the recorded flux, depends on the sense of the 90" phase shift introduced by the equalizer 1000 as it will be described later in more detail.

Besides providing a linear phase response for all the frequencies transmitted through the channel, the equalization circuit also compensates for the non-constant amplitudefrequency response of the reproduce head, as it will be disclosed below. As it is well known in the art, the output voltage of the reproduce head 1008 and preamplifier 1009 combination of Figure 1 rises at low freqencies at a rate of 6dB/octave, levels off at mid-band frequencies and falls at high frequencies. Such an amplitude response is shown as an example at GR in Figure 4. Consequently, if an overall flat amplitude response of the record/playback channel is to be obtained, it is necessary for the equalizer to boost the amplitude at both low and high frequencies. This required equalizer characteristic is obtained by the circuit of Figure 1 in a following manner. As an example, Figure 5 shows a graph representing the gain G2 of the integrating circuit 1002 and the gain G3 of the differentiating circuit 1003 in dB, respectively, as dependent on freqency, the frequency values being plotted on a logarithmical scale. The characteristic G2 falls and the characteristic G3 rises with frequency at a rate of 6dB/octave. There are also shown diagrams of two other transfer functions G'3 and G"3 of the differentiating circuit, representing linear variation of these functions with variation of the gain control circuit 1004 output signal, as it will be described in more detail later. At GE a resulting transfer functon of the equalization circuit 1000 is shown, obtained by adding the linear magnitudes G2 and G3. It can be seen that the transfer characteristic GE of the equalization circuit 1000 is complementary to the transfer characteristic GR of the reproduce head. Consequently, when combining the two characteristics GR and GE, as it is provided by the circuit shown in Figure 24, the equalizer characteristic GE compensates for the departures from flatness of the reproduce head characteristic GR both at low and high frequencies and an overall flat amplitude characteristic results.

There is an additional advantage provided by the presently described equalization circuit which allows linearly varying the amount of high frequency boost provided by the differentiating circuit. For this purpose a variable gain control circuit is utilized in the differentiating signal path, shown for example at 1004 in Figure 1. By adjusting the gain of the differentiating signal path by means of circuit 1004, the frequency at which the high frequency boost of the equalizer amplitude response begins may be changed. For this purpose a variable resistor or potentiometer may be utilized or in case an amplifier is employed in the differentiating signal path, the gain of that amplifier may be changed in a well known manner, as it will be described in connection with the embodiment of Figure 3.

The group of curves G3, G3', G"3 shown in Figure 5 is obtainable for three different values of gain provided by the differentiator 1003 in Figure 1 and adjusted by the variable gain control circuit 1004. The gain adjustment affects only the gain constant k3 in the transfer function (3) presented above and therefore, it changes only the corner frequency at which the high frequency boost begins, in accordance with the formula for the corner frequency

As the corner frequency increases, the amount of signal amplitude boost decreases linearly as the curves obtained move from G3 to G'3 to G", etc. Increasing the amplitude boost linearly at the high frequencty end of the equalizer response is an important feature because it enables to compensate, for example, for changes in the relative head-to-recording medium speed, such as due to the variations in track length of a magnetic disc. When recording digital signals on magnetic disc, this feature permits compensation for higher density of recorded bits, also called pulse crowding which occurs on the inner tracks of the disc.

Examples of practical implementation of the above-described idealized form of the equalization circuit shown in Figure 1 are shown in the form of block diagrams in Figures 2 and 3. Elements similar to those previously described and shown in Figure 1 are designated in Figures 2 and 3 by the same reference characters as in Figure 1. With respect to the relatively low signal level at the output of playback amplifier 1009, it is necessary for practical purposes to amplify the signal in both the integrating signal path as well as in the differentiating signal path. Thus, in the diagram of Figure 2 the integrating circuit of Figure 1 is implemented by inverting integrating amplifier circuit 1002, comprising an inverting operational amplifier 1010, a negative feedback capacitor C1 and a series input resistor R1.

On the other hand, the differentiating circuit of Figure 2 is implemented by an inverting operational amplifier 1011, a negative feedback variable resistor R. and a series input capacitor C. The variable resistor R2 represents a variable gain control for the differentiating signal path. The transfer function of the integrating amplifier circuit 1002 of Figure 2 is: G2 - Ricks (9) When comparing equation (9) with (2) we obtain k2 z- - 1 (10) R1C1 The transfer function of the differentiating amplifier circuit 1003 of Figure 26 is G3 - R2C2s (11) When comparing equation (11) with (3) we obtain k3 - R2C2 (12) The subtraction of Figure 1 is implemented in the circuit of Figure 2 by a differential amplifier 1005. The output of the inverting integrating circuit 1002 is coupled to an inverting input of the differential amplifier 1005 while the output of the inverting differentiating circuit 1003 is coupled to a non-inverting input of amplifier 1005. The output signal at terminal 1007 is the difference signal which also represents the equalized signal of the recording/reproducing channel. The resulting equalized signal has 0 phase difference with respect to the signal recorded on the magnetic medium, that is, it is in phase therewith.

Thus, the phase response of the overall channel becomes linear when the equalization circuit 1000 is utilized.

However, the circuit of Figure 2 is still considered idealized to the extent that exact implementation of the above transfer functions (9) and (11) would require unlimited gain in the integrating amplifier circuit 1002 at low frequencies and in the differentiating amplifier circuit 1003 at high frequencies. In practical applications both these extremities are avoided, for example, by adding a shunt register R" to C1 and a series register R' to C2 as shown in Figure 2, to truncate the respective integrating and differentiating approximations at selected frequencies below and above the frequency range of interest. Considering the presence of the respective resistors R', R" in the circuit of Figure 2, the respective transfer functions G2, G3 will be G2 - k2 (13) 1 s + R"C1 U3 - k3 s (14) R'C2 1 s + R'C2 where R1, R2, R', R", Cl and 2 are component values pertaining to corresponding circuit elements.

When considering in equation (13) R"C,s 1 - > > > 1 (15) R"C1 We obtain Go - k2 (16) s which is identical to the transfer function of (2).

When considering in equation (14) R'C2s < < 1 - > s < < 1/R'C2 (17) we obtain G3 - k3s (18) which is identical to the transfer function of (3).

It follows from the above discussion that when substituting for s=jw, the respective transfer functions of the integrating and differentiating circuit of the equalization circuit 1000 shown in Figure 2 will approach that of an ideal integrator and differentiator in the frequency range 1 1 R"C1 w R'C2 (19) In Figure 3 another example of practical implementation of the equalization circuit is shown. The integrating circuit of Figure 1 is here implemented by a passive integrating network 1002 comprising series resistor RA and parallel capacitor CA followed by a non-inverting amplifier 1012 providing the necessary amplification in the integrating signal path. Analogously, the differentiating circuit of Figure 1 is implemented in Figure 3 by a passive differentiating network 1003 comprising a series capacitor Ca and a parallel resistor RB followed by a non-inverting amplifier 1013 providing the necessary amplification in the differentiating signal path. Similarly as in the circuit of Figure 2 the subtraction circuit is implemented by a differential amplifier 1005. In the circuit of Figure 3 the integrated and subsequently amplified signal at the output of amplifier 1012 is fed to a non-inverting input of the differential amplifier 1005, while the differentiated and subsequently amplified signal at the output of amplifier 1013 is fed to an inverting input of amplifier 1005. The output signal at terminal 1007 of the circuit in Figure 3 is the resulting difference signal which represents the equalized signal of the record/playback channel. The resulting equalized signal has a 0 phase difference with respect to the signal recorded on the magnetic disc.

Thus, the phase difference caused by the presently described equalization circuit does not introduce non-linearities in the phase response of the overall channel, but to the contrary, it yields an overall linear phase response.

The respective transfer functions of the integrating and differentiating circuit of Figure 3 are A2 CAS A2 Rsi + 1 RACY s A2 (20) AS RB A3RBCBS G3 # A3 = Rg RB + 1 1 + RBCBS (21) Qs where A2 is the gain of amplifier 1012 and A3 is the gain of amplifier 1013.

When comparing equation (20) with (2) we obtain for w > > l/RACX k2 = A2 (22) RACA when comparing equation (21) with (3) we obtain for w k3 = A3RBCB (23) A potentiometer 1014 in Figure 3 connected to the amplifier 1013 in the differentiated signal path represents a variable gain control circuit. By adjusting the gain A3 of amplifier 1013, the gain constant k3 expressed by (23) and the corner frequency of the boost changes as it has been described above in connection with the description of Figure 5 and equation (8).

A detailed electrical circuit diagram of the data detector and equalizer 99 is shown as an example in consecutive Figures 6A and 6B and will now be described. In the video frame storage recording and reproducing system, a color television signal is encoded in digital form and recorded on a magnetic disc. Upon playback, the digital data is reproduced by a reproduce head and amplified by a reproduce preamplifier 1009 (reproduce head and preamplifier are not shown in Figures 6A and 6B. Figures 6A and 6B show two identical playback equalizer and data detector circuits utilized for the ten separate data streams received from the disc drive data interface 151. However, only one of these circuits will be described. In the circuit of Figures 6A and 6B the preamplified playback data in the channel encoded format, equalized by an equalization circuit 1000 corresponding to the abovedescribed equalization circuit with reference to Figures 1 to 3. The equalized signal is filtered in a low pass filter circuit 1018, and thereafter amplified and amplitude limited to produce a rectangular pulse sequence in an amplifier-limiter circuit 1019. The pulse sequence from the limiter is fed through a pulse former circuit 1020 which forms output pulses for each detected signal transition. The pulses from circuit 1020 are fed to the data decoder and time base corrector circuitry 100 which decodes and removes timing errors from the playback data from which the original color television signal is recovered.

As shown in Figures 6A and 6B, the playback data from the preamplifier is applied to differential input terminals 1021 and 1022 of a differential amplifier 1033, such as manufactured by RCA, type CA 3004. This type of amplifier contains open-collector differential output transistors connected to output terminals 1034 and 1035. Resistor 1036 is the load resistor for the non-inverting output terminal 1034. The gain of the amplifier 1033 to output terminal 1034 is constant throughout the frequency range of interest. The non-inverted signal is buffered by emitter follower 1037 and then applied to a differentiating network 1003 comprising capacitor 1038 and resistor 1039. This network 1003 performs differentiation for signal frequencies below 60 MHz. Its transfer function is R R (1039)C(1038)s 22 G3 = 1 + (R1039)C(1038)s and for w < R(1039)C(1038) G3 R(1039)C(1038) s (23) Equation (23) corresponds to previously discussed equation (3) related to the block diagram of Figure 1 where k3=R( 1039)C(1038). Since signals of interest in this particular embodiment extend only to about 10 MHz, this network 1003 may be viewed as a true differentiator. The output of the differentiator 1003 is applied to input terminal 1040 of differential amplifier-multiplier circuit 1041, such as manufactured by Motorola, type MC1496. Input terminals 1040 and 1042 of the circuit 1041 are differential input terminals biased by connection to +7.5V. The amplifier-multiplier 1041 receives a second input signal at differential input terminals 1043 and 1044 and at output terminal 1045 an output current is provided proportional to the negative of the product of the input signals at terminals 1040, 1042 and 1043, 1044. In the present circuit a direct current gain control voltage is applied to input terminal 1043, while terminal 1044 is grounded. The control voltage at 1043 corresponds to an output voltage from a remote variable gain control circuit (not shown on Figure 6A), such as previously described in connection with circuit 1014 of Figure 3. In the presently described embodiment of the frequency equalizer, the gain of the circuit 1041 in the differentiated signal path is remotely and automatically controlled by a digital-to-analog converter to obtain desired gain variations dependent on the variations of the recording track length of the magnetic disc. A particular track number (corresponding to a specific track length) from which a particular data is being reproduced is decoded in a digital decoder and converted in the digital-analog converter to a direct current voltage level which is then applied as a gain control signal to input terminal 1043 of circuit 1041. As it has been mentioned before, the variable gain adjustment in the differentiated signal path is designed to compensate for higher pulse density on inner tracks of the disc while linearity of the high frequency boost of the equalized signal is maintained for the entire frequency band transmitted.

The magnitude of the current at output terminal 1045 of the amplifier-multiplier circuit 1041 is proportional to the input signal at input terminal 1040 and to the gain value determined by the control voltage at terminal 1043. The output current from terminal 1045 of the circuit 1041 is applied as an input current to the emitter of a common-base transistor amplifier serving as the subtraction circuit 1005 which has been previously described and shown in Figures 1, 2 and 3. This input current produces an output voltage at the collector of the amplifier which is proportional to both the input current and resistance of the collector load resistor 1047. Thus, the above-indicated part of the transistor 1005 output voltage is proportional to the negative of the signal derivative amplified by the amplifier-multiplier circuit 1041.

The inverting output terminal 1035 of the differential amplifier 1033 has a load resistor 1048 and a parallel load capacitor 1049. The direct current gain of the amplifier 1033 to output terminal 1035 is higher than the gain to the non-inverting output terminal 1034 by the ratio of the respective load resistances R1049/C1036, that is, by the factor of about 3.

For signal frequencies above 80 kHz the gain to output terminal 1035 is determined by 1049 and is inversely proportional to the frequency. Thus, the output circuit R1048, C1049, connected to terminal 1035 functions as an integrating network for frequencies above 80 kHz and throughout the frequency range of interest which is approximately from 0.3 MHz to 10 MHz The transfer function of the amplifier 1033 to the output terminal 1035 is G1033 = - 3A1033 (R 1 ( 1048) C (1049)sol (24) where A1033 is the gain of the differential amplifier 1033 to output terminal 1034.

For w > - ~~~~~~~~~~~~ R(1048)C(1049) (25) U1033 - 3A11133 1048) 1049)s (25) Equation (25) corresponds to previously discussed equation (2) related to the block diagram of Figure 1, where k2 = -3A11)33 R(1048)C(1049) The inverted and subsequently integrated signal from the output terminal 1035 of amplifier 1033 is applied to the common emitter transistor amplifier 1005. Transistor 1005 inverts this input signal and multiplies it by the ratio of its respective collector and emitter load resistances R1047/R1050. The transistor 1005 operates as a common emitter amplifier in the integrating signal path and as a common base amplifier in the differentiating signal path. The resulting output signal at the collector of transistor 1005 is the sum of two input signal contributes, one proportional to the integral of the playback signal from the reproduce head and preamplifier combination, the other one proportional to the negative of the derivative of the playback signal. Thus, the resulting output signal at the collector of transistor 1005 corresponds to a difference signal, such as previously described with reference to the output signal at the output terminal 1007 of the previously described embodiments of the equalization circuit shown in Figures 1, 2 and 3. Thus, the output signal of the equalization circuit 1000 of Figures 6A and 6B corresponds to the equalized signal of the record/playback channel as previo low pass filter circuit 1018 and thereafter fed through a first buffer amplifier 1051, such as type MC10116P, of an amplifier-limiter circuit 1019. The output signal from the buffer amplifier is fed through a series of five amplitude-limiting amplifiers, preferably of the same type as the buffer amplifier. The equalized playback signal provided at the input of the amplitude-limiting circuit 1019 is in the channel encoded form with the transitions properly positioned. Amplitude limiting the playback signal serves to restore the rectangular shape of the playback data signal which has been considerably distorted by the record and reproduce processes. Furthermore, the amplitude-limiting circuit 1019 also serves to provide opposite phased waveforms of the restored data signal which are subsequently used to generate a pulse for each transition of the rectangularly shaped channel encoded playback data signal.

To generate a pulse for each transition of the playback data signal so that only leading, positive edges of the pulses identify the data signal transitions, the amplifier-limiter circuit 1019 provides two opposite phased waveforms of the data signal. First, a rectangular pulse sequence of non-inverted polarity is provided at the output terminal 1052 of the last amplifier 1053 of the series of amplitude-limiting amplifiers and second, an identical pulse sequence of inverted polarity is provided at the output terminal 1054 of the same amplifier 1053. Both these pulse sequences are applied respectively to two identical one-shot multivibrators 1055 and 1056, such as type MC10131L of the pulse former circuit 1020.

Each multivibrator forms a positive pulse, respectively, for each positive going transition of the playback data signal received at its clock input. Consequently, the one-shot multivibrator 1055 receiving the non-inverted form of the playback data signal provides a positive pulse at each positive going transition in the data signal. On the other hand, the other one-shot multivibrator 1056 receiving the inverted form of the playback data signal provides a positive pulse at the location of each negative going transition in the data signal.

Since the leading edges of the positive pulses generated by the multivibrators 1055 and 1056 are defined by rapidly switching the multivibrators from its stable state to its quasi-stable state (there being no significant time constant determining components involved), each leading edge will be identical to all others and occur at a precise time following the occurrence of the positive clocking transition of the playback data signal. Because the transmission channel over which the pulses are sent will act on identical pulse edges the same, the locations of the transition-related positive pulse edges, hence, data signal transitions themselves, are not lost as a result of any distortion that may be introduced to the pulses by the action of the transition channel.

For transmission of the transition related pulses, the output pulses of both one shot multi-vibrators 1055 and 1056 are applied to separate inputs of a postive OR-gate 1057 which forms an output pulse for each input pulse. The output pulses of the OR-gate 1057 are applied to the disc drive data interface 151 for onward transmission.

WHAT WE CLAIM IS: 1. Apparatus in which a magnetic playback head provides a signal which is the time differential of recorded magnetic flux and in which this signal is transmitted through a channel of non-constant amplitude response to varying frequency and non-linear phase response to varying frequency, the apparatus including an equalizer comprising a parallel combination of a low-pass integrating circuit and of a high-pass differentiating circuit, both said circuits having inputs coupled to an output of said magnetic reproduce head, each said circuit having respective outputs providing output signals having respective phase shifts of substantially 90 , equal in magnitude and opposite in sense with respect to said signal provided by said reproduce head; and means providing a difference signal of said output signals, said difference signal being amplitude and phase equalized with respect to said provided by said reproduce head, the resulting equalized channel having a constant amplitude response and a linear phase response for all signal frequencies transmitted therethrough.

2. Apparatus according to claim 1, further comprising a gain adjustment circuit coupled to said differentiating circuit to provide a linear variation of a high frequency amplitude boost effected by said differentiating circuit with frequency while maintaining an unchanged low frequency amplitude boost effected by said integrating circuit.

3. Apparatus according to claim 1, wherein the low pass integrating circuit comprises a first inverting operational amplifier, a negative feedback capacitor, and a series input resistor, the high pass differentiating circuit comprises a second inverting operational amplifier, a negative feedback resistor, and a series input capacitor, said first and second amplifier having their respective inverting inputs coupled to receive said reproduce signal, and the means providing the difference signal comprises a differential amplifier having its inputs coupled to respective outputs of said first and second operational amplifier.

4. Apparatus according to claim 3 wherein said negative feedback resistor of said second inverting operational amplifier is a variable resistor for adjusting the gain provided

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (8)

**WARNING** start of CLMS field may overlap end of DESC **. low pass filter circuit 1018 and thereafter fed through a first buffer amplifier 1051, such as type MC10116P, of an amplifier-limiter circuit 1019. The output signal from the buffer amplifier is fed through a series of five amplitude-limiting amplifiers, preferably of the same type as the buffer amplifier. The equalized playback signal provided at the input of the amplitude-limiting circuit 1019 is in the channel encoded form with the transitions properly positioned. Amplitude limiting the playback signal serves to restore the rectangular shape of the playback data signal which has been considerably distorted by the record and reproduce processes. Furthermore, the amplitude-limiting circuit 1019 also serves to provide opposite phased waveforms of the restored data signal which are subsequently used to generate a pulse for each transition of the rectangularly shaped channel encoded playback data signal. To generate a pulse for each transition of the playback data signal so that only leading, positive edges of the pulses identify the data signal transitions, the amplifier-limiter circuit 1019 provides two opposite phased waveforms of the data signal. First, a rectangular pulse sequence of non-inverted polarity is provided at the output terminal 1052 of the last amplifier 1053 of the series of amplitude-limiting amplifiers and second, an identical pulse sequence of inverted polarity is provided at the output terminal 1054 of the same amplifier 1053. Both these pulse sequences are applied respectively to two identical one-shot multivibrators 1055 and 1056, such as type MC10131L of the pulse former circuit 1020. Each multivibrator forms a positive pulse, respectively, for each positive going transition of the playback data signal received at its clock input. Consequently, the one-shot multivibrator 1055 receiving the non-inverted form of the playback data signal provides a positive pulse at each positive going transition in the data signal. On the other hand, the other one-shot multivibrator 1056 receiving the inverted form of the playback data signal provides a positive pulse at the location of each negative going transition in the data signal. Since the leading edges of the positive pulses generated by the multivibrators 1055 and 1056 are defined by rapidly switching the multivibrators from its stable state to its quasi-stable state (there being no significant time constant determining components involved), each leading edge will be identical to all others and occur at a precise time following the occurrence of the positive clocking transition of the playback data signal. Because the transmission channel over which the pulses are sent will act on identical pulse edges the same, the locations of the transition-related positive pulse edges, hence, data signal transitions themselves, are not lost as a result of any distortion that may be introduced to the pulses by the action of the transition channel. For transmission of the transition related pulses, the output pulses of both one shot multi-vibrators 1055 and 1056 are applied to separate inputs of a postive OR-gate 1057 which forms an output pulse for each input pulse. The output pulses of the OR-gate 1057 are applied to the disc drive data interface 151 for onward transmission. WHAT WE CLAIM IS:

1. Apparatus in which a magnetic playback head provides a signal which is the time differential of recorded magnetic flux and in which this signal is transmitted through a channel of non-constant amplitude response to varying frequency and non-linear phase response to varying frequency, the apparatus including an equalizer comprising a parallel combination of a low-pass integrating circuit and of a high-pass differentiating circuit, both said circuits having inputs coupled to an output of said magnetic reproduce head, each said circuit having respective outputs providing output signals having respective phase shifts of substantially 90 , equal in magnitude and opposite in sense with respect to said signal provided by said reproduce head; and means providing a difference signal of said output signals, said difference signal being amplitude and phase equalized with respect to said provided by said reproduce head, the resulting equalized channel having a constant amplitude response and a linear phase response for all signal frequencies transmitted therethrough.

2. Apparatus according to claim 1, further comprising a gain adjustment circuit coupled to said differentiating circuit to provide a linear variation of a high frequency amplitude boost effected by said differentiating circuit with frequency while maintaining an unchanged low frequency amplitude boost effected by said integrating circuit.

3. Apparatus according to claim 1, wherein the low pass integrating circuit comprises a first inverting operational amplifier, a negative feedback capacitor, and a series input resistor, the high pass differentiating circuit comprises a second inverting operational amplifier, a negative feedback resistor, and a series input capacitor, said first and second amplifier having their respective inverting inputs coupled to receive said reproduce signal, and the means providing the difference signal comprises a differential amplifier having its inputs coupled to respective outputs of said first and second operational amplifier.

4. Apparatus according to claim 3 wherein said negative feedback resistor of said second inverting operational amplifier is a variable resistor for adjusting the gain provided

by differentiating circuit.

5. Apparatus according to claim 3 futher comprising a shunt resistor connected to said negative feedback capacitor and a series resistor connected to said series input capacitor to limit respective integrating and differentiating operations by said respective integrating and differentiating circuit outside a frequency range of interest.

6. Apparatus according to claim 1, further comprising a first and second non-inverting amplifier and wherein the low pass integrating circuit comprises a passive integrating network having a series resistor and a parallel capacitor, said network coupled to an input of said first non-inverting amplifier, the high pass differentiating circuit comprises a passive differentiating network having a series capacitor and a parallel resistor, said network coupled to an input of said second non-inverting amplifier, and said means providing a difference signal comprises a differential amplifier having its inputs coupled to respective outputs of said first and second non-inverting amplifier.

7. Apparatus according to claim 6 further comprising a variable gain control circuit for adjusting the gain of said second non-inverting amplifier to provide a linear variation of a high frequency amplitude boost effected by said differentiating circuit with frequency.

8. A frequency response equalization circuit in association with a magnetic transducer employed for reproducing a signal recorded on a magnetic medium, the reproduced signal being a time differential of the recorded magnetic flux, and exhibiting amplitude and phase distortions caused by a non-constant amplitude response and nonlinear phase response to the transducer, comprising means coupled to said transducer for providing an output signal which has a high frequency amplitude boost and a substantial 90" phase lead relative to the reproduced signal, means coupled to said transducer for producing an output signal which has a low frequency amplitude boost and a substantial 90" phase lag relative to the reproduced signal, the said low frequency amplitude boost compensating for a rising portion of a non-constant amplitude response of said transducer and the said high frequency amplitude boost compensating for a falling portion of a non-constant amplitude response of said transducer, a gain control for providing a linear variation with frequency of said high frequency amplitude boost while maintaining said low frequency amplitude boost unchanged, and means for providing a signal according to the difference between the said output signals.