GB1593694A - Method for making a semiconductor device - Google Patents

Method for making a semiconductor device Download PDF

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Publication number
GB1593694A
GB1593694A GB1075/78A GB107578A GB1593694A GB 1593694 A GB1593694 A GB 1593694A GB 1075/78 A GB1075/78 A GB 1075/78A GB 107578 A GB107578 A GB 107578A GB 1593694 A GB1593694 A GB 1593694A
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layer
polyoxide
polysilicon
substrate
oxide
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CTU of Delaware Inc
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Mostek Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28229—Making the insulator by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32105—Oxidation of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Formation Of Insulating Films (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Local Oxidation Of Silicon (AREA)

Description

(54) METHOD FOR MAKING A SEMICONDUCTOR DEVICE (71) We, MOSTEK CORPORATION, a corporation organized and existing under the laws of the State of Delaware, with its principal place of business at 1215 West Crosby Road, Carrollton, Dallas County, Texas, United States of America, do hereby declare the invention for which we pray that a patent may be granted to us and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates generally to making semiconductor devices, and more particularly to a method of forming an insulating layer in a semiconductor device. The method is of value in making metal-oxide-semiconductor fieldeffect transistors and in related integrated circuit manufacturing techniques, particularly isoplanar MOSFET integrated circuit manufacture.
Prior art integrated circuit manufacturing techniques have employed silicon dioxide deposition in a number of areas, and particularly for the purpose of masking silicon nitride. Formation of an oxide mask is typically achieved by selective etching using a photoresist mask of the same pattern desired for the oxide mask. Deposited silicon dioxide tends to contain hard particles, which makes it difficult to duplicate the good mask definition of the photoresist in the oxide. When a large number of silicon wafers undergo simultaneous silicon dioxide deposition, variations in thickness occur from wafer to wafer. Such variations necessitate an etch duration long enough to cut through the thickest oxide anticipated, which causes over etching of thinner oxide layers and consequently undesirable undercutting of the photoresist. Compounding such problems is the relatively fast etch rate of deposited silicon dioxide (compared to grown oxide, for example) which makes controlling the etch more difficult.
According to the first feature of the present invention, there is provided a method of making an oxidation mask comprising the steps of: (a) forming a layer of an oxidation resistant material on a semiconductor substrate, (b) depositing a polysilicon layer on the oxidation resistant layer, (c) exposing the polysilicon layer to an oxidising ambient to oxidise the entire layer to form a polyoxide layer as hereinafter defined, (d) exposing selected portions of the polyoxide to an acid etch to form a polyoxide mask, and (e) using the polyoxide mask to remove portions of the oxidation resistant layer thereby to form an oxidation mask for a layer of the semiconductor substrate beneath the oxidation resistant material.
According to a second feature of the invention there is provided a method of stabilising a semiconductor device comprising the steps of: (a) depositing polysilicon on a semiconductor device, (b) doping the polysilicon with a stabilising material, and (c) converting the polysilicon to polyoxide as hereinafter defined.
The term stabilising used herein means immobilising otherwise mobile ions in the environment which, if not immobilised, could contaminate that environment or cause a threshold voltage shift.
In carrying out a method according to the present invention, polycrystalline silicon (hereinafter referred to "polysilicon") is deposited on a semiconductor device and then converted to silicon (hereinafter referred to as "polyoxide"). The polysilicon is preferably vacuum deposited in a hot wall furnace. The oxidation of the polysilicon preferably takes place in a moist oxidizing ambient at a temperature sufficient to convert the polysilicon layer to a polyoxide layer having the general characteristics of a thermal oxide grown directly on silicon. The polyoxide may, however, overlie surfaces other than silicon, as in the first aspect of the invention noted above, in which an oxidiation mask is formed by etching a pattern of an oxidation-resistant material through a polyoxide mask. One particular application of this important aspect of the invention involves the use of an oxidation mask of silicon nitride in the formation of an isoplanar field oxide which defines active areas in a semiconductor substrate. Polyoxide provides advantages over deposited silicon dioxide in that polyoxide has a slower etch rate and a more uniform thickness and composition compared to deposited silicon dioxide, thereby permitting better mask definition and resulting finer control in locating the field oxide and active areas therebetween.
An additional advantage of the present invention is the relatively low temperature at which a polyoxide layer may be created, which permits the formation of passivation and stabilization layers at temperatures which do not affect diffusion profiles in the semiconductor device.
Still another advantage of using polyoxide as opposed to deposited silicon dioxide is that a large number of wafers may be positioned vertically on edge and closely spaced in a boat for processing in a hot wall furnace as opposed to the lower volume cold wall arrangement typically used to deposit silicon dioxide. Additionally, the wafers conveniently remain in situ in the boat during subsequent oxidation of the wafers.
The invention further provides semiconductor devices having one or more insulating or stabilization layers comprised of polyoxide. In particular the invention provides a semiconductor device, comprising a substrate, an isoplanar field oxide defining active regions in the substrate, a stabilization layer of polyoxide disposed over the field oxide and the active regions, and contacts disposed in electrical cooperation with selected active regions through windows in the stabilization layer.
The invention is illustrated by way of Example, with reference to the manufacture of a semiconductor device as shown in the accompanying drawings, wherein: Figures 1-15 are schematic sectional views of various stages in a process for making a device of the present invention.
Referring to Figure 1, there is shown a schematic slice of a device of the present invention, indicated generally by the reference numeral 10, at an early stage in a manufacturing process.
A silicon wafer of P-type conductivity, having a resistivity preferably of about 5 to 30 ohmcm., is employed as a substrate 12. Grown on top surface 14 of the substrate 12 is a silicon dioxide layer 16, having a preferred thickness of about 600 Angstroms. A silicon nitride layer 18, having a thickness of about 650 Angstroms, is deposited on the silicon dioxide layer 16 using known cold wall or hot wall reactor techniques. A top layer 20 of polysilicon is deposited on silicon nitride layer 18 preferably in a hot wall furnace using known vacuum deposition techniques.
The device 10 is then exposed to an oxidizing ambient in steam preferably at about 950"C for a sufficient period of time to completely oxidize the polysilicon layer 20 of Figure 1, thereby producing a polyoxide layer 20' as shown in Figure 2. The layer 20' is preferably about 2500 Angstroms in thickness, which is about twice the thickness of the original polysilicon layer 20 due to growth during oxidation.
Referring to Figure 3, a photoresist pattern 22 is deposited on polyoxide layer 20' using standard photomasking techniques; after which the unmasked portions of layer 20 are etched away. Following the etching step, an ion implant step is performed in a known manner as indicated by the arrows, preferably using boron which produces Pt regions 24 in the portions of the substrate 12 not covered by the polyoxide 20'. Isolated between regions 24 is the area where active elements will be formed in the device 10.
Figure 3 illustrates an important feature of the presently described method wherein the resolution in defining the photoresist mask 22 is substantially reproduced in the polyoxide layer 20' by virtue of the controllability with which polyoxide can be etched. Undercutting of photoresist by lateral etching of the underlying oxide is a significant prior-art problem, which is greatly alleviated by the use of polyoxide as the material of layer 20'. The tendency to undercut the mask 22 by lateral etching of layer 20' is comparatively reduced since polyoxide can be etched with greater control than the deposited oxide used in the prior art. Such greater etch control is possible by virtue of the qualitative advantages of polyoxide over deposited oxide. Polyoxide has a slower etch rate, a more uniform thickness from wafer to wafer, and a relatively clean, particle-free composition.
Next, the photoresist layer 22 is removed and the portions of the nitride layer 18 not covered by the polyoxide layer 20' are etched away to produce the structure of Figure 4, using known techniques. Since the polyoxide layer 20' acts as a mask during the etching of nitride layer 18, a high degree of resolution is carried through in the structure of Figure 4.
Now referring to Figure 5, an isoplanar field oxidation is performed in steam for about 6 to 8 hours at approximately 10000C, which results in a relatively thick "field" oxide layer 26, preferably about 13,000 Angstroms in thickness, being disposed around the stack of layers 16, 18 and 20'. The field oxide 26 penetrates into the substrate 12 to a depth of about 5000 Angstroms, driving the boron implant 24 to a greater depth therebelow. The field oxide 26 defines a region in the substrate 12 for forming an active element such as a MOSFET. Since the field oxide 26 is defined by the layer 18 comprising oxidation-resistant silicon nitride, it will be apparent that the controlled etching of polyoxide layer 20' is a determining factor in the achievement of precise substrate space allocation, thereby affecting not only yields but also element density in the substrate.
Next, the polyoxide layer 20' is removed by means of etching with hydrofluoric acid in a known manner, which also reduces the thickness of the field oxide 26. Then, the nitride layer 18 and oxide layer 16 are removed using conventional techniques, which produces the structure shown in Figure 6. Incident to the removal of oxide layer 16, the thickness of the field oxide 26 is again reduced somewhat. As an alternative to the above sequence of steps, it may be advantageous to remove the polyoxide layer 20' prior to growing the field oxide 26, thereby limiting the etching of the field oxide 26.
Following a surface cleaning step, a "channel" oxide layer 28 is grown to a thickness of about 900 Angstroms as shown in Figure 7.
This is followed by an ion implant step using known techniques. Either an enhancement mode or a depletion mode FET may be produced depending on the ion conductivity type and dosage level as described in United States Patent No. 3,898,105, the terms of which are incorporated by reference herein.
Now referring to Figure 8, a polysilicon layer 30 is deposited on the channel oxide 28 to a thickness of about 5000 Angstroms using vacuum deposition in a hot wall furnace, similarly as described above in conjunction with layer 20 in Figure 1. The polysilicon layer 30 will provide a means for forming a gate of a MOSFET by subsequent processing to be discussed below.
A partial oxidation of polysilicon layer 30 is then performed to produce a polyoxide layer 32 of about 700 Angstroms in thickness above the polysilicon layer 30 as shown in Figure 9.
Next, a gate area is defined by a photoresist pattern 34, and the oxide layer 32 not covered by the photoresist 34 is etched away to produce the structure shown in Figure 10.
Now referring to Figure 11, the photoresist 34 is removed, leaving the polyoxide layer 32 as a mask for etching the polysilicon 30 to produce the structure shown. Since both layers 32 and 30 may be controllably etched, good channel definition is achieved as will be apparent to those skilled in the art.
Next, an etch is performed which removes the polyoxide layer 32 and the portions of the oxide layer 28 not covered by the polysilicon 30, leaving a channel oxide strip 28 covered by a polysilicon strip 30. Thereafter, an N-type dopant, preferably phosphorus, is diffused using known techniques to produce N+ source and drain regions 36 and 38 in the substrate 12, which define channel region 40 in accordance with the structure of Figure 12. The N+ regions 36 and 38 preferably have a resistivity of about 20 to 25 ohms/square. The phosphorus also diffuses into the polysilicon 30 (as indicated by the stippling), which causes layer 30 to be heavily doped N-type and thus highly conductive.
A thin, thermal oxide layer 42 is then grown as illustrated in Figure 13. The oxide layer 42 is preferably grown in steam at about 950"C to a thickness of about 700 Angstroms.
Now referring to Figure 14, a layer 44 of polysilicon, preferably about 2500 Angstroms in thickness, is deposited using the same techniques described above in conjunction with the formation of layers 20 and 30. Next, a doping step is performed to introduce a stabilizing material on all sides for the purpose of preventing impurities such as sodium from migrating into the underlying oxide layers, particularly the gate oxide 28. The doping step is preferably phosphorus diffusion, which readily enters polysilicon layer 44 without traversing the underlying oxide. Stabilization by phosphorus diffusion into silicon dioxide has been practiced in the prior art. Here it will be seen that a particular advantage of the present invention which greatly facilitates stabilization is that phosphorus diffuses at a much faster rate into polysilicon than into silicon dioxide.
The polysilicon layer 44 is then oxidized in steam at a temperature not exceeding 950"C, thereby producing a polyoxide stabilization layer 44 , which expands to about 5000 Angstroms in thickness. A further advantage of the present invention is the relative speed with which N-doped polysilicon oxidizes. This relatively fast oxidation rate provides a favourable reduction in furnace time at this point in the process. Thereafter, contact windows are opened and metal source, drain and gate contacts 46, 48 and 50 are formed, preferably using aluminium deposition in a known manner to produce the structure shown in Figure 15, which is referred to as a "silicon gate " structure. Due to the high conductivity of polysilicon layer 30, a gate signal applied to the contact 50 is carried by polysilicon layer 30, thereby modulating the channel 40 through oxide layer 28 in a manner known to those familar with field-effect transistors. Polysilicon layer 30 may be located at a predetermined height above the channel 40 depending on the thickness of oxide layer 28.
A particular advantage of the deposition and oxidation steps of Figures 14 and 15, is that the oxidation may be performed at a temperature low enough to prevent adverse alteration of the characteristics of the underlying regions of the device 10. For example, undesirable lateral diffusion of regions 36 and 38 is substantially averted by using the stabilization method of the present invention. While temperatures greatly in excess of 950"C will cause undesirable lateral diffusion of impurities in regions 36 and 38, 950"C is a sufficiently high temperature to convert polysilicon to a polyoxide having good thermal oxide characteristics.
Finally, a glassivation step is performed to environmentally passivate device 10 in a known manner. Preferably, a phosphorus stabilized glass layer is formed by depositing a phosphorus doped oxide at a low temperature.
Although a preferred embodiment of the invention has been described in detail, it is to be understood that various changes, substitutions and alterations can be made therein without departing from the scope of the invention as defined by the appended claims. For example, while silicon has been designated as a preferred substrate material, other known elemental and compound semiconductor materials may be employed advantageously in certain applications; while the substrate 12 has been explicitly shown as P-type, a device having an N-type substrate may be produced by similar process steps as will be appreciated by those skilled in the art; while phosphorus and boron have been designated as preferred dopants, other known N-type and P-type dopants may be substituted therefor. These and other known variations of the above-described method of practicing the invention are within the scope of the claimed subject matter.
WHAT WE CLAIM IS: 1. A method for accurately forming an oxidation mask comprising the steps of: (a) forming a layer of an oxidation resistant material on a semiconductor substrate, (b) depositing a polysilicon layer on the oxidation resistant layer, (c) exposing the polysilicon layer to an oxidising ambient to oxidise the entire layer to form a polyoxide layer as hereinbefore defined, (d) exposing selected portions of the polyoxide to an acid etch to form a polyoxide mask, and (e) using the polyoxide mask to remove portions of the oxidation resistant layer thereby to form an oxidation mask for a layer of the semiconductor substrate beneath the oxidation resistant material.
2. A method according to claim 1 used accurately to define an active area of a semiconductor substrate, wherein the oxidation resistant material comprises silicon nitride, and subsequent to step (e) the substrate is exposed to an oxidising ambient to grow an isoplanar thick oxide layer around the silicon nitride oxidation mask.
3. A method according to claim 1 or claim 2 wherein a thermal oxide layer is formed on the semiconductor substrate prior to step (a) and the oxidation resistant layer is deposited on the thermal oxide layer.
4. A method of stabilising a semiconductor device comprising the steps of: (a) depositing polysilicon on a semiconductor device, (b) doping the polysilicon with a stabilising material, and (c) converting the polysilicon to polyoxide as hereinbefore defined.
5. A method according to claim 4 wherein, in step (b) the stabilising material is phosphorus, and in step (c) the conversion of polysilicon to polyoxide is achieved by oxidising the polysilicon in steam in a hot wall furnace at a temperature sufficient to convert the polysilicon to polyoxide having the general characteristics of a thermal oxide grown directly on silicon.
6. A method according to claim 4 or 5 wherein the temperature in the hot wall furnace is about 950"C.
7. A method of making an isoplanar MOS device comprising the steps of: (a) growing a thick isoplanar field oxide around an active area in a semiconductor substrate, (b) forming an MOS device in the active area, (c) growing a thin thermal oxide in the active area (d) depositing a polysilicon layer over both the thick thermal oxide and the thin thermal oxide (e) oxidising the entire polysilicon layer to produce a polyoxide layer as hereinbefore defined, and (f) forming contacts through windows in the polyoxide layer.
8. A method according to claim 7 wherein in step (e) the polysilicon layer is oxidised in steam at a temperature low enough to prevent adverse alteration of characteristics in the substrate, yet at a temperature high enough to produce a polyoxide having the general characteristics of a thermal oxide grown directly on silicon.
9. A method according to claim 7 or 8 further comprising the step of diffusing a stabilising material into the polysilicon layer prior to the oxidation step (e).
10. A method according to any one of claims 7 to 9 further comprising, preceding step (a), the step of: implanting ions in selected portions of the substrate using an implantation mask, and then using the same mask pattern to grow the isoplanar field oxide in step (a) thereby driving the ions to a greater depth in the substrate.
11. A method of making an isoplanar MOS device substantially as hereinbefore described with reference to the accompanying drawings.
12. A semiconductor device comprising: a substrate, an isoplanar field oxide defining active regions in the substate, a stabilisation layer of polyoxide, as hereinbefore defined, disposed over the field oxide and the active regions, and contacts disposed in electrical cooperation with selected active regions through windows in the stabilisation layer.
13. A device according to claim 1 2 wherein the stabilisation layer of polyoxide comprises an oxidised vacuum deposited layer of polycrystalline silicon containing a stabilising impurity.
14. A device according to claim 12 or 13 further comprising a silicon gate disposed with an oxide layer which is between the stabilisation layer and an active region, the silicon gate comprising heavily doped polysilicon.
15. A device according to claim 14 including at least one MOSFET, the MOSFET having a channel region of P-type conductivity disposed
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (15)

**WARNING** start of CLMS field may overlap end of DESC **. as defined by the appended claims. For example, while silicon has been designated as a preferred substrate material, other known elemental and compound semiconductor materials may be employed advantageously in certain applications; while the substrate 12 has been explicitly shown as P-type, a device having an N-type substrate may be produced by similar process steps as will be appreciated by those skilled in the art; while phosphorus and boron have been designated as preferred dopants, other known N-type and P-type dopants may be substituted therefor. These and other known variations of the above-described method of practicing the invention are within the scope of the claimed subject matter. WHAT WE CLAIM IS:
1. A method for accurately forming an oxidation mask comprising the steps of: (a) forming a layer of an oxidation resistant material on a semiconductor substrate, (b) depositing a polysilicon layer on the oxidation resistant layer, (c) exposing the polysilicon layer to an oxidising ambient to oxidise the entire layer to form a polyoxide layer as hereinbefore defined, (d) exposing selected portions of the polyoxide to an acid etch to form a polyoxide mask, and (e) using the polyoxide mask to remove portions of the oxidation resistant layer thereby to form an oxidation mask for a layer of the semiconductor substrate beneath the oxidation resistant material.
2. A method according to claim 1 used accurately to define an active area of a semiconductor substrate, wherein the oxidation resistant material comprises silicon nitride, and subsequent to step (e) the substrate is exposed to an oxidising ambient to grow an isoplanar thick oxide layer around the silicon nitride oxidation mask.
3. A method according to claim 1 or claim 2 wherein a thermal oxide layer is formed on the semiconductor substrate prior to step (a) and the oxidation resistant layer is deposited on the thermal oxide layer.
4. A method of stabilising a semiconductor device comprising the steps of: (a) depositing polysilicon on a semiconductor device, (b) doping the polysilicon with a stabilising material, and (c) converting the polysilicon to polyoxide as hereinbefore defined.
5. A method according to claim 4 wherein, in step (b) the stabilising material is phosphorus, and in step (c) the conversion of polysilicon to polyoxide is achieved by oxidising the polysilicon in steam in a hot wall furnace at a temperature sufficient to convert the polysilicon to polyoxide having the general characteristics of a thermal oxide grown directly on silicon.
6. A method according to claim 4 or 5 wherein the temperature in the hot wall furnace is about 950"C.
7. A method of making an isoplanar MOS device comprising the steps of: (a) growing a thick isoplanar field oxide around an active area in a semiconductor substrate, (b) forming an MOS device in the active area, (c) growing a thin thermal oxide in the active area (d) depositing a polysilicon layer over both the thick thermal oxide and the thin thermal oxide (e) oxidising the entire polysilicon layer to produce a polyoxide layer as hereinbefore defined, and (f) forming contacts through windows in the polyoxide layer.
8. A method according to claim 7 wherein in step (e) the polysilicon layer is oxidised in steam at a temperature low enough to prevent adverse alteration of characteristics in the substrate, yet at a temperature high enough to produce a polyoxide having the general characteristics of a thermal oxide grown directly on silicon.
9. A method according to claim 7 or 8 further comprising the step of diffusing a stabilising material into the polysilicon layer prior to the oxidation step (e).
10. A method according to any one of claims 7 to 9 further comprising, preceding step (a), the step of: implanting ions in selected portions of the substrate using an implantation mask, and then using the same mask pattern to grow the isoplanar field oxide in step (a) thereby driving the ions to a greater depth in the substrate.
11. A method of making an isoplanar MOS device substantially as hereinbefore described with reference to the accompanying drawings.
12. A semiconductor device comprising: a substrate, an isoplanar field oxide defining active regions in the substate, a stabilisation layer of polyoxide, as hereinbefore defined, disposed over the field oxide and the active regions, and contacts disposed in electrical cooperation with selected active regions through windows in the stabilisation layer.
13. A device according to claim 1 2 wherein the stabilisation layer of polyoxide comprises an oxidised vacuum deposited layer of polycrystalline silicon containing a stabilising impurity.
14. A device according to claim 12 or 13 further comprising a silicon gate disposed with an oxide layer which is between the stabilisation layer and an active region, the silicon gate comprising heavily doped polysilicon.
15. A device according to claim 14 including at least one MOSFET, the MOSFET having a channel region of P-type conductivity disposed
in the substrate below the silicon gate, and heavily doped source and drain regions of Ntype conductivity, the source region, drain region and silicon gate having been simultanously doped by a phosphorus diffusion.
GB1075/78A 1977-01-17 1978-01-11 Method for making a semiconductor device Expired GB1593694A (en)

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US4268951A (en) * 1978-11-13 1981-05-26 Rockwell International Corporation Submicron semiconductor devices
JPS5941870A (en) * 1982-08-25 1984-03-08 Toshiba Corp Manufacture of semiconductor device
JPS5955071A (en) * 1982-09-24 1984-03-29 Hitachi Micro Comput Eng Ltd Non-volatile semiconductor device
GB2131407B (en) * 1982-11-12 1987-02-04 Rca Corp Method of formation of silicon dioxide layer
JPS59184547A (en) * 1983-04-04 1984-10-19 Agency Of Ind Science & Technol Semiconductor device and manufacture thereof
JPS6066866A (en) * 1983-09-24 1985-04-17 Sharp Corp Manufacture of silicon carbide mos structure

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US3966501A (en) * 1973-03-23 1976-06-29 Mitsubishi Denki Kabushiki Kaisha Process of producing semiconductor devices
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US3911168A (en) * 1973-06-01 1975-10-07 Fairchild Camera Instr Co Method for forming a continuous layer of silicon dioxide over a substrate
US3874920A (en) * 1973-06-28 1975-04-01 Ibm Boron silicide method for making thermally oxidized boron doped poly-crystalline silicon having minimum resistivity
US3899373A (en) * 1974-05-20 1975-08-12 Ibm Method for forming a field effect device

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DE2801680A1 (en) 1978-07-20
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IT1089298B (en) 1985-06-18
JPS5390776A (en) 1978-08-09
FR2377703A1 (en) 1978-08-11

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