GB1585891A

GB1585891A - Tdm switching networks

Info

Publication number: GB1585891A
Application number: GB2448/77A
Authority: GB
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1976-01-23
Filing date: 1977-01-21
Publication date: 1981-03-11
Also published as: BE850636A; ATA961876A; CH614330A5; DE2602561A1; SE7700671L; IT1076528B; AT355632B; FR2339310A1; SE413970B; FR2339310B1; DE2602561B2; DE2602561C3

Abstract

The time division multiplex switching network has switching network units (KE) which in each case effect a spatial and a temporal allocation of time channels formed on connected time division multiplex lines. For a switching network of this type, a structure is indicated in which, using a single type of switching network unit and starting with the lowest configuration levels, expansions of any size can be undertaken in simple fashion by adding further switching network units without any preparatory work having to be carried out for this purpose during a basic configuration. To achieve this, the time division multiplex lines in the form of groups of lines (1Z to nZ; 1S to mS) form a matrix-type arrangement at whose intersection points at least one switching network unit (KE) is in each case connected to the individual lines of two line groups (Z, S) via which connections between time division multiplex lines of the two line groups (S, Z) as well as connections between time division multiplex lines within the two groups can be set up, and the switching network units (KE) have a lower traffic handling capacity than that which corresponds to full accessibility. <IMAGE>

Description

(54) IMPROVEMENTS IN OR RELATING TO T.D.M. SWITCHING NETWORKS (71) We, SIEMENS AKTIENGESELLSCHAFT, a German Company, of Berlin and Munich, Federal Republic of Germany, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement This invention relates to t.d.m. switching networks.

The use of switching network units, each of which effects a spatial and time coordination of time channels formed on t.d.m.

lines connected thereto, forming a small t.d.m. exchange is of particular interest when the units are constructed as large scale integration (LSI) units. It is then possible to construct switching networks of virtually arbitrary size with only a few types of such switching network units, without the need initially to make particular provisions for this.

Our copending application No. 2450/77 (Serial No. 1,585,892) discloses and claims such a switching network in which a matrix of t.d.m. lines is provided, switching network units being provided at respective intersections each between two intersecting lines.

German Specification No. 2,444,854 relates to the construction of t.d.m. switching networks from a total of three such types of switching network units provided with eight, sixteen, and twenty-four terminals for t.d.m.

lines, the use of which units is dependent upon the overall size of the switching network, in each case two types being components of first and second switching network stages of at least one switching network level.

As long as unconnected t.d.m. terminals exist in a t.d.m. switching network of this type in the switching network units of the second stage of a switching network level, it is possible to extend the switching network in a simple fashion by the addition of further switching network units in the first stage and by a corresponding connection of the latter to the free terminals of the second stage by means of intermediate lines. If, however, all the t.d.m. terminals of the second stage of a switching network level are connected it is no longer possible to achieve a substantial extension of the switching network without re-arranging existing intermediate line connections.

In a t.d.m. switching network constructed as described above the switching network units of the first switching network stage are provided so that no possibility exists of handling the traffic of the t.d.m. lines connected to a switching network unit of this stage also via another switching network unit.

Therefore the switching network units of the first stage must be designed for relatively small numbers of terminals which, with the two-stage construction, means that it is not possible to dispense with switching network units having comparatively larger numbers of terminals in the second switching network stage.

As development costs are of particular importance in integrated circuit technology, there is interest in constructing switching networks from only a single type of switching network unit. This invention seeks to provide a t.d.m. switching network which comprises only a single type of switching network unit and which commencing from its smallest form can be extended in a simple manner by the addition of further such switching network units.

According to this invention there is provided a t.d.m. switching network comprising a plurality of groups of t.d.m. lines, which groups intersect with one another to form a matrix, and at each intersection a switching network unit connected to the individual lines of the two groups defining the intersection via which switching network unit connections can be established each between any two t.d.m. lines of the two groups, each switching network unit providing a spatial and time coordination of time channels formed on the connected t.d.m. lines and having a smaller traffic handling capacity than that of the t.d.m. lines to which it is connected.

A plurality of switching network units may be connected in parallel with one another at one or more of the intersections; this is expedient in relatively small switching net works to match the traffic handling capacity of the network to particular traffic loads.

The switching network units are expediently all identical to one another; thus a single type of switching network unit can be used in any arbitrary switching network which can consequently be extended without the need to carry out re-arrangements of intermediate lines.

The groups of t.d.m. lines may form column line groups and row line groups of a rectangular matrix, or each group of t.d.m.

lines may intersect each other group of t.d.m.

lines to form a triangular matrix. A larger t.d.m. switching network may be formed by a plurality of similar such rectangular matrix switching networks and a plurality of similar such triangular matrix switching networks, the column or the row line groups of each rectangular matrix being each connected to a respective group of t.d.m. lines of a respective one of the triangular matrices via a respective group of intermediate lines, or alternatively from a plurality of similar such rectangular matrix switching networks, the lines of the column or the row line groups of each matrix being connected each to a corresponding line of a respective one of the other matrices via a respective intermediate line.

It will be appreciated that in such switching networks the traffic of each group of t.d.m.

lines is not restricted to being handled by only a single switching network unit, so that relatively favourable operating conditions are achieved also taking into consideration the losses occurring in the event of the breakdown of a switching network unit. The undercapacity of the individual switching network units prevents an unnecessary redundancy in particular in the construction of large switching networks.

Expediently when the switching network is for use in a PCM exchange system each switching network unit comprises a time stage comprising a plurality of parallelconnected shift registers each having as many stages as there are bits in each PCM word, an input end spatial stage comprising a multiplexer having a plurality of switches each of which serves to couple a respective incoming pair of t.d.m. line wires to the shift register inputs, and an output end spatial stage comprising a demultiplexer having a like plurality of switches each of which serves to couple the shift register outputs to a respective outgoing pair of t.d.m. line wires, the switches of the multiplexer and the demultiplexer which serve for the coupling of associated incoming and outgoing pairs of t.d.m.

line wires being arranged to be operated in synchronism with one another.

Each switching network unit preferably further comprises a holding set comprising as many parallel connected shift registers as there are time channels on each t.d.m. line each of which can simultaneously store a first address identifying any switch of the multiplexer and demultiplexer and a second address identifying any one of the shift registers of the time stage, the outputs of the holding set shift registers being connected via a first switch, which is arranged to be closed for the duration of read out from any of the shift registers of each first address, to a first series-parallel converter whose outputs are connected to inputs of a first decoder which supplies control signals for the switches of the multiplexer and demultiplexer, via a second switch, which is arranged to be closed for the duration of read out from any of the shift registers of each second address, to a second series-parallel converter whose outputs are connected to inputs of a second decoder which supplies release signals for shift pulse trains for the shift registers of the time stage, and via a third switch, which is arranged to be opened only during entry of new addresses into the holding set shift registers, to the inputs of these shift registers, the holding set further comprising a further shift register having as many stages as there are time channels on each t.d.m. line and arranged to supply a release signal for a shift pulse train for each of the holding set shift registers in turn each for the duration of a respective time channel of the t.d.m. pulse frame.

The invention will be further understood from the following description by way of example of embodiments thereof with reference to the accompanying drawings, in which: Fig. 1 symbolically illustrates a switching network unit; Figs. 2 to 5 schematically illustrate alternative forms of PCM t.d.m. switching networks, in which the t.d.m. lines are four-wire lines, in accordance with embodiments of the invention; and Fig. 6 schematically illustrates a switching network unit which can be used in the switching networks of Figs. 2 to 5.

Fig. 1 illustrates symbolically, a switching network unit with which a spatial and time slot switching can be carried out between t.d.m. lines to which it is connected. Double arrows at individual terminals of the unit indicate that these are the terminals of incoming and outgoing pairs of wires of the PCM t.d.m. lines, and the fact that the terminals lead in different directions indicates that two groups of terminals are provided for different groups of t.d.m. lines. The distribution of terminals between the groups is arbitrary. The switching network unit is designed in such manner that via the unit it is possible to establish a connection between two t.d.m.

lines of the same group or of different groups.

Fig. 2 uses the symbol of Fig. 1 to illustrate a switching network which is in the form of a matrix of PCM line groups 1Z to nZ each of which line groups for example comprises four PCM t.d.m. lines and PCM t.d.m. line groups 1S to mS each of which line groups for example comprises five PCM t.d.m. lines, these line groups constitute respectively row groups and column groups of the matrix. At intersection points of the PCM t.d.m. line groups switching network units KE are connected by one group of its terminals to the t.d.m. lines of a row group and by its other group of terminals to the t.d.m. lines of a column group. At each intersection point one or more switching network units may be connected in this manner.

The individual switching network units KE are identical to one another and each unit has a smaller traffic handling capacity than that of the t.d.m. lines to which it is connected.

Thus if there is a number Zk of time channels on each individual t.d.m. line, then in this embodiment less than (4+5) Zk/2 connections (the handling of this number of connections is referred to as "full availability") can be handled via each switching network unit. In a large switching network full availability via a switching network unit would represent an unnecessary redundancy, since the probability is small that all the possible connections from the t.d.m. lines of a column group are to be established via the same switching network unit, i.e. exclusively to t.d.m. lines of the same column group and/or to t.d.m. lines of a single row group. In practice a switching network unit with fifteen PCM four wire line terminals via which sixteen connections can be conducted simultaneously can be used as described below.

In a small switching network, in which the incidence of traffic at the individual intersection points between line groups is greater, it is possible to meet particular requirements by connecting one or more than one switching network unit in parallel to the already existing switching network unit, as already indicated above.

It is possible to extend the switching network in a simple manner by connecting in the same manner further t.d.m. line column groups and/or row groups to the existing groups via further switching network units.

As can be seen from Fig. 2, the breakdown of a switching network unit does not necessarily lead to the loss of all the connections which can be conducted via the t.d.m. lines of the line groups connected to this switching network unit.

If, as assumed, the t.d.m. lines are fourwire lines, with the arrangement illustrated in Fig. 2 it is not readily possible to establish connections between t.d.m. lines which belong to different line groups but line groups of the same type, such as between different groups of row lines. Therefore, as is further explained below, this arrangement is particularly suitable to form part of a large switching network in which case line groups of one type comprise t.d.m. lines which do not lead to other exchanges but instead establish connections to further matrix arrangements within the switching network.If instead the t.d.m. lines are two wire lines the above limitation does not exist, it being possible to establish a connection for example between a t.d.m. line of one row group and a t.d.m. line of another row group via a first switching network unit, a t.d.m. line of a column group, and a further switching network unit.

Fig. 3 illustrates an alternative switching network in the form of a triangular matrix having m(m - l)/2 intersections between m groups 1 to m of t.d.m. lines, at each of which intersections at least one switching network unit KE is provided. Thus as illustrated in Fig. 3 a switching network unit is connected between every pair of t.d.m. line groups, so that it is possible to establish connections between different t.d.m. lines of a single group of lines and also between t.d.m. lines belonging to different line groups, in each case via only one switching network unit. This switching network can also be readily extended by the provision of further switching network units for additional t.d.m. line, groups.

Fig. 4 illustrates a switching network having two stages A and B, in which the A-stage consists of rectangular matrix arrangements as illustrated in Fig. 2 and the B-stage consists of triangular matrix arrangements as illustrated in Fig. 3. With z rectangular matrix arrangements Ml to Mz in the A-stage each having connected thereto, and forming for example the row line groups, m t.d.m.

line groups and each having n output-end line groups which form in this example the column line groups, n triangular matrix arrangements Dl to Dn each for m t.d.m. line groups are required. Intermediate lines ZL connect each output-end line group of the matrix arrangements of the A-stage to a respective t.d.m.

line group input of the triangular matrix arrangements of the B-stage. Connections which are established between t.d.m. lines of different line groups will with this arrangement, run via three switching network units, namely via two switching network units in the A-stage and via one switching network unit in the B-stage.

It will be appreciated that the switching network illustrated in Fig. 4 has reverse grouping; another switching network having reverse grouping is illustrated in Fig. 5 and consists of a plurality of switching network levels each of which comprises a square or rectangular matrix arrangement composed of row line groups Z and column line groups S as described above with reference to Fig. 2.

The row line groups comprise the t.d.m. lines which lead to or from the exchange to which the switching network belongs, and the column line groups are line groups via which and intermediate Zl connections can be established between different switching network levels, The arrangement is such that any t.d.m. line of a column line group S is connected to a t.d.m. line of a corresponding column line group of another switching network level, as a result of which in the case of b t.d.m. lines per column group b+l switching network levels must be provided. Thus a connection between a t.d.m. line of a row group of one switching network level and a t.d.m. line of a row line group of another switching network level runs via two switching network units, one in each switching network level.

Fig. 6 illustrates a switching network unit which is particularly suitable for use as a switching network unit KE referred to above.

The switching network unit illustrated in Fig. 6 is designed for the connection of 15 PCM t.d.m. lines and for the simultaneous handling of sixteen connections, and accordingly comprises a multiplexer M including 15 switches SE1 to SE15 each of which serves to couple a respective one of 15 incoming pairs of line wires lAn to 15An of connected t.d.m. lines to a common super-multiplex line SME, a demultiplexer D including 15 switches SA1 to SA15 each of which serves to couple a respective one of 15 outgoing pairs of line wires lAb to 15Ab of the connected t.d.m. lines to a common supermultiplex line SMA, and a time stage comprising 16 shift registers Schl to Schl6, each having eight stages corresponding to a PCM word length of eight bits, connected in parallel between the super-multiplex lines SME and SMA.Switches in the multiplexer M and the demultiplexer D having the same index, e.g. the switches SE1 and SA1, are commonly controlled to open and close in synchronism, and the shift registers Schl to Schl6 are also controlled, by a holding set comprising 32 shift registers SchH1 to SchH32, corresponding to the number of time channels of the PCM exchange system, whose inputs and outputs are interconnected to one another. Each of these shift registers serves to store a t.d.m. line address, i.e. a drive address for the switches SE and SA and an address for one of the shift registers Schl to Schl6, so that in this case with fifteen connected t.d.m. lines and sixteen simultaneous connections each of these addresses possesses four bits and each of the shift registers SchH1 to SchH32 has eight stages.

The interconnected outputs of the shift registers SchH1 to SchH32 are connected via a first switch K1 to a first series-parallel converter SP1 the outputs of which are connected to a first decoder Decl whose outputs supply control signals for the switches SUE 1 to Sue 15 of the multiplexer and SAl to SA15 of the demultiplexer, are also connected via a second switch K2 to a second series-parallel converter SP2 the outputs of which are connected to a second decoder Dec2 whose outputs supply release signals for shift pulse trains for the shift registers Schl to Schl6.

The switches K1 and K2 are in each case closed for the duration of the transmission of each drive address and each shift register address respectively. The interconnected outputs of the shift registers SchH1 to SchH32 are also connected via third switch K3 to the interconnected inputs of these shift registers.

The switch K3 is normally closed and is opened only during a new entry of addresses into the shift registers SchH1 to SchH32.

The holding set also contains a further shift register SchT having 32 stages 1 to 32 corresponding to the number of time channels of the t.d.m. system. A signal input into this shift register at the beginning of each pulse frame is advanced with the channel pulse train so that at individual outputs of this shift register there is produced for each time channel a signal which serves as a release signal for the shift pulse train of a respective one of the shift registers SchH1 to SchH32.

It will be appreciated from the above description that the switching network unit illustrated in Fig. 6 comprises an input-end spatial stage constituted by the multiplexer M, a time stage constituted by the shift registers Schl to Schl6, and an output-end spatial stage constituted by the demultiplexer D.

If for example a connection is to be established via this switching network unit between the time channel 10 on the t.d.m. line 1 and the time channel 20 on the t.d.m. line 15, then the address of the switches SE1 and SA1 is entered into the 10th holding set shift register SchH10 together with the address of a free one of the shift registers Schl to Schl6, e.g. the shift register Schl, and the address of the switches SE15 and SA15 and the same shift register address are entered into the shift register SchH20. During the time channel 10 the shift register SchT supplies a release signal for the shift pulse train to the shift register SchH10 so that from this shift register the drive address for the switches SE1 and SA1 passes via the initially closed switch K1 to the series-parallel converter SP1, is decoded by the decoder Decl and causes the switches SE1 and SAl to be closed. After the expiration of four bit time intervals, the switch K1 is opened and the switch K2 is closed, so that the address of 'the shift register Schl which is now read out from the shift register SchH10 passes to the seriesparallel converter SP2 and is decoded by the decoder Dec2 and actuates the shift register Schl.At the same time the addresses read out from the shift register SchH10 are entered back into this shift register via the closed switch K3.

In this way information supplied in the time channel 10 on the incoming pair of line wires lAn of the first t.d.m. line is supplied via the switch SE1 and the incoming supermultiplex line SME to the shift register Schl, and at the same time information already contained in this shift register Schl is fed via the outgoing super-multiplex line SMA and the switch SA1 to the outgoing pair of line wires lAb of this t.d.m. line.In the same manner, during the time channel 20 the addresses of the switches SE15 and SA15 and the shift register Schl are read out from the shift register SchH20 and are decoded, so that during this time channel the switches SE15 and SA15 are closed, and the information meanwhile stored in the shift register Schl is output to the outgoing pair of line wires 15Ab whereas information incoming during this time channel on the incoming pair of line wires 15An is entered into this shift register.

A spatial and time coordination of the time channels of the two t.d.m. lines is thus established.

As already indicated, the intermediate storage of items of information belonging to other connections takes place simultaneously to the above described processes, in others of the shift registers Schl to Schl 6.

WHAT WE CLAIM IS 1. A t.d.m. switching network comprising a plurality of groups of t.d.m. lines, which groups intersect with one another to form a matrix, and at each intersection a switching network unit is connected to the individual lines of the two groups defining the intersection via which switching network unit connections can be etablished each between any two t.d.m. lines of the two groups, each switching network unit providing a spatial and time coordination of time channels formed on the connected t.d.m. lines and having a smaller traffic handling capacity than that of the t.d.m. lines to which it is connected.

2. A switching network as claimed in Claim 1 wherein a plurality of switching network units are connected in parallel with one another at one or more of the intersections.

3. A switching network as claimed in Claim 1 or Claim 2 wherein the switching network units are all identical to one another.

4. A switching network as claimed in any one of Claims 1 to 3 wherein the groups of t.d.m. lines form column line groups and row line groups of a rectangular matrix.

5. A switching network as claimed in any one of Claims 1 to 3 wherein each group of t.d.m. lines intersects each other group of t.d.m. lines to form a triangular matrix.

6. A t.d.m. switching network comprising a plurality of similar rectangular matrix switching networks each as claimed in Claim 4 and a plurality of similar triangular matrix switching networks each as claimed in Claim 5, wherein the column or the row line groups of each rectangular matrix are each connected to a respective group of t.d.m. lines of a respective one of the triangular matrices via a respective group of intermediate lines.

7. A t.d.m. switching network comprising a plurality of identical rectangular matrix switching networks each as claimed in Claim 4, wherein the lines of the column or the row line groups of each matrix are connected each to a corresponding line of a respective one of the other matrices via a respective intermediate line.

8. A t.d.m. switching network substantially as herein described with reference to Figs. 1 and 2, or Figs. 1 and 3, or Figs. 1 to 4, or Figs. 1, 2 and 5 of the accompanying drawings.

9. A switching network, for a PCM exchange system, as claimed in any one of the preceding claims, wherein each switching network unit comprises a time stage comprising a plurality of parallel-connected shift registers each having as many stages as there are bits in each PCM word, an input end spatial stage comprising a multiplexer having a plurality of switches each of which serves to couple a respective incoming pair of t.d.m. line wires to the shift register inputs, and an output end spatial stage comprising a demultiplexer having a like plurality of switches each of which serves to couple the shift register outputs to a respective outgoing pair of t.d.m. line wires, the switches of the multiplexer and the demultiplexer which serve for the coupling of associated incoming and outgoing pairs of t.d.m. line wires being arranged to be operated in synchronism with one another.

10. A switching network as claimed in Claim 9 wherein each switching network unit further comprises a holding set comprising as many parallel-connected shift registers as there are time channels on each t.d.m. line each of which can simultaneously store a first address identifying any switch of the multiplexer and demultiplexer and a second address identifying any one of the shift registers of the time stage, the outputs of the holding set shift registers being connected via a first switch, which is arranged to be closed for the duration of read out from any of the shift registers of each first address, to a first series-parallel converter whose outputs are connected to inputs of a first decoder which supplies control signals for the switches of the multiplexer and demultiplexer, via a second switch, which is arranged to be closed for the duration of read out from any of the shift registers of each second address, to a second series-parallel converter whose out

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. out from the shift register SchH10 are entered back into this shift register via the closed switch K3. In this way information supplied in the time channel 10 on the incoming pair of line wires lAn of the first t.d.m. line is supplied via the switch SE1 and the incoming supermultiplex line SME to the shift register Schl, and at the same time information already contained in this shift register Schl is fed via the outgoing super-multiplex line SMA and the switch SA1 to the outgoing pair of line wires lAb of this t.d.m. line.In the same manner, during the time channel 20 the addresses of the switches SE15 and SA15 and the shift register Schl are read out from the shift register SchH20 and are decoded, so that during this time channel the switches SE15 and SA15 are closed, and the information meanwhile stored in the shift register Schl is output to the outgoing pair of line wires 15Ab whereas information incoming during this time channel on the incoming pair of line wires 15An is entered into this shift register. A spatial and time coordination of the time channels of the two t.d.m. lines is thus established. As already indicated, the intermediate storage of items of information belonging to other connections takes place simultaneously to the above described processes, in others of the shift registers Schl to Schl 6. WHAT WE CLAIM IS

1. A t.d.m. switching network comprising a plurality of groups of t.d.m. lines, which groups intersect with one another to form a matrix, and at each intersection a switching network unit is connected to the individual lines of the two groups defining the intersection via which switching network unit connections can be etablished each between any two t.d.m. lines of the two groups, each switching network unit providing a spatial and time coordination of time channels formed on the connected t.d.m. lines and having a smaller traffic handling capacity than that of the t.d.m. lines to which it is connected.

puts are connected to inputs of a second decoder which supplies release signals for shift pulse trains for the shift registers of the time stage, and via a third switch, which is arranged to be opened only during entry of new addresses into the holding set shift registers, to the inputs of these shift registers, the holding set further comprising a further shift register having as many stages as there are time channels on each t.d.m. line and arranged to supply a release signal for a shift pulse train for each of the holding set shift registers in turn each for the duration of a respective time channel of the t.d.m. pulse frame.

11. A switching network as claimed in any one of Claims 1 to 8 wherein each switching network unit is substantially as herein described with reference to Fig. 6 of the accompanying drawings.