GB1575326A - Telegraph circuit - Google Patents

Description

(54) TELEGRAPH CIRCUIT (71) We, ING. C. OLIVETTI & C., S.p.A., a body corporate organised and existing under the laws of Italy, of Via G.

Jervis 77, 10015, Ivrea, Italy, do hereby declare the invention, for which we pray that a Patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention relates to a telegraph circuit for automatically detecting and correcting the direction of the current in a two-wire telegraph line operating with single current, when current of incorrect polarity persists beyond a predetermined time.

As is known in the art of telegraphic transmissions on a switched single current two-wire line, the signals transmitted by a teleprinter or other device to the exchange and vice versa are constituted by changes in polarity and amplitude of the current flowing in the line and by the duration of the interval between two successive changes.

Thus, for example, in the inoperatve state the line current has a value of - SmA; in the calling stage of the teleprinter, the current changes to a value of - 40 mA and thereafter changes over to + 40 mA. The maximum duration of persistence or absence of current in the line does not normally exceed about 3 seconds. Any interruption of current longer than about 3 seconds is interpreted by the exchange as trouble on the line and the teleprinter concerned is, therefore, disconnected automatically until the line is reinstated.

It may sometimes happen that, during normal maintenance when the line must be cut off, the wires of a pair are inadvertently reversed. In fact, the two wires of the same pair are normally of the same colour, so that once they are disconnected from the line it is not possible to distinguish them to reconnect them in the same way. Therefore, in the case where the wires of a pair are reconnected in the reverse sense, the teleprinter will receive from the exchange and will send signals of opposite sign with respect to the norm to the exchange, creating an abnormal situation. It is clear that in these circumstances the exchange will put the wrongly connected teleprinter "out of service". Manual devices are known in the art for reversing the direction of the current in the line.One of these devices consists of a relay actuated manually by the exchange operator by means of a push button located at the telegraph exchange. The relay changes over the two wires of the line by crossing the connection between the exchange and the teleprinter.

When the exchange signals that there is a fault on the line, the operator presses the push button to actuate the relay. If the fault consists in the reversal of the wires by a person employed on maintenance of the line, the actuation of the relay brings the line back to the operative condition, because there are now two reversals in the line.

The known device described requires the presence of a person at the exchange for reinstating the line if necessary and is, therefore, not suitable for being employed in automatically operating telegraph networks. Moreover, in the case of teleprinters operating the "unattended" mode, the use of such a device restricts the operation thereof in an unacceptable manner because of the long time elapsing between the impairment of the line and the intervention of the operator to reinstate it.

The object of the present invention is automatically to detect the direction of the current in the line after a given interval of time starting from an interruption and automatically to reverse the connections of the two line wires if the current proves to be of opposite direction with respect to telegraph conventions.

According to the present invention, there is provided a telegraph circuit for automatically detecting and reversing the polarity of the current in a two-wire telegraph line, comprising the line, a reversing device in the line, detecting means connected in series with one wire of the line for detecting the polarity of the current flowing, an oscillator, a first frequency divider connected to the oscillator and enabled by the detecting means when current of either polarity flows for defining a first given time interval, and a control circuit including a first bistable circuit arranged under the control of the detecting means to assume first and second states when the detected polarity of current is correct and incorrect respectively and arranged to actuate the reversing device when in the second state, the control circuit being further so arranged under the control of the first frequency divider that the reversing device is not actuated until the conclusion of the first time interval.

The circuit preferably further comprises a second frequency divider connected to the oscillator and enabled by the detecting means when no current of either polarity flows for defining a second given time interval much longer than the first time interval, with the control circuit including a second bistable circuit having first and second inputs connected to the second and first frequency dividers respectively and arranged under control of the second frequency divider to assume a first state at the end of the second time interval when no current of either polarity flows and under control of the first frequency divider to assume a second state at the end of the first time interval when current of either polarity flows, and a logical circuit preventing actuation of the reversing device so long as the second bistable circuit is in the first state.

The durations of the said time intervals will naturally be adapted to the signalling standards employed and these will determine how much longer the second interval must be than the first. However, it can be understood that the second interval will be at least one order of magnitude greater than the first.

An embodiment of the invention will be described, by way of example, in conjunction with the accompanying drawing.

Referring to the drawing, a two-wire line L connects a telegraph exchange CT to a peripheral unit TS for transmitting and receiving data, for example a teleprinter.

The line L is interrupted by a two-position polarity change-over switch ID. Under normal conditions, the two terminals a and b of the switch ID are connected to the terminals c and e, respectively. When an electromagnet 18 is energised, in the manner which will be described hereinafter, the terminals a and b of the switch ID are connected to the terminals d and f, respectively, so that the wires of the line L to the left of the switch ID are connected in crossed fashion to the corresponding wires of the line L to the right of the switch ID.

In series with one of the two wires of the line L, for example the lower wire in the drawing, there are connected two optoelectronic devices S and 6, respectively. Each of the optoelectronic devices is composed of a photodiode (light-emitting diode) 5', 6' optically coupled to a photo-transistor 5", 6", the two elements being enclosed in a single container. The two diodes 5' and 6' are connected in parallel with one another but with opposite polarities (i.e. back to back) and the parallel diodes are disposed in series with one wire of the line L. In parallel with the diodes, there are connected, firstly, two Zener diodes 2, 3, in series with one another and connected in opposition, and, secondly, a capacitor 4.The Zener diodes 2 and 3 and the capacitor 4 constitute a protective circuit for the diodes 5' and 6' against possible sudden over-currents on the line.

Each of the two phototransistors 5" and 6" is connected between earth M and a source of positive voltage T through limiting resistors 7 and 8 respectively.

When current is not flowing on the line, both photodiodes' 5' and 6' are deenergized, and so also are the two phototransistors 5" and 6", so that on the collectors 51 and 52 of the two phototransistors there is present a signal at high level (LIPOA = 1; LINEA = 1). When a positive current flows in the line, to which there correspond, in accordance with telegraph conventions, the positive signal MATE 3 and the negative signal LICO 2, the signal LIPOA = 0 and LINEA = 1 are obtained at the collectors 51 and 52, respectively. Conversely, when a negative current flows in the line, MATE 3 is negative, LICO 2 is positive and LIPOA = 1 and LINEA = 0, respectively, are obtained at the collectors 51 and 52.

A relaxation oscillator 40 is constituted by two inverters 25 and 28 in series with one another, two resistors 26 and 27 in series with one another and located between the output and the input of the inverter 28, and a capacitor 29 connected between the output of the inverter 25 and the point K common to the two resistors 26 and 27. The signal generated by the oscillator 40 and present on the wire 41 has a frequency defined by the values of the capacitor 29 and of the resistors 26 and 27. It is used as a timing clock signal for the entire circuit, as will be described hereinafter and is called CLOC 5.

A resistor 34 and a capacitor 33 in series are connected between the source of positive voltage T and earth M. The intermediate point N between the resistor 34 and the capacitor 33 is connected to the input of an inverter 35. In the switching-on of the apparatus, the capacitor 33 is charged and a signal SEIN B of logical 1 value appears at the point N, while at the output 66 of the inverter 35 the signal SEIN 1 has 0 value.

A NAND gate 37 having two inputs is connected by a wire 53 to the collector 51 of the phototransistor 5" and by a wire 54 to the collector 52 of the phototransistor 6".

The output RECO1 of the gate 37, i.e., the NAND of LIPOA and LINEA, is applied by means of a wire 56 to the RESET terminal of a 14-bit binary counter 31, which divides by 2l4 the frequency of the signal CLOC 5 present on an input wire 57 connected to the output wire 41 of the oscillator 40. A NAND gate 36 with two inputs has its first input 58 connected to receive the signal Rue 01, its second input connected to the point N at logical 1 level between the capacitor 33 and the resistor 34, and its output 60 (signal RECOB) connected to the reset terminal 61 of a seven-bit .binary counter 32 which divides by 27 the frequency of the signal CLOC 5 present on an input wire 62 connected to the output wire 41 of the oscillator 40.

The outputs 63 and 64, respectively, of the counters 31 and 32, signals SEDR1 and REAV1, are connected to the terminals J and K, respectively, of a flip-flop 30, while a set terminal 65 is connected to the output 66 of the inverter 35, i.e., the logical 0 signal SEIN1. The timing of the flip-flop 30 is effected by using the signal CLOC 5 present on a wire 67 connected to the output 41 of the oscillator 40.

The collectors 51 and 52 of the phototransistors 5" and 6" are connected through inverters 23 and 21, respectively, to the terminals J' and K' of a flip-flop 22, a reset terminal 68 of which is connected to the output 66 of the inverter 35, i.e., the logical 0 signal SEIN1.

The timing of the flip-flop 22 is effected by means of the signal CLOC 5 conditioned by a NAND gate 20, an input 70 of which is connected to the direct output RITAO of the flip-flop 30 and the second input 71 of which is connected to the output 41 of the oscillator 40. The negated output 72 of the flip-flop 22, signal COELN, is connected to a first input of a NAND gate 24, while the negated output RITAN of the flip-flop 30 is connected to the second input of the gate 24. The output 73 of the gate 24, COELA, is connected to an inverter 11 which drives an actuating circuit for the electromagnet 18 and which is composed of transistors 13 and 15 and resistors 12 and 14. This circuit is a conventional amplifier circuit.

Connected in parallel with the electromagnet 18 is a diode 19 for shunting the reverse voltages which appear across the coil 18 on the opening of its driving circuit.

The coil of the electromagnet 18 is fed through a resistor 16 by a voltage source T1.

In the case of an interruption on the line, the signals LIPOA and LINEA both assume logical 1 value. The signal RECO1 is, therefore, at 0 value, which removes the reset command of the counter 31, which therefore begins to count the pulses which arrive from the oscillator 40 on the wire 57.

After about six seconds, the signal SEDE1 at the output 63 of the counter 31 is brought to 1 value, which sets the flip-flop 30, so that the signal RITA0 goes to 1 and the signal RITAN goes to 0. The cause of interruption on the line L having ceased, one of the two signals LIPOA and LINEA goes to 0 and, therefore, the signal RECO1 on the wire 56 also returns to level 1. The counter 31 is reset, but at the same time the counter 32 begins the count, since the signal RECOB at the output 60 of the gate 36 assumes level 0 and removes the reset command of the flip-flop 32.

After about 45 ms, the output REAV1 at the terminal 64 of the counter 32 goes to 1, effecting the reset of the flip-flop 30: RITAO goes to 0 and RITAN goes to 1. If, for maintenance purposes, the pair of wires L has been disconnected, two alternatives may present themselves on restoration of the connection: the two wires of the line are reconnected correctly and a current will then flow again in the conventionally correct direction; or the two wires are reconnected crossed and the direction of the current flowing will then be inverted.

In the first case, in which the line current flows in the correct direction, it has already been seen that the signal MATE 3 is positive, so that the signal LINEA has the value 1 and the signal LIPOA has the value 0. Under these conditions, after 45 ms, from the beginning of the count by the counter 32, the flip-flop 30 is reset, RITAO goes to 1 and the gate 20 therefore allows the timing signal for the flip-flop 22 to pass. However, the flip-flop 22 cannot be set inasmuch as the signal LIPO2 at the input J' has the value 1 and the signal LINE2 at the input K' has the value 0. At the output 72 of the flip-flop 22, the signal COELN remains at O.

The signal RITAN also has the value 0, so that the gate 24 is blocked and the signal COELA at the output 73 has the value 1.

Even when, as already stated, the signal REAV1, goes to 1 after 45 ms, and causes the flip-flop 30 to reset, bringing the signal RITAN to 1 value, the gate 24 does not change over and the signal COELA remains at 1. Therefore, in response to the signal COELA = 1, the inverter 11 delivers as output a signal COEL2 at level 0, so that the transistors 13 and 15 and the electromagnet 18 are not activated. The changeover switch 10, therefore, remains in its rest position as shown in the drawing.

Conversely, if, on reinstatement of the line, the pair of wires is reconnected crossed, then a current of opposite direct with respect to the conventional direction will flow in the line. In this case, LICO 2 is positive and MAT 3 is negative. Consequently, LINEA = 0 and LIPOA = 1. The counter 31 is blocked, (reset) RECO1 being = 1, and the counter 32 begins to operate, since the signal RECOB = 0 removes the reset command at the terminal 61 of the counter 32. During the first 45 ms, when REAV1 is at 0 value, the signal RITAO is at 1 value and the signal RITAN is at 0 value.

The flip-flop 22 is clocked via the gate 20.

Now, however, LIPO2 has 0 value and LINE 2 has 1 value, so that the flip-flop 22 is set to change over the signal COELN to 1 value. After 45 ms, the signal RITAN changes over to 1 value, as already seen, and the gate 24, therefore, changes over the signal COELA to 0 value. The inverter 11 delivers a signal COEL 2 at level 1 and the transistors 13 and 15 and the electromagnet 18 are, therefore, activated, so that the changeover switch ID is brought from the previous position c - e to the position d thus reversing the connections of the pair of wires of the line L. Consequently, the line current will arrive at the teleprinter TS in the conventionally correct direction.

It is pointed out that the internal circuits of the counters 31 and 32, the flip-flops 22 and 30, the NAND gates 20, 24, 36 and 37 and the inverters 11, 21, 23, 25 and 28, represented in the drawing by their conventional graphic symbols, are not described in detail since they are standard circuits.

In summary, the flip-flop 30 (second bistable circuit) is set to a first state at the end of the 6 second time interval (second time interval) established by the counter 31 (second frequency divider), and reset to the second state at the end of the 45 ms time interval (first time interval) established by the counter 32 (first frequency divider). The flip-flop 22 (first bistable circuit) is set to the second state when the flip-flop 30 is set, only if LIPOA = 1 and LINEA = 0 (wrong polarity). The reversing device is actuated only when the flip-flop 22 is thus set and the flip-flop 30 resets to the second states so that the logical circuit 24 receives two logical 1 inputs (both flip-flops in their second states).

WHAT WE CLAIM IS: 1. Telegraph circuit for automatically detecting and reversing the polarity of the current in a two-wire telegraph line, comprising the line, a reversing device in the line, detecting means connected in series with one wire of the line for detecting the polarity of the current flowing, an oscillator, a first frequency divider connected to the oscillator and enabled by the detecting means when current of either polarity flows for defining a first given time interval, and a control circuit including a first bistable circuit arranged under the control of the detecting means to assume first and second states when the detected polarity of current is correct and incorrect respectively and arranged to actuate the reversing device when in the second state, the control circuit being further so arranged under the control of the first frequency divider that the reversing device is not actuated until the conclusion of the first time interval.

2. Telegraph circuit according to claim 1, further comprising a second frequency divider connected to the oscillator and enabled by the detecting means when no current of either polarity flows for defining a second given time interval much longer than the first time interval, and wherein the control circuit includes a second bistable circuit having first and second inputs connected to the second and first frequency dividers respectively and arranged under control of the second frequency divider to assume a first state at the end of the second time interval when no current of either polarity flows and under control of the first frequency divider to assume a second state at the end of the first time interval when current of either polarity flows, and a logical circuit preventing actuation of the reversing device so long as the second bistable circuit is in the first state.

3. Telegraph circuit according to claim 2, wherein the first bistable circuit is prevented from changing state when the second bistable circuit is in its second state.

4. Telegraph circuit for automatically detecting and reversing the polarity of the current in a two-wire telegraph line, substantially as hereinbefore described with reference to, and as illustrated in, the accompanying drawing.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (4)

**WARNING** start of CLMS field may overlap end of DESC **. output a signal COEL2 at level 0, so that the transistors 13 and 15 and the electromagnet 18 are not activated. The changeover switch 10, therefore, remains in its rest position as shown in the drawing. Conversely, if, on reinstatement of the line, the pair of wires is reconnected crossed, then a current of opposite direct with respect to the conventional direction will flow in the line. In this case, LICO 2 is positive and MAT 3 is negative. Consequently, LINEA = 0 and LIPOA = 1. The counter 31 is blocked, (reset) RECO1 being = 1, and the counter 32 begins to operate, since the signal RECOB = 0 removes the reset command at the terminal 61 of the counter 32. During the first 45 ms, when REAV1 is at 0 value, the signal RITAO is at 1 value and the signal RITAN is at 0 value. The flip-flop 22 is clocked via the gate 20. Now, however, LIPO2 has 0 value and LINE 2 has 1 value, so that the flip-flop 22 is set to change over the signal COELN to 1 value. After 45 ms, the signal RITAN changes over to 1 value, as already seen, and the gate 24, therefore, changes over the signal COELA to 0 value. The inverter 11 delivers a signal COEL 2 at level 1 and the transistors 13 and 15 and the electromagnet 18 are, therefore, activated, so that the changeover switch ID is brought from the previous position c - e to the position d thus reversing the connections of the pair of wires of the line L. Consequently, the line current will arrive at the teleprinter TS in the conventionally correct direction. It is pointed out that the internal circuits of the counters 31 and 32, the flip-flops 22 and 30, the NAND gates 20, 24, 36 and 37 and the inverters 11, 21, 23, 25 and 28, represented in the drawing by their conventional graphic symbols, are not described in detail since they are standard circuits. In summary, the flip-flop 30 (second bistable circuit) is set to a first state at the end of the 6 second time interval (second time interval) established by the counter 31 (second frequency divider), and reset to the second state at the end of the 45 ms time interval (first time interval) established by the counter 32 (first frequency divider). The flip-flop 22 (first bistable circuit) is set to the second state when the flip-flop 30 is set, only if LIPOA = 1 and LINEA = 0 (wrong polarity). The reversing device is actuated only when the flip-flop 22 is thus set and the flip-flop 30 resets to the second states so that the logical circuit 24 receives two logical 1 inputs (both flip-flops in their second states). WHAT WE CLAIM IS:

1. Telegraph circuit for automatically detecting and reversing the polarity of the current in a two-wire telegraph line, comprising the line, a reversing device in the line, detecting means connected in series with one wire of the line for detecting the polarity of the current flowing, an oscillator, a first frequency divider connected to the oscillator and enabled by the detecting means when current of either polarity flows for defining a first given time interval, and a control circuit including a first bistable circuit arranged under the control of the detecting means to assume first and second states when the detected polarity of current is correct and incorrect respectively and arranged to actuate the reversing device when in the second state, the control circuit being further so arranged under the control of the first frequency divider that the reversing device is not actuated until the conclusion of the first time interval.

2. Telegraph circuit according to claim 1, further comprising a second frequency divider connected to the oscillator and enabled by the detecting means when no current of either polarity flows for defining a second given time interval much longer than the first time interval, and wherein the control circuit includes a second bistable circuit having first and second inputs connected to the second and first frequency dividers respectively and arranged under control of the second frequency divider to assume a first state at the end of the second time interval when no current of either polarity flows and under control of the first frequency divider to assume a second state at the end of the first time interval when current of either polarity flows, and a logical circuit preventing actuation of the reversing device so long as the second bistable circuit is in the first state.

3. Telegraph circuit according to claim 2, wherein the first bistable circuit is prevented from changing state when the second bistable circuit is in its second state.

4. Telegraph circuit for automatically detecting and reversing the polarity of the current in a two-wire telegraph line, substantially as hereinbefore described with reference to, and as illustrated in, the accompanying drawing.