GB1575074A - Buffer store control arrangements - Google Patents

Abstract

This arrangement makes it possible for the information unit to be exchanged between the buffer memory and a functional unit, for example a peripheral unit, to be different in format and number from the information unit to be exchanged between the other functional unit, for example a sample-and-hold memory and the buffer memory. For this purpose, the information traffic between one functional unit and the buffer memory (PS) is controlled by a first control circuit (STB), and the information traffic between the second functional unit and the buffer memory (PS) is controlled by a second control circuit (STA). The control circuits generate addresses which specify the storage location of the buffer memory into which and from which information can be written and read. A comparison circuit (VG) determines when the addresses allocated to the two functional units correspond to one another and then generates an inhibit signal. The two control circuits are influenced with the aid of a control flip flop (FF) in such a manner that one functional unit in each case exchanges one information item and the other functional unit one block of information items with the buffer memory. <IMAGE>

Description

(54) IMPROVEMENTS IN OR RELATING- TO BUFFER STORE CONTROL ARRANGEMENTS (71) We, SIEMENS AKTIENGESELLSCHAFT, a Germany Company, of Berlin and Munich, Federal Republic of Germany, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to a buffer store control arrangement.

In data processing systems buffer stores are required at various points. The functions of these buffer stores is, for example, to match function units having information paths of different widths, different transmission speeds or different real time characteristics.

An example of the use of a buffer store within a data processing system is for data transmission between a peripheral unit and a main or working store constituting respective function units. This data transmission is carried out via an input output unit, which contains control circuits, switches ,and registers which are responsible for ensuring that the data transmission takes place in the correct manner, and a buffer store which intermediately stores the items of data to be transmitted. Intermediate storage is necessary because the rate at which the peripheral unit supplies or withdraws information differs from the rate at which the working store emits or receives information. Furthermore the path width of the connection of the peripheral unit to the input/output unit can differ from that of the connection of the input/output unit to -the working store. The buffer store must be suitable to store information transmitted in both directions between the peripheral unit and the working store, and in addition it must be ensured that the read-out process from the buffer store does not overtake the write-in process to the buffer store and vice versa.

German Auslegeschrift No. 1 247 050 discloses a buffer store in which attempts to read out from the buffer store more data than has ben entered therein are prevented by the use of two address registers which are constructed as counters, one of which indicates the address of that storage position in the buffer store into which an item of information is to be written and the other of which indicates the address of that storage position from which the next item of information is to be read out, and a comparator which compares the contents of the two address registers with one another and in the event of an identity inhibits the read-out process from the buffer store.

In each case only one unit of information unit, e.g. a data word, can be written into and read out from this known buffer store. However, in data processing systems it is often necessary for the format and number of information units which are exchanged in each operating cycle between the buffer store and the function unit to be different for the different function units.

For example, in order to reduce the frequency of accesses to the working store during the transmission of information between a peripheral unit and the working store, in- each case only half a data word might be exchanged between the peripheral unit and the buffer store whereas four data words might be exchanged between the buffer store and the working store in an operating cycle.

This invention seeks to provide a buffer store control arrangement which enables information units which differ in respect of format and number to be exchanged between a buffer store and respective function units between - which the buffer store is connected.

According to this invention there is pro vided a -buffer store arrangement for intermediate storage of items of information transmitted between two function units, comprising a buffer store, a first control circuit which serves to control information traffic between the buffer store and the first function unit, a second control circuit which serves to control information traf fic- between the second function unit and the buffer store, the first and second control circuits being such that information can be transmitted from one function unit to the buffer store and from the buffer store to the other function unit simultaneously, addressing means for producing addresses of storage, positions of the buffer store into which write-in is to be effected and addresses of storage positions of the buffer store from which read-out is to be effected, a comparator arranged to compare the addresses for write-in to the buffer store with the addresses for read-out from the buffer. store and to provide an output whenever the addresses are such as would result in an attempt to access any storage position for both reading and writing simultaneously, a bistable stage, and a logic element having an input connected to an output of the comparator, wherein the bistable stage has a control input connected to an output of the first control circuit to be controlled thereby and an output connected to an input of the.second control circuit and to another input of the logic element; the arrangement being such that the bistable stage is set to a first state by the first control circuit whenever transmission of a predeermined amount of information is possible between the buffer store and the second function unit in the selected transmission direction and is reset to a second state when a first item of information has' been transmitted between the second function unit and the buffer store iii the selected direction and the logic element supplies a blocking signal to the first control circuit Whefl both the bistable stage is in the first state and the comparator provides said output.

Thus' the -bistable stage and the comparator together ensure that read-out from the buffer store cannot overtake write-in to"' "the"' buffer store; or vice versa. The bistable btag:alsd;' however, enables the number and format of information units trans'ri'itie'd' b"e'tw'ee'n' one function - unit -'and the 'buffe'r" store t6 differ' from the number and format of informationt knits ex- chang"ed" 'bet'we"en -the buffer-" stor'e - and the other function unit where the information units can be of different formats. To this end the bistable stage is set to the first state by the first control circuit whenever the first function unit has written into the buffer store the number of information units required for the further transmission to the other function unit. The bistable stage then supplies the second control circuit with a signal which informs the latter that it is possible to transmit the corresponding number of information units between this other function unit and the buffer store.

The invention also extends to a data processing system comprising two function units and such a buffer store arrangement, the buffer store being arranged for the intermediate storage of items of information transmitted between the two function units.

The invention will be further described from the following description by way of example of an embodiment thereof with reference to the accompanying drawings, in which: Fig. 1 schematically illustrates an example of the arrangement of a buffer store within a data processing system; and Fig. 2 schematically illustrates a buffer Store and a control arrangement for controlling the intermediate storage of data in the buffer store.

Fig. 1 illustrates parts of a data processing system comprising a main or working store ASP, an input! output unit IOC including a buffer store PS, and a peripheral unit PE with an interface a between the working store ASP and the input/ output unit IOC and an interface b between the input/output unit IOC and the peripheral unit PE. Information is exchanged between the buffer store PS and the peripheral unit PE constituting a first function unit via the interface b, and between the buffer store PS and the working store constituting a second function unit via the interface a. For controlling the buffer - store PS and the interfaces a and b for this purpose the input/output unit IOC includes a first control circuit STB which controls the information traffic via the interface b and a second control circuit STA which controls the infornia- tion traffic via the interface a. The control circuits STB and STA also ensure that items of information which are to be transmitted are stored in and withdrawn from the correct storage positions of~the buffer store PS. Fig. 1 merely indicates "-how' a buffer store can be arranged in -a data processing system, and further description of the function units of such a "data 'pro'- cessing system is not necessary here.

In the following description with reference to Fig. 2 it is assumed that information is exchanged between the first function unit (the peripheral unit PE) and the buffer store PS via a path having a width 6f 2 bytes, and is exchanged between the second function unit (the working store ASP) and the buffer store PS via a path having a width of 4 bytes, these different formats being matched in the buffer store PS. It is also assumed that in an operating cycle one unit of information comprising 2 bytes can be transmitted between the peripheral unit PE and the buffer store PS via the interface b and four units of information each comprising 4 bytes can be transmitted between the buffer store PS and the working store ASP via the interface a. Here 2 bytes are referred to as one half word and 4 bytes are referred to as one word. An information block consists of 4 words, i.e. 16 bytes. Naturally the invention is not limited to this particular example.

Referring now to Fig. 2, the buffer store PS is constituted by four register sets PS1 to PS4, each of which can accommodate four information units each of 2 bytes.

Thus 4 words (a block) can be stored in the register sets PSl and PS2 together, and four words can be stored in the register sets PS3 and PS4 together.

The interfaces a and b, having widths of 4 bytes and 2 bytes respectively, are connected to inputs of the register sets PS1 to PS4 via logic elements LG1 and LG2, one or the other of which is enabled to feed items of information to the buffer store PS in dependence upon a signal from the first control circuit STB which is fed to a logic element LG3 and which for example is a binary 1 when the transmission direction is from the interface a to the interface b. Outputs of the register sets PS1 to PS4 are connected directly to the interface a and via another logic element LG4 to the interface b, which logic element determines which half word is to be transmitted from the buffer store PS via the interface b to the finst function unit.

addresses of these storage positions of the buffer store PS into which information is to be written and frond which it is to be read out are determined with the aid of address registers which are constituted by counters. An address register which is assigned to the" interface" b and hence to the first function unit connected thereto is referenced KZ, and an address register which is- assigned to the interface; a and hence to the'' second function unit connected thereto is: referenced MZ. Counter pulses which serve to 'modify the contents dStheX address registers Kz and MZ are produced by the control 'circ'luits"" STB and STA respectively and are conducted directly to the address - reg'iste""r MZ and via a NED 'gate" -NGl to thee address register E. Outputs 'of" 'The address' registers MZ arid E are connected to decoder circuits SA and LA, which operate the relevant storage positions in the buffer store PS.

The decoder circuit SA operates those storage positions of the buffer store PS into which information is to be written, and the decoder circuit LA operates those storage positions of the buffer store PS from which information is to be read out.

Drive lines lead from outputs of the decoder circuits SA and LA to the individual register sets PS1 to PS4 of the buffer store PS.

Selection of the register sets PS1 to PS4 for information transfer is determined by decoder circuits SE and LE, the circuit SE determining those register islets into which write-in is to be effected and the circuit LE determining those register sets from which information is to be read out.

The time of the selection of the register sets PS1 to PS4 is determined by a write-in pulse WB from the first control circuit STB and WA from the second control circuit STA. In addition the circuit SE is connected to the decoder circuit SA and the circuit LE is connected to the decoder circuit LA; cooperation between each decoder circuit and the decoder circuit connected thereto enables any arbitrary storage position of any register set PS1 to PS4 to be addressed.

As already explained, the address register KZ is operated by the first control circuit STB via a NAND gate NG1 which selects those counting pulses from the control circuit STB which are to serve to modify the contents of the address register KZ. The three highest order outputs of the address register KZ are additionally connected to inputs of a comparator VG, this connection of only the three highest order outputs being sufficient because the data transmission via the interface b is carried out in half words. The outputs of the address register MZ, which is caused to count upwardis by the second control circuit STA, are not connected directly to inputs of the comparator circuit VG but via a further register MZR, the function of which is to synchronise signals conducted to the comparator VG from the address register MZ with those conducted thereto from the address register KZ, this being necessary because the two control circuits STB and STA operative asynchronously to one another whereas comparisons of the contents of the address registers MZ and KZ are only effectiye in the case of synchronous operation. A circuit ,,EP derives from the pulses emitted by the second control circuit STA ,pulses which fit into the pulse train pattern of the first control circuit STB and, feeds, Shese pulses to the register MZR, which in response to each pulse receives'the contents of the address register MZ and presents these to the comparator VG. The comparator VG thus compares the contents of the address register MZ with the contents of the three highest order positions of the address register KZ and in the event of identity applies a signal to one input of a NAND gate NG2, another input of which is connected to an output o fa control flipflop (bistable stage) FF.

The outputs of the address register KZ are also connected to inputs of a circuit SK which determines when a block of infortion has been transmitted via the interface b and in this event emits a signal to the first control circuit STB. In response to this signal the first control circuit STB causes the control flip-flop FF to be set if it is not already set. If it is already set the control circuit STB causes the control flip-flop FF to be set again when it is next reset. The resetting is effected from the second control circuit STA whenever the first information word of a block has been transmitted via the interface a.

This is effected with each change in address, and thus it is possible to use the lowest order position of the address register MZ as an indication to this effect.

Accordingly a resetting input of the control flip-flop FF is connected to the output of a NAND gate NG3 one input of which is connected to the lowest-order output of the register MZR and another input of which is connected to the output of the circuit EP.

-The output of the control flip-flop FF is also connected to an input of the second control circuit STA, since the control flipflop FF indicates when a block of information has been transmitted via the interface b into the buffer store PS and when the first data word has been withdrawn there from. The output signal of the control flip-flop FF is thus an indication to the second control circuit STA that the latter can be operated to transmit an information block via the interface a.

In the following the situation in which the direction of operation is from the interface b to the interface a, for example information being transmitted from the peripheral unit PE via the interface b into the buffer store PS and from there via the interface a to the working store ASP, will be described. Initially the buffer store PS is empty, the address registers MZ and 1tZ have counbs of zero, and the control flip-flop FF is in the reset state.

For the transmission of information via the interface b into the buffer store PS 2 bytes at a time, the first control circuit STB becomes operative and produces a write-in pulse WB. The address of that storage position in the buffer store PS into which the first item of information is to be written is obtained from the ad- dress register KZ whose contents are decoded in the decoder circuit SA. As described above, the first storage position is then selected in for example the register set PS of the buffer store PS. Then the control circuit STB increases the contents of the address register KZ by 1. The next item of information is stored in the buffer store PS using the new address formed in the address register KZ, for example in the first storage position of the register set PS2. This process is repeated until the register sets PS1 and PS2 are full, at which time 16 bytes have been transferred into the buffer store PS. The circuit SK realises this from the address of the address register KZ and emits an output signal to the first control circuit STB which latter consequently sets the control flip-flop FF.

In this way the second control circuit STA is informed that it can take an information block from the buffer store PS.

Assuming that the second control circuit STA is not yet ready to take an information block from the buffer store PS, the first control circuit STB is still able to carry out further entry of information into the buffer store and in fact to fill the register sets PS3 and PS4. When these register sets PS3 and PS4 are full, i.e. when a second information block of 16 bytes has been transmitted via the interface b into the buffer store PS, the circuit SK again emits a signal to the first control circuit STB. However, as the control flipflop FF is still set, the control circuit STB cannot set the control flip-flop again, and instead it delays the setting process for the control flip-flop FF until the control flip-flop FF has been reset by the second control circuit STA.

If the buffer store PS is completely full, the address in the address register KZ is zero again. As the address in the address register MZ is likewise zero, the comparator VG emits a signal to one input of the NAND gate NG2, the other input of which also receives a signal from the control flip-flop FF. Thus the NAND gate NG2 produces at its output a blocking signal which indicates to the first control circuit STB that the latter is not allowed to carry out further processing. The county ing pulse train from the first control circuit STB to the address register KZ is interrupted accordingly.

When the second control circuit STA commences to transmit an information block in the buffer store PS via the interface a, when the first word has been taken, the contents of the address register MZ are modified and thus a resetting pulse for the control flip'flop FF is produced and the 'latter is reset. The control circuit STA how continues to operate independently of the control circuit STB until it has with drawn the information block from the buffer store. If, having read out the first information block from the buffer store PS via the interface a the second control circuit STA establishes that the control flip-flop FF is set again, it commences to read out the second information block from the buffer store.

Thus with the aid of the comparator VG it is ensured that the read-out process is unable to overtake the write-in process and with the aid of the control flip-flop FF it is ensured that the second control circuit STA becomes operative only when an information block has been transferred via the inter'face' b into the buffer store PS. The comparator VG and the control flip-flop FF thus ensure that faulty input into the buffer store PS or read-out from the buffer store does not occur.

If the direction of the data transmission is from the interface a to the interface b, the transmission process proceeds as follows.

Again it is assumed that initially the buffer store PS is empty and the address registers MZ and KZ are at zero. At the start of the transmission process the control circuit STB must set the control flip-flop FF.

Thus the second control circuit STA is informed that it can commence the data transmission via the interface a into the buffer store PS. When the first word has been transferred into the buffer store PS, the control flip-flop FF is reset in the manner already described. Then the first control circuit STB sets the control flipflop FF again.- 'This is necessary in order to enable the second control circuit STA to fill 'the entire buffer store PS with informa tion'. The second control circuit STA of course can transmit an 'information block into the buffer store PS only when the control flip-flop FF has previously been set. If the buffer store PS is full, the control flip-flop is no longer set and after the transmission > of the second information block the activity - Of the control circuit STA is stop'ped'.

When the first control circuit STB starts the read-out process, firstly, the in 'fd'rraation'W6,r'4s of the first block are read out frdm the buffer store PS in half words and are transmitted via the interface b.

When an information block has been transmitted from the buffer store PS via the interface b, the circuit SK again emits a signal which causes the control circuit STB to set the control fliv-flon FF. Now the second control circuit STA can again commence the information transmission into the buffer store PS. However, again the write-in process can never overtake the read-out process because of the setting of the control flip-flop FF.

Thus items of information can be written into the buffer store PS and items of information can be read out therefrom simultaneously, and it is ensured that the ,write-in process cannot overtake the readout process and the read-out process cannot overtake the write-in process. The buf fer store PS can firstly be entirely filled with the information supplied via one interface before information is transmitted via the other inface.

WHAT WE CLAIM IS:- 1. A buffer store arrangement for intermediate storage of items of information transmitted between two function units, comprising a buffer store, a first control circuit which serves to control information traffic between the buffer store and the first function unit, a second control circuit which serves to control information traffic between the second function unit and the buffer store, the first and second control circuits being such that information can be transmitted from one function unit to the buffer store and from the buffer store to the other function unit simultaneously, addressing means for producing addresses of storage positions of the buffer store into which write-in is to be effected and addresses of storage positions of the buffer store from which read-out is to be effected, a comparator arranged to compare the addresses for write-in to the buffer store with the addresses for read-out from the buffer store and to provide an output whenever the addresses are such as would result in an attempt to access any storage position for both reading and writing simultaneously, a bistable stage, and a logic element having an input connected to an output of the comparator, wherein the bistable stage has a control input connected to an output of the first control circuit to be controlled thereby and an output connected to an input of the second control circuit andto another input of the logic element, th arrangement being such that the -blstabl stage is set' 'to a first state by the first control circuit whenever transmission of a predetermined amount of information ,,'i5 possible, between the buffer store and the second function unit in the selected transmission direction and is reset to a second state when a first item of information has been transmitted between the second function unit and the buffer store in the selected direction, and the logic element supplies a blocking signal to the first control circuit when both the bistable stage is in the first state and the comparator provides said output.

2. An arrangement as claimed in Claim

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (10)

**WARNING** start of CLMS field may overlap end of DESC **. 'latter is reset. The control circuit STA how continues to operate independently of the control circuit STB until it has with drawn the information block from the buffer store. If, having read out the first information block from the buffer store PS via the interface a the second control circuit STA establishes that the control flip-flop FF is set again, it commences to read out the second information block from the buffer store. Thus with the aid of the comparator VG it is ensured that the read-out process is unable to overtake the write-in process and with the aid of the control flip-flop FF it is ensured that the second control circuit STA becomes operative only when an information block has been transferred via the inter'face' b into the buffer store PS. The comparator VG and the control flip-flop FF thus ensure that faulty input into the buffer store PS or read-out from the buffer store does not occur. If the direction of the data transmission is from the interface a to the interface b, the transmission process proceeds as follows. Again it is assumed that initially the buffer store PS is empty and the address registers MZ and KZ are at zero. At the start of the transmission process the control circuit STB must set the control flip-flop FF. Thus the second control circuit STA is informed that it can commence the data transmission via the interface a into the buffer store PS. When the first word has been transferred into the buffer store PS, the control flip-flop FF is reset in the manner already described. Then the first control circuit STB sets the control flipflop FF again.- 'This is necessary in order to enable the second control circuit STA to fill 'the entire buffer store PS with informa tion'. The second control circuit STA of course can transmit an 'information block into the buffer store PS only when the control flip-flop FF has previously been set. If the buffer store PS is full, the control flip-flop is no longer set and after the transmission > of the second information block the activity - Of the control circuit STA is stop'ped'. When the first control circuit STB starts the read-out process, firstly, the in 'fd'rraation'W6,r'4s of the first block are read out frdm the buffer store PS in half words and are transmitted via the interface b. When an information block has been transmitted from the buffer store PS via the interface b, the circuit SK again emits a signal which causes the control circuit STB to set the control fliv-flon FF. Now the second control circuit STA can again commence the information transmission into the buffer store PS. However, again the write-in process can never overtake the read-out process because of the setting of the control flip-flop FF. Thus items of information can be written into the buffer store PS and items of information can be read out therefrom simultaneously, and it is ensured that the ,write-in process cannot overtake the readout process and the read-out process cannot overtake the write-in process. The buf fer store PS can firstly be entirely filled with the information supplied via one interface before information is transmitted via the other inface. WHAT WE CLAIM IS:-

1. A buffer store arrangement for intermediate storage of items of information transmitted between two function units, comprising a buffer store, a first control circuit which serves to control information traffic between the buffer store and the first function unit, a second control circuit which serves to control information traffic between the second function unit and the buffer store, the first and second control circuits being such that information can be transmitted from one function unit to the buffer store and from the buffer store to the other function unit simultaneously, addressing means for producing addresses of storage positions of the buffer store into which write-in is to be effected and addresses of storage positions of the buffer store from which read-out is to be effected, a comparator arranged to compare the addresses for write-in to the buffer store with the addresses for read-out from the buffer store and to provide an output whenever the addresses are such as would result in an attempt to access any storage position for both reading and writing simultaneously, a bistable stage, and a logic element having an input connected to an output of the comparator, wherein the bistable stage has a control input connected to an output of the first control circuit to be controlled thereby and an output connected to an input of the second control circuit andto another input of the logic element, thè arrangement being such that the -blstablé stage is set' 'to a first state by the first control circuit whenever transmission of a predetermined amount of information ,,'i5 possible, between the buffer store and the second function unit in the selected transmission direction and is reset to a second state when a first item of information has been transmitted between the second function unit and the buffer store in the selected direction, and the logic element supplies a blocking signal to the first control circuit when both the bistable stage is in the first state and the comparator provides said output.

2. An arrangement as claimed in Claim

1 wherein said predetermined amount is an information block consisting of a plurality of information words.

3. An arrangement as claimed in Claim 1 or 2 wherein, in the event that the bistable stage is in the first state when said predetermined amount of information can be transmitted, the first control circuit delays the setting of the bistable stage to the first state until the bistable stage has been reset to the second state.

4. An arrangement as claimed in Claim 1, 2 or 3 wherein the addressing means comprises a first counter for the production of the addresses of the storage positions of the buffer store which serve for the transmission of information between the first function unit and the buffer store and a second counter for the production of the addresses of the storage positions of the buffer store which serve for the transmission of information between the buffer store and the second function unit, wherein the first and second control circuits are arranged to supply counter pulses respectively to the first and second counters and the comparator is arranged to compare the counts of the counters with one another, and wherein there is provided a further circuit which is connected to the first counter and which is arranged to emit a signal to the first control circuit when said predetermined amount of information is available in the buffer store in response to which signal the first control circuit effects said setting of the bistable stage to the first state.

5. An arrangement as claimed in Claim 4 wherein, for the transmission of the items of information in words between the second function unit and the buffer store and in half-words between the first function unit and the buffer store, the first counter has one more address output than has the first counter and all the outputs, except the lowest order output, of the first counter are connected to the comparator.

6. An arrangement as claimed in Claim 2 or any one of Claims 3 to 5 when dependent on claim 2, wherein the control circuits are such that when information is transmitted from the first function unit to the second function unit via the buffer store, information is transferred into the buffer store until an information block is contained in the buffer store, then the bistable stage is set to the first state by the first control circuit, and the second control circuit is thereby enabled for transmission of the information block from the buffer store into the second function unit.

7. An arrangement as claimed in Claim 2 or any one of Claims 3 to 6 when dependent on Claim 2, wherein the control circuits are such that when information is transmitted from the second function unit to the first function unit via the buffer store, the first control circuit sets the bistable stage to the first state as frequently as corresponds to the number of information blocks in the buffer store, the bistable stage is reset to the second state by the second control circuit each time a first information word of an information block is transmitted, and is set to the first state by the first control circuit each time an information block limit is exceeded during the transmission of information from the buffer store to the first function unit.

8. A buffer store control arrangement substantially as herein described with reference to Figure 2 of the accompanying drawings.

9. A data processing system comprising two function units and a buffer store arrangement as claimed in any one of Claims 1 to 8, the buffer store being arranged for the ?ntermediate storage of items of information transmitted between the two function units.

10. A system as claimed in Claim 9 and substantially as herein described with reference to Figure 1 of the accompanying drawings.