GB1572637A - Analogue-to-digital converter - Google Patents

Description

(54) ANALOG-TO-DIGITAL CONVERTER (71) We. MOTOROLA, INC.. a corporation organised and existing under the laws of the State of Delaware. United States of America, of 1303 East Algonquin Road, Schaumburg, Illinois 60196, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to an analog-to-digital converter and. in particular, to a serial-parallel analog-to-digital converter with overlapping operations.

An analog-to-digital (A/D) converter encodes a voltage or current signal into a digital representation with respect to a known reference. Its accuracy is determined by the number of significant digits of the digital representation (typically the number of bits in a binary representation). The bandwidth of an A/D converter is determined by its conversion speed - the amount of time required to convert an applied input quantity to an equivalent digital representation. A widely applied class of A/D converters function by comparing an applied analog input signal to a known reference to produce a discrete or quantized signal and then encoding the quantized signal to produce a digital representation of the analog input. The particular A/D converters within this class range from what are called "serial" A/D converters in contrast to what are called "parallel" A/D converters.Serial A/D converters encode the applied analog input signal one bit at a time starting with the most significant bit and progressing sequentially towards the least significant bit. This is accomplished by coupling the analog input signal to the input of a single comparator and using control logic to coupled different reference values to another input of the comparator for the conversion of each successive bit of the output representation. Thus serial A/D converters are characterized by the advantages of relatively simple circuit configurations and low power consumption and by the disadvantage of slow conversion speeds. Parallel A/D converters, on the other hand, use a plurality of comparators each with its own distinct input reference value to allow all bits of the digital output representation to be produced simultaneously.

Although the approach offers the advantage of minimum conversion time, this high speed operation is obtained only with greatlv increased circuit complexity and component count.

Thus, for binary output representation. N output bits would require 2N separate comparators. Manv potential applications for high speed AID converters require digital output representation of 8-bits. In applications where an A/D converter interfaces with a bus-oriented microprocessor system an 8-bit output (which can then correspond to a computer data byte) is particularly useful. Similarly. the encoding of samples representative of a 6 megahertz color video signal requires a converter of at least 8-bits and conversion times of 15 nanoseconds or less. The implementation of an A/D converter having an 8-bit output using the parallel approach would require 256 separate comparator circuits.An A/D converter of this complexity and high component count is impractical from a cost point of view and. in particular. precludes implementation in monolithic integrated circuit form.

Another approach to AID conversion is the serial-parallel A/D converter which is a merger of the two conversion techniques previously discussed. In converters of this type, the digital output representation is partitioned into a most significant bit (MSB) group and a least significant bit (LSB) group. Parallel conversion is used to obtain the digital output representations of both the MSB group and the LSB group but these conversions are performed in a serial fashion with the initial representation of the MSB group determining the reference voltage value required for the parallel conversion of the LSB group.

Serial-parallel AID converters yield faster conversion speeds than the all serial A/D converters with a circuit configuration which is simpler and has lower power consumption than the all parallel A/D converter.

Prior art serial-parallel A/D converters perform a conversion in the following sequence: 1. Parallel A/D conversion is used to obtain a digital representation of the MSB group; 2. Digital to analog conversion is used to convert the MSB representation back to an analog signal: 3. The analog representation of the MSB group is either subtracted from the input analog signal or is used to generate a change in voltage reference such that an analog difference signal is produced; and 4. Parallel A/D conversion is used to convert the analog difference signal to obtain a digital representation of the LSB group.

Although the serial-parallel A/D converter represents a compromise which provides conversion speeds which are faster than exlusively serial A/D converters and I reduction in circuit complexity and component count from exclusively parallel A/l) converters. the circuit delay times required in past converters of this type have made them too slow for very high speed applications such as color video encoding or interfacing with a high-speed microprocessor. Thus it has remained a problem to obtain an effective design for an A/l) converter which is simple enough in circuit complexity and component count to be implemented as a monolithic integrated circuit but which is also capable of high-speed operation.

Accordingly, it is an object of this invention to provide an improved scrial-parallel All) converter which obtains improved conversion speeds through the use of overlapping operations.

It is a further object of this invention to provide an improved serial-parallel AID converter which is amenable to implementation of the monolithic integrated circuit.

According to the present invention there is provided an analog-to-digital conversion device comprising a reference potential. first comparator means for comparing an analog signal with a reference for producing an intermediate signal and a first conversion signal.

subtraction means for subtracting said analog signal from said intermediate signal to produce a residual signal. means for substantially concurrently digitally encoding the first conversion signal and for comparing said residual signal to a second reference to produce a second conversion signal. and means for digitally encoding said second conversion signal.

The invention will now be described by way of example only with particular reference to the accompanying drawings wherein: Figllze I is a block diagram of an analog-to-digital converter according to the invention.

Figllre 2 is a schematic circuit diagram of a comparator which can be used to provide both comparators shown in the embodiment of Figure 1.

flgiire 3 is a circuit schematic diagram of an encoder which can be utilized to provide both encoders shown in Figure 1.

Figllre 4 is a circuit diagram of the voltage subtractor shown in Figure 1.

flgitre S is a logic diagram of output latches which can be utilized in the embodiment of Figure 1.

Figlxre 6 is a circuit diagram of the compare-latch command generator of Figure 1.

Figure 7 is logic diagram of the read-latch command generator of Figure 1.

Figure 8 is a circuit diagram of part of the subtractor circuitry of Figure 4 and is useful in describing the operation of the subtractor circuit of Figure 4.

Figure 9 is a circuit diagram of alternative circuitry which can be utilized in the subtractor of Figure 4.

Frrre 10 is a timing diagram which is useful in describing the operation of the invention.

Figure 1 shows a serial-parallel A/D convertor 10 according to the present invention.

Figure 1 is a functional block diagram and, as such. a single line interconnecting functional block may represent a single conductor or a multiplicity of conductors as will be made clear bv the subsequent detailed description. Power supply and reference voltage connections are also omitted from Figure 1 in the interest of simplicity.

In Figure 1, an analog input couples to a first comparator 12 and a voltage subtractor 14 via conductor 16. The output of comparator 12 couples to ROM encoder 18 and to voltage subtractor 14 via line s(), which represents a multiplicity of conductors. Reference voltage levels generated within comparator 12 are coupled to voltage subtractor 14 via line 22 which also represents a multiplicity of conductors. ROM encoder 18 couples to output latch 24 via conductors 26. 28, 30 and 32. Output latch 24 produces a digital output representation on conductors 34. 36, 38 and 4() which form the most significant bit group output of the first parallel AID converter means 42 formed by comparator 12, ROM encoder 18 and output latch 24. A second parallel analog-to-digital converter means 44 is formed by comparator 46, ROM encoder X and output latch 5(1. Conductor 52 couples the analog difference output signal of voltage subtractor 14 to an input of comparator 46.Line 54, which represents a multiplicity of conductors, couples the output of comparator 46 to the input of ROM encoder 48. Conductors 56. 58, 60, and 62 couple the outputs of ROM encoder 48 to the inputs of output latch 50. The outputs of output latch 50 are coupled to conductors 64, 66, 68 and 70 to form the least significant bit group output of analog-to-digital converter circuit 10. Conductor 72 couples a clock input to a compare-latch command generator 74 and line 76. which represents a multiplicity of conductors, couples the output of compare-latch command generator 74 to the input of first comparator 12, the input of second comparator 46 and the input of read-latch command generator 78. Line 80, which represents a multiplicitv of conductors couples the output of read-latch command generator 78 to the inputs of output latch 24 and output latch 50.

The mode of operation of analog-to-digital converter circuit 10 is particularly adapted for high-speed operation. As the subsequent detailed descriptions will illustrate, the circuit configuration of each function block is adapted for high speed. In addition, and more significantly. the particular arrangement of functional elements as illustrated in Figure 1 provides unique advantages for achieving high-speed operation. These advantages derive from the fact that the particular structures and interconnections used in Figure 1 allows a time overlap or coincidence of the parallel conversion of the least significant bit group output and the most significant bit group digital output.

Figure 2 shows one particular embodiment of a high-speed comparator circuit which can be used as comparators 12 and 46 in the A/D converter circuit of Figure 1. The basic function of the comparator circuit of Figure 2 is to compare the kind of applied analog input voltage to a series of voltage reference values to produce a digital output. For the particular embodiment of Figure 2, this is accomplished using fifteen comparator circuits, Each of the comparator circuits contains identical circuitry and, for simplicity in the drawing, Figure 2 shows the detailed circuit structure and interconnections of only four of these comparator circuits which are, accordingly. representative of the others.Thus, as shown, the applied analog input signal couples via conductor 1()2 to a first comparator stage 104. a second comparator stage 1()6 and additional I 1 comparator stages which are part of block 108 but not shown specifically. a fourteenth comparator stage 110 and a fifteenth comparator stage 11'. The reference voltige values for each comparator stage are generated by a series connected resistive ladder. 'this ladder is formed by a first terminal 114 which couples to resistor 115 which couples to terminal 116 which in turn couples to resistor 117 which couples to terminal 118. etc.This series interconnection continues for eleven additional resistors which are included in block 108 but not shown and then continues with a connection to resistor 119 which couples to terminal 120 which in turn couples to resistor 121 which couples to node 122 which couples to resistor 123 which couples to terminal 124.

Thus. the connection of a minimum reference voltage value to terminal 114 and a maximum voltage reference value to terminal 1'4 produces a series of reference voltage values between the minimum and the maximum at each of the recited nodes. The operation of the comparator circuit will now be explained in terms of the operation of individual comparator stage 106. Comparator stage 106 comprises a constant current source transistor 125, a pair of common emitter input transistors 126 and 127, a pair of regenerative latching transistors 128 and 129 and a pair of compare-latch mode selection transistors 130 and 131.The emitter of current source transistor 125 couples to resistor 132 which in turn couples to a power supply conductor 133 which couples to the V- power supply. The base of constant current source transistor 125 connects to conductor 134 which couples in common to the bases of each of the constant current source transistors in each of the other comparator stages.

Conductor 134 also couples to the base and the collector of transistor 135. which establishes the required operating reference current level for each of the constant current source transistors connected to conductor 134. The emitter of current emitter transistor 135 connects to resistor 136 which couples to the V- power supply conductor 133. The collector of transistor 135 couples to resistor 137 which couples to a power supply conductor which is ground for the embodiment of Figure 2. The collector of constant current source transistor 1'5 couples to conductor 138 which in turn couples to the emitters of compare-latch mode selection transistors 130 and 131.The base of transistor 130 couples to conductor 139 which is the compare mode clock conductor which couples in the same manner to each of the converter stages. The base of transistor 131 couples to conductor 140 which is the latch mode clock conductor which couples to each of the individual comparator stages. The collector of transistor 130 couples to conductor 141 which in turn couples to the emitters of input transistors 1'6 and 1'7. The collector of transistor 131 couples to conductor 142 which in turn couples to the emitters of regenerative latching transistors 128 and 129. The collector of input transistor 1'6 couples to conductor 143 which couples to the collector of reeenerative latching transistor 128. the base of regenerative latching transistor 129 and load resistor 144. The collector of input transistor 127 couples to conductor 145 which couples to the collector of regenerative latching transistor 129, the base of regenerative latching transistor 128 and to a first terminal of load resistor 146. A second terminal of load resistor 146 couples to a first emitter of output transistor 147. A second emitter of output transistor 147 couples to load resistor 148 which is part of comparator stage 104. The second terminal of load resistor 144 couples to a first emitter of output transistor 149. A second emitter of output transistor 149 couples to the load resistor of a similar comparator stage (not shown) within block 108.The base of output transistor 147 and the base of output transistor 149 are each coupled to an output reference voltage conductor 150 which also couples to the bases of similar output transistors for each of the individual comparator stages. This output reference voltage is generated by circuit 151 in which the emitter of transistor 152 is coupled via resistor 153 to ground and the base of transistor 152 couples to the collector of transistor 152 and to V+ power supply conductor 154 via resistor 155. The collector of transistor 152 couples to the base of transistor 156 whose collector couples to the V+ power supply conductor 154 and whose emitter couples to conductor 150 and to resistor 157 which in turn couples to ground.

Referring again to representative comparator stage 106, the collector of output transistor 147 couples to conductor 158 which is one of the multiplicity of conductors forming comparator output 2() previously mentioned in the discussion for Figure l. Conductor 158 also couples to a first terminal of an output resistor 159 whose second terminal couples to V+ power supply conductor 154. In a similar manner. the collector of output transistor 149 couples to conductor 16() which is another of the multiplicity of conductors forming the output of the comparator circuit. Conductor 16() also couples to a first terminal of resistor 161 whose second terminal couples to V+ power supply conductor 154.

Turning now to the operation of the comparator circuit of Figure 2. as typified bv the operation of representative comparator stage 106, it should first be noted that the comparator stage has two fundamental modes of operation. the compare mode and the latch mode. The compare mode is defined by a high level on the compare clock conductor 139 and a low level on the latch clock conductor 140. Conversely. the latch mode is defined bv a low level on conductor 139 and a high level on conductor 140. The clock timing waveforms of Figure 10 illustrate the relationship between these two clock signals.The compare-latch mode selecting transistor pair 130 and 131 determines whether comparator stage 106 is in the compare mode or the latch mode by supplying the current value defined by constant current transistor 125 to the emitters of either the "compare" emitter coupled transistors 126 and 127 or to the "latch" emitter-coupled transistor pair 128 and 129. Since the clock signals on conductors 139 and 190 are complements (see Figure 10) only the compare transistors or the latch transistors will be active at any one time. In the compare mode. the analog input voltage present on conductor 102 which couples to the base of transistor 127 is compared to the reference voltage value present on conductor 118 which couples to the base of transistor 126.The coupling between the emitters of transistors 126 and 127 form a differential amplifier. When the applied analog input voltage on conductor 102 is greater than the reference voltage value on conductor 118, the collector current of transistor 127 will be greater than the collector current of transistor 126 and as a result the voltage developed across resistor 146 will be larger than the voltage developed across resistor 144. Conversely, if the applied analog input voltage coupled to the base of transistor 127 is less than the reference voltage applied to the base of transistor 126. the voltage developed across resistor 144 will be greater than the voltage developed across resistor 146.Thus, in the compare mode the polarity of the differential voltage developed between the collector of transistor 126 and the collector of 127 indicates whether the applied analog input signal applied to comparator stage 106 is greater than or less than the reference voltage value applied to that same stage. A key feature in the speed of operation of each comparator stage and thus of the over-all comparator circuit is the use of latching transistors 128 and 1'9 when the compare-latch clock signals switch such that the level of the compare clock conductor 139 goes from high to low and the level of the latch clock conductor 140 goes from low to high (see Figure 10). Transistor 130 switches to the nonconducting state and, simultaneously, transistor 131 switches to the conducting state such that latch transistors 128 and 129 are enabled.The regenerative cross-coupling formed bv conductors 143 and 145 acts to re-enforce the polarity of any differential voltage established between the collectors of transistors 126 and 127 in the compare mode and thus store or "latch" the results of the comparison. Assume, for example, that the input voltage applied via conductor 1()2 is only slightlv greater than the reference voltage value on conductor 118 so that at the end of the compare interval the collector of transistor 126 is only a few millivolts more positive than the collector of transistor 127.As the circuit enters the latch mode interval and transistors 128 and 129 begin to conduct, the slightly more positive voltage on conductor 143 will cause greater conduction in transistor 129 and less conduction in transistor 128 with the result that conductor 143 will become even more positive with respect to conductor 145. This regenerative effect proceeds rapidly until transistor 129 is saturated and transistor 128 is cut off. The speed inherent in a differential amplifier configuration which makes use of current switching together with the "snap" action of a latch circuit which uses regeneration to capture the results of a fast comparison are combined to provide a particularly useful high-speed comparator configuration.

High speed and a simple circuit configuration are further provided by the comparator circuit through the use of multiple emitter output transistors such as transistor 147 and transistor 149 shown in Figure 2. Each of the individual comparator stages function in the manner previously described for representative stage 106 and in the latch interval, each stage will assume one of two possible states defined by the presence or absence of current in the load resistors such as representative resistors 144 and 146. If, during the compare interval. the applied analog input voltage on conductor 102 was greater than the reference voltage value on conductor 118 during the latch mode, resistor 146 will conduct essentially all of the current flowing through constant current source transistor 125 and resistor 144 will conduct essentially no current.Conversely, if the applied analog input voltage on conductor 102 is less than the reference voltage value on conductor 118, resistor 146 will conduct essentially no current. Now consider the case where the applied analog input voltage has a value which is greater than the reference voltage value on conductor 116 but less than the reference voltage value on conductor 118. During the latch interval this value of applied analog input voltage will result in essentially no current in resistor 146 and no current in resistor 148. This means that no current can flow in either emitter of transistor 147 so that there is no current in the collector of transistor 147 and resistor 159 pulls output conductor 158 to a high level.Since all comparator stages to the left of comparator stage 106 see reference voltage values which are greater than the applied analog input voltage on conductor 102 they will all be latched into a conducting state which is the same as that described for stage 106 and as a result the multiple emitter output transistors corresponding to the stages will each have at least one conducting emitter so that all of the output conductors of comparator output 2() except for conductor 158 will be held in the low state.

Thus, the multiple emitter output transistor structure shown in Figure 2 provides a simple and high-speed method for producing an output signal on a single one of a multiplicity of output conductors which indicates the value of an applied analog input voltage with respect to a series of reference voltage values.

The comparator circuit shown in Figure 2 also includes a bias generating- circuit 165 which is used for generating reference bias voltages used by the read-only memory encoder circuit (Figure 3) and the voltage subtracter circuit (Figure 4). Conductor 134 couples to the base of a constant current source transistor 166 whose emitter couples to the 'V- power supply conductor 133 via a current scanning resistor 167. The collector of constant current source transistor 166 couples to conductor 168 which in turn couples to the emitter of transistor 169. The base of transistor 169 couples to bias voltage conductor 150 and the collector of transistor 169 couples to resistors 170 and 171 and to output conductor 172 which is the reference bias voltage output.The required reference value on output 172 is obtained by making resistor 167 and transistor 166 identical to the constant current source networks of each comparator stage (as represented by transistor 125 and resistor 132).. Similarly, the values of resistors 170 and 171 are chosen to be equal to the value of output resistors 159, resistor 161. etc. Since transistor 169 will conduct the same current of an individual output transistor, the result of this choice is that resistors 170 and 171 each will concluct half of the current, so that the voltage level established on reference bias voltage output conductor 172 is halfway between the high and low levels appearing on the individual conductors of comparator output 20.

Figure 3 shows one particular embodiment of a read-only memory encoder circuit which can be used to implement the A/D converter of the present invention. Read-only memory encoder circuit 200 comprises a read-only memory input section 202. an output section 204 and a bias voltage generator 206. Read-only memory input section 202 consists of a plurality of multiple emitter transistors. The number of multiple emitter input transistors corresponds to the number of digital outputs produced by the comparator circuit of the AID converter. Thus. for the particular embodiment of Figure 3, read-only memory input section 202 comprises sixteen multiple emitter input transistors.Transistors 208, 209, 210 and 211 are representative of these transistors as shown in Figure 3. the collectors of all of the multiple emitter input transistors are coupled to a common V4- power supply conductor 212. Each of the conductors forming the plurality of digital outputs from the comparator circuit of Figure 2 couples to the base of one multiple emitter input transistor. Thus, a first comparator output couples to the base of multiple emitter transistor 208 via conductor 213, a second comparator output signal couples to the base of multiple emitter transistor 209 via conductor 214 and similar connections are made to the bases of each of the other multiple emitter input transistors such that a fifteenth comparator output signal is coupled to the base of transistor 210 via conductor 215 and a sixteenth comparator output signal couples to the base of multiple emitter transistor 211 via conductor 216. As previously discussed. the comparator circuit (Figure 2) produces a plurality of digital output signals each of which represents a particular level of applied analog input signal.The particular arrangement of connections to the multiple emitters of the input transistors provides an encoding function by which a unique digital code is obtained for each comparator output signal and. thus, for each particular level of applied input signal. This arrangement of emitter connections is accomplished by providing a plurality of common conductors such as conductors 217. 218, 219 and 220. For the particular embodiment of read-only memory encoder 200, a binary code is used.Thus, the comparator output signal on conductor 213. which indicates that the applied analog input signal is greater than a first reference voltage value, couples to the base of multiple emitter transistor 208, which has none of its emitters coupled to the common conductors 217. 218. 219 and 220 and thus defines a binary code 000(1. A comparator output signal on conductor 214. which indicates that the level of applied analog input voltage is greater than a second reference voltage value, couples to the base of multiple emitter transistor 209 which has a first emitter 221 coupled to common conductor 22(1 therebv defining the binary code 0001. Similar emitter connections are used for the other multiple emitter transistors shown in read-only memory input circuit 202.Thus. a comparator output signal on conductor 215 indicative of an applied analog input signal level greater than a fifteenth reference voltage value couples to the base of transistor 210 which has a first emitter 222 which is not connected, a second emitter 223 which is coupled to conductor 219. third emitter 224 coupled to common conductor 218 and a fourth emitter 225 coupled to common conductor 217 thereby defining a binary code 1110. Similarly, a comparator output on conductor 216 indicative of an applied analog input signal level greater than a sixteenth reference voltage level, couples to the base of multiple emitter transistor 211 whose four emitters couple respectively to common conductors 217, 218, 219, and 220 therebv defining a binary code 1111.A multiple emitter encoding arrangement such as shown in Figure 3 is advantageous because coded representations of the applied analog input level. other than the binary code shown, can be readily obtained by simply changing the emitter interconnection arrangement used. In a monolithic integrated circuit, device structures incorporating several emitter device regions within a common base region or other similar techniques commonly employed in integrated circuit read-only memories provide a simple way to obtain the multiple emitter structure shown and make it easy to change the interconnection pattern as required by a new code.

The coded representation provided by the signals on each of the conductors 217. 218. 219 and 220 are coupled respectively to output circuits 226. 227. 228 and 229 which provide the amplification and level conversion required by the output latch circuit (Figure 5 described below). Each of these output circuits operate using two constant current source transistors.

The reference current for these constant current source transistors is provided bv transistor 23(1 whose emitter couples to V- power supply conductor 231 via resistor 232 and whose base collector is coupled to conductor 233. Conductor 233 couples to the bases of the constant current source transistors of each output circuit and to a first terminal of resistor 234 whose second terminal couples to a power supply terminal (GND) which is ground for the particular embodiment of Figure 3. Conductor 233 also couples to the base of constant current source transistor 235 which is part of reference voltage generating circuit 206.

in reference to voltage generating circuit 206. the emitter of constant current source transistor 235 couples to the V- power supply conductor 231 via resistor 236. The collector of constant current source transistor 235 couples to conductor 237 which is the reference bias voltage conductor coupling to each of the output circuits. Conductor 237 also couples to the base of transistor 238 whose collector couples to the Ve power supply conductor and whose emitter couples to the emitter base of transistor 239. The collector of transistor 239 couples to the emitter of transistor 241 whose collector couples to the V+ power supply and whose base couples to the reference bias voltage transmitted from the comparator circuit (Figure 2) via conductor 172.As previously discussed, the reference bias voltage on conductor 172 defines a level midwav between the low and high levels of the comparator output and reference voltage generating circuit 206 translates this voltage to the bias voltage present on conductor 237 thereby providing a trip point for high-speed current switching within each of the output circuits. The structure and operation of each of the output circuits is identical and will be described in terms of the operation of output circuit 229.

The heart of output circuit 229 is the differential amplifier formed bv transistors 241A and 242. The emitters of transistors 241A and 242 are coupled by conductor 243 which also couples to the collector of first current source transistor 244. The base of first current source transistor 244 couples to current reference conductor 233 (previously described). The emitter of first current source transistor 244 couples to the V- power supply conductor 231 via current scanning resistor 245. Turning to the differential amplifier, the collector of transistor 241A couples to the V+ power supply conductor and to the collector of transistor 246.The base of transistor 246 couples to conductor 247 which also couples to the base of transistor 241A and to the collector of second current source transistor 248. The base of second current source transistor 248 couples to current source reference conductor 233. The emitter of second current source transistor 248 couples to the V- power supply via resistor 249. The collector of transistor 246 couples to the emitter and the base of transistor 25() whose collector forms the input of output circuit 229 and couples to common conductor 220.

The base of transistor 242 couples to bias voltage conductor 237. The collector of transistor 242 couples to conductor 251 which is the output of output circuit 229 and which also couples to the V+ power supply conductor via resistor 252.

The operation of memory encoder circuit 200 is understood by first looking at representive output circuit 229. When the voltage at the base of transistor 241A is less than the voltage at the base of transistor 242, the constant current value established by constant current source transistor 244 and resistor 245 will be conducted by transistor 242 and the resulting voltage drop across resistor 252 will establish a low level on output conductor 251.

As previously discussed. the operation of the comparator circuit results in a high level on one of the comparator output conductors, for example. conductor 214. The encoding function of the emitter connections of each of the multiple emitter transistors steers such a high level to the inputs of the appropriate output driver circuits. Thus, a high level on conductor 214 results in a high level at emitter 221 of multiple emitter transistor 209 which couples via conductor 220 to the input of output circuit 229.This high level is level shifted bv transistor 250 and transistor 246 to produce the appropriate change in voltage at the base of transistor 241 A. Transistor 246 and transistor 250 operate in an emitter base reverse breakdown mode and resistor 249 is chosen such that a small constant current is conducted bv constant current source transistor 248. This small current establishes a stable value of reverse breakdown voltage for transistor 246. As a result of the level shifted high level appearing at the base of transistor 241A. transistor 241A conducts the constant current value set bv transistor 244 and transistor 242 becomes nonconducting so that the output level on conductor 251 changes from a low to a high level.

Circuit structures shown in Figure 3 are particularly adapted to minimize the effects of temperature and process variations in the monolithic integrated circuit embodiment. The use of a current source. such as current source transistor 248 to establish a small stable current value to sustain the emitter base reverse breakdown voltage of the level shifter transistors tends to eliminate the effects of process variations. Also, the use of a common current source reference (conductor 233) for all output stages and in particular for the generation of the bias voltage on conductor 237 compensates for the effects of temperature and process variation. It also should be noted that transistor 250 can be eliminated in those applications where the additional level shifting it provides is not required.

The operation of each of the output circuits of read-only memory encoder 200 is the same as has been described for output circuit 229. Thus output circuit 228 responds to a high level on conductor 219 to produce a level shift at high level on output conductor 252. output circuit 227 responds to a high level on conductor 218 to produce a level shift at high level on output conductor 253 and output circuit 226 responds to a high level on conductor 217 to produce a level shifted high level on output conductor 254.

Figure 4 shows one particular embodiment of a reference voltage switching and analog voltage subtraction circuit 300 which can be used in the present invention.

As previously discussed. the kev to the high A/D conversion speeds obtained by the present invention is the time overlap or coincidence of the parallel conversion of the most significant bit group digital output and the least significant bit group digital output. This time overlap is obtained by using intermediate outputs obtained during the process of the most significant bit group conversion to determine the particular reference voltage value which must be subtracted from the applied analog input to obtain the analog difference signal required for the parallel conversion of the least signifcant bit group output. The reference voltage switching and subtraction of circuit 300 provides one way of accomplishing this requirement.

Circuit 300 comprises a basic subtractor module 302, a reference voltage generator 304 and a pluralitv of level shifting and reference voltage switching circuits. For the particular embodiment of Figure 4, sixteen level shifting and reference voltage switching circuits are shown bv representative circuits 306. 308. 310, and 312 with the remaining twelve circuits represented pictorally bv block 314. Each of these switching modules couples in common to conductor 315 which is the voltage reference input to subtractor module 302. The other inputs to subtractor module 302 are the analog voltage input VIN terminal 316 and the constant bias voltage input terminal (VC) 317. The output of subtractor module 302 is VO terminal 318. Subtractor module 302 functions to subtract a particular reference voltage appearing on conductor 315 from the analog input voltage appearing on terminal 316 to produce an analog difference signal output which includes the constant bias voltage VC as an additive constant. The detailed circuit operation which allows subtractor module 302 to perform this function is given below in the detailed description of Figure 8 and Figure 9.

The particular reference voltage value which is applied to subtractor module 302 via conductor 315 is determined by the functioning of the switching modules as discussed above. The action of the latching comparator of Figure 2 produces a high level on one of the plurality of comparator outputs. As shown in Figure 4, each of the switching modules has as an input one of the comparator outputs and a corresponding voltage reference value. Thus, for example the comparator output VC02 couples to switching module 308 via conductor 158 and corresponding voltage reference value Vr, couples to switching modules 308 via conductor 118. Similarly, comparator output VC15 and corresponding voltage reference value Vri.s are coupled to switching module 310. This pattern is repeated for each of the modules.

Reference voltage generator 304 provides a reference voltage which provides the trip point for current switching in all of the switching modules. This voltage is derived from the VCO0 voltage level which is applied to reference voltage 304 via conductor 172. As described above, VCO0 defines a reference voltage level midway between the low (inactive) and high (active) output levels of the comparator outputs. Conductor 172 couples to the base of transistor 319 whose collector couples to a V+ power supply conductor 320 and whose emitter couples to the emitter of diode connected transistor 321.The base and collector of transistor 321 are coupled to the collector of transistor 322 whose base and emitter are coupled to the collector of constant current source transistor 323 via conductor 324 which is the reference voltage output of reference voltage generator 304. The emitter of constant current source transistor 323 couples to V-- power supply conductor 325 via resistor 326. The base of constant current source transistor 323 couples to the base and collector of current reference transistor 327 via conductor 328 which is a first current source reference conductor for all of the switching modules. The emitter of current reference transistor 327 couples to V-- power supply conductor 325 via resistor 329.Current source reference 327 also couples to a first terminal of resistor 330 whose second terminal couples to ground power supply conductor 333.

Transistor 331 whose emitter couples to V-- power supply conductor 325 via resistor 332 and whose base couples to ground power supply conductor 333 via resistor 334, couples at its collector to a second current source reference conductor 335 which is common to all of the switching, modules.

The operation of the switching modules, each of which functions ;dent;cally. will now explained bv considering the circuit operation of switching module 308. In switching module 308 the VC02 comparator output on conductor 158 couples to the base of transistor 336 whose collector couples to V+ power supply conductor 320. The emitter of transistor 336 couples to the emitter of transistor 337 whose base and collector couple to the emitter of transistor 338. The base and collector of transistor 338 are coupled to the collector of current source transistor 339 via conductor 340. The current source reference 327 (common to all switching modules) couples to the base of current source transistor 339 whose emitter couples to V-- power supply conductor 325 via resistor 341.Transistors 336. 337, 338 and 339 function as a high-speed voltage level shifter for the VC02 comparator output on conductor 158 such that a voltage shifted replica of this output appears on conductor 340.

Conductor 340 couples to the base of transistor 342 whose emitter couples to the emitter of transistor 343 and to the collector of current source transistor 344 whose emitter couples to the V- - power supply conductor 325 via resistor 345. The base of transistor 343 couples to the voltage shifted comparator output reference voltage on conductor 324 which couples in common to all switching modules. Transistor 342 and 343 act as a differential current switch for the constant current value defined bv constant current source transistor 344.

When the voltage shifted comparator output level on conductor 340 is less than the voltage shifted reference voltage on conductor 324 (indicating that the VC02 comparator output is in the low or inactive state) the constant current defined by transistor 344 will be conducted by transistor 343 whose collector couples to conductor 346 which is the digital ground power supply conductor for all switching modules. In this state. the voltage reference value Vrr on conductor 118 is decoupled from common conductor 315 and has no effect on the operation of subtractor module 302.

When the voltage shifted comparator output level on conductor 340 is in the high state (corresponding to comparator output VC02 on conductor 158 in the higher active state), the constant current defined bv transistor 344 is conducted by transistor 342 whose collector couples to the commonlv coupled emitter of transistors 347 and 348. The base and collector of transistor 347 are coupled to conductor 349 which couples to the emitters of transistors 350 and 351. The collector of transistor 350 couples to the base of transistor 352 and to the emitter of transistor 353 whose collector couples to V+ power supply conductor 320 and whose base couples to conductor 118 which is the Vr, reference voltage input to switching module 308. The collector of transistor 352 couples to the cathode of diode 354 whose anode couples to common conductor 315.The base and collector of transistor 348 couples to conductor 355 which couples in common to all switching modules and to subtractor module 302.

Transistors 347. 348. 350, 351. 352 and 353 form a current splitting network such that when the VC02 comparator output on conductor 158 is in its active (high) state, the constant current value established by transistor 344 is conducted via transistor 342 and divided between transistors 347 and 348 with the effect that voltage reference value Vr. on conductor 118 is coupled to subtractor module 302 to form the required analog difference signal at the output of subtractor module 302. The manner in which this current switching is combined with the circuit operation of subtractor module 302 to obtain the required analog difference signal is explained in the detailed circuit description of the basic subtractor module (Figure 8 and Figure 9) given below.

Figure 8 shows subtractor module 3()2 together with portions of the current splitting and current switching circuits of Figure 4 arranged to facilitate cxplanation of the particular and unique subtraction circuit used in the present invention. As shown in Figure 8, the structure of the subtractor is a symmetrical arrangement of circuitry around an operational amplifier.

As previously discussed, reference voltage value V,1 is coupled via conductor 118 to the current splitting network formed by transistors 350, 351, 352 and 353 and diode 354. The anode of diode 354 couples via conductor 315 to the (+) input of operational amplifier 355.

In a symmetrical fashion the analog input voltage couples to a current splitting network formed by transistors 356. 357. 358 and 359 with the collector of transistor 359 coupling to conductor 360 which in turn couples to the negative (-) input of operational amplifier 355.

The output of operational amplifier 355 couples to conductor 318 which is the V" output of the subtractor. A first logarithimic impedance means 362 couples from conductor 360 to conductor 318 to form a feedback connection between the operational amplifier output and input. A second logarithimic impedance means 363 couples from the constant bias voltage conductor 317 (if ) to conductor 315. For the particular embodiment of Figure 8. first logarithmic impedance means 362 comprises the four diode connected transistors 364. 365.

366 and 367 coupled in series and in similar fashion, second logarithmic impedance means 363 comprises the four diode coupled transistors 368, 369. 370 and 371 again coupled in series. As shown in Figure 8 the output of second current splitting circuit 350' couples to conductor 349 which couples to the base and collector of transistor 347. The current in conductor 349 is designated I.. Similarly. the output of first current splitting circuit 356' couples to conductor 372 which couples to the base and collector of transistor 348. The current flowing in conductor 372 is designated II. The emitters of transistors 347 and 348 are coupled in common and coupled to current source 373 which in turn couples to V-- power supply conductor 3'5.It should be noted that current source 373 is an abbreviated symbolic representation of the current source and current switching circuitry previously described in Figure 4 which is shown in Figure 8 in abbreviated form to simplify the description of operation. Also. for further convenience in this discussion of operation. the current flowing in current source 373 is designated as Ic. The operational amplifier input voltage on conductor 360 is designated V, and the operational amplifier input voltage on conductor 315 is designated V2.

Turning now to the basic operation of the subtractor circuit shown in Figure 8, consider first the differential amplifier formed by transistor 356-348 and transistor 353-347. The collector current of transistor 359 and the emitter current of transistor 356 are both equal to IiI2 because of the current mirror formed by transistors 356 and 358. While the collector current of transistor 352 and the emitter current of transistor 353 are similarly 1212. The sum of the currents Ii and I. must equal the source current Ic. It can be shown that when all devices are in their linear region.

Since operational amplifier 355 draws a negligible input current the current through logarithmic impedance means 363 must be 142 and thus

where Is is the base-emitter reverse saturation current and Vc is the constant bias voltage on conductor 317.

Similarly, summing voltages around the loop containing impedance means 362 gives

For a high gain operational amplifier in a unity gain configuration, the inputs V, and V2 are virtually identical so that

But this last term. from equation (1). gives V" = V. + (VIN - Vr2) (5) The subtractor output V} is thus the input voltage minus the next smaller reference voltage value offset by a constant bias voltage.

Examination of the above equations relating to the operation of the basic subtractor circuit of the present invention shows that the required analog difference signal output is obtained because the ratio of the currents flowing in the logarithmic impedance means 362 and 363 (I/2 divided by I2/2) is the same as the ratio of the currents flowing in transistors 348 and 347 (I divided by 12). Thus, the function of the current splitting networks 356' and 350' is to prevent any current conducted by the VIN conductor 316 or the Vr. conductor 118 from distorting inputs of operational amplifier 355. Thus. it is clear that other circuit arrangements which preserve the equality of the current ratio can also be used.

Figure 9 shows a subtractor circuit 400 which is one such embodiment. In Figure 9 the current splitting currents used in Figure 8 have been replaced by simple emitter follower structures. Thus the VIN input couples to the base of a transistor 402 whose collector couples to one input of an operational amplifier 404 and the Vr input couples to the base of transistor 406 whose collector couples to the other input of operational amplifier 404. The emitter of transistor 4ü2 couples via diode connected transistors 408 and 410 to the collector and base of transistor 412 which is analogous to transistor 348 (Figure 8). Similarly the emitter of transistor 406 couples via diode connected transistors 414 and 416 to the collector and the base of transistor 418 which is analogous to transistor 347 (Figure 8).Because the current ratio is maintained, the equations listed above for Figure 8 apply to the operation of this circuit. This circuit requires that the current gain of transistors 402 and 406 be high enough to ensure that the base current conducted via the VIN and Vr inputs is negligible with respect to currents I, and I.

Figure 6 shows a compare-latch command generator circuit 500 which can be used to implement the present invention. This circuit uses high-speed current switching to provide the high frequencv compare and latch mode clock signals required by the comparator to accomplish the high-speed A/D conversion objectives of the present invention. As shown in the Figure. a clock input is level shifted by a zener diode 501 and coupled to a first differential amplifier formed bv transistors 502 and 503. The collector of transistor 503 couples to Q 1 output conductor 504 which is the compare mode clock for the most significant bit (MSB) comparator.Similarly. the collector of transistor 502 couples to the Q' output conductor 505 which is the latch mode clock for the most significant bit (MSB) comparator. The level shifted clock input also couples via conductor 506 to resistor 507 and capacitor 5U8. Resistor 507 and capacitor 508 form a delav line which delay the applied clock input prior to its being coupled to the differential amplifier formed by transistors 509 and 511). The collector of transistor 510 couples to Q2 clock conductor 511 which is the compare mode clock for the least significant bit comparator.Similarly. the collector of transistor 5()9 couples to the Q' clock conductor 512 which is the latch mode clock for the least significant bit comparator. It should also be noted in Figure 6 that the collector load resistors of transistors 50' and 503 couple to ground power supply conductor 513 via transistor 514 while the collector load resistors of transistor 509 and 510 couple to V+ power supply conductor 515 via transistor 516. These differences in collector supply voltage provide compare mode and latch mode clock signals appropriate for each comparator. The time relationship of the compare mode and latch mode outputs of compare-latch command generator circuit 5()() are shown in the timing diagram of Figure 10.

As previously discussed. the AID converter of the present invention achieves high speed operation by overlapping the parallel conversion used to produce the most significant bit group digital outpt and the least significant bit group digital output. Figure 10 shows the timing relationship of this overlapping.Figure 11) shows three successive conversion periods designated T,* T2 and T. Each of these conversion intervals is subdivided into four smaller intervals designated t,. t2. t and t. Under the control of the Ill clock, the applied analog input signal is compared by the MSB comparator during the tl interval of each conversion period and the results of this comparison are latched in the comparator during the subsequent time period defined by t2, t, and t4.Similarly under control of the 2 clock, the analog difference signal generated by the voltage subtractor is compared by the MSB comparator during time interval t of each conversion period and the results of the comparison latched in the comparator for the next three time intervals. Thus as shown in Figure 10. both the MSB and LSB comparisons are complete at the end of the t3 time interval and after the encoding of the MSB and LSB ROM encoders. the complete digital representation of the applied analog input quantity will be available. In order that all bits oí the digital representation appear simultaneously, the A/D converter circuit of the present invention includes an output latch circuit 60() and an output read/latch command generator circuit 700.

Referring to Figure 5. output latch circuit 600 comprises four identical latch circuits 6()l, 602. 603 and 6()4. The structure and operation of each latch circuit will be explained in terms of representative circuit 601 which comprises NAND gates 605. 6() and 6()7. NANI) gates 6()6 and 6()7 are cross coupled to form a latch. Conductor 6()8 couples the (1R clock signal generated by output read-latch command generator circuit 7()() to in input of NAND gate 6()7. This signal forces the latch formed by NAND gate 6()6 and 6()7 to the~"reset" state during the time interval 4 shown in Figure 10.Conductor 6()9 couples the (1R clock signal generated by output read-latch command generator circuit 700 to an input of NAND gate 605. Conductor 6(19 is high during the time interval t4 shown in Figure l() and thus enables NAND gate 605 during that time such that the digital data coupled to o second input of NAND gate 605 via conductor 61()iS inverted and applied to the "set" input of the latch formed by NAND gates ()()6 and 607.At the end of time interval t4, the (1R clock signal on conductor 608 returns to a high level such that the latch circuit formed by NAND gates 606 and 607 is no longer held in the reset state and will. accordingly. latch into the state defined bv the logic level at the output of NAND gate 605 therebv producing the required digital output on conductor 611 which couples to the output of NAND gate 6()6.In a similar fashion the ROM encoder output applied to latch circuit 602 via conductor 612 is latched to produce a digital output on conductor 613. the ROM encoder output applied to latch circuit 603 via conductor 614 is latched to produce a digital output on conductor 615 and the ROM encoder output applied to latch circuit 604 via conductor 616 is latched to produce a digital output on conductor 617.

Figure 7 shows output read-latch command generator circuit 700 which comprises cross coupled NOR gates 701 and 702, NAND gate 703 and inverter 704. The inputs to circuit 700 are clock signals from the compare-latch command generator circuit 500 shown in Figure 6.

Compare mode clock (11 couples via conductor 504 to an input of NOR gate 701 and compare mode clock (12 couples to an input of NOR gate 702 via conductor 511. These signals alternately set and reset the latch formed by NOR gates 701 and 702 to produce a signal at the output of NOR gate 701 which is low during time interval t and t2 and high during time interval t and t4 (see Figure 10). This output of NOR gate 7()1 couples to an input of NAND gate 703 via conductor 705. Latch mode clock (12 (Figure 6) couples to a second input of NAND gate 703 via conductor 512.As shown in Figure 10, latch mode clock (12 is low during time interval t, and high during time intervals t1, t2 and t4. Thus the coincidence of high levels at the input of NAND gate 703 produces the output read-latch command BR at the output of NAND gate 703 which couples to conductor 608. This signal is coupled to the input of inverter 704 whose output couples to conductor 609 which is the inverted output read-latch command R.

WHAT WE CLAIM IS: 1. An analog-to-digital conversion device comprising a reference potential. first comparator means for comparing an analog signal with a reference for producing an intermediate signal and a first conversion signal. subtraction means for subtracting said analog signal from said intermediate signal to produce a residual signal. means for substantially concurrently digitally encoding the first conversion signal and for comparing said residual signal to a second reference to produce a second conversion signal and means for digitally encoding said second conversion signal.

2. An analog to digital converter comprising: an analog signal source: first comparator means coupled to said analog signal source for comparing said analog signal to a first reference voltage and producing a first output signal representative of whether said analog signal exceeds or is less than said first reference voltage; said first comparator means including a first reference voltage source for producing said first reference voltage: first encoder means responsive to said first output signal for producing a first digital number representative of whether said analog signal exceeds or is less than said first reference voltage:

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (9)

**WARNING** start of CLMS field may overlap end of DESC **. period and the results of this comparison are latched in the comparator during the subsequent time period defined by t2, t, and t4. Similarly under control of the 2 clock, the analog difference signal generated by the voltage subtractor is compared by the MSB comparator during time interval t of each conversion period and the results of the comparison latched in the comparator for the next three time intervals. Thus as shown in Figure 10. both the MSB and LSB comparisons are complete at the end of the t3 time interval and after the encoding of the MSB and LSB ROM encoders. the complete digital representation of the applied analog input quantity will be available.In order that all bits oí the digital representation appear simultaneously, the A/D converter circuit of the present invention includes an output latch circuit 60() and an output read/latch command generator circuit 700. Referring to Figure 5. output latch circuit 600 comprises four identical latch circuits 6()l, 602. 603 and 6()4. The structure and operation of each latch circuit will be explained in terms of representative circuit 601 which comprises NAND gates 605. 6() and 6()7. NANI) gates 6()6 and 6()7 are cross coupled to form a latch. Conductor 6()8 couples the (1R clock signal generated by output read-latch command generator circuit 7()() to in input of NAND gate 6()7. This signal forces the latch formed by NAND gate 6()6 and 6()7 to the~"reset" state during the time interval 4 shown in Figure 10.Conductor 6()9 couples the (1R clock signal generated by output read-latch command generator circuit 700 to an input of NAND gate 605. Conductor 6(19 is high during the time interval t4 shown in Figure l() and thus enables NAND gate 605 during that time such that the digital data coupled to o second input of NAND gate 605 via conductor 61()iS inverted and applied to the "set" input of the latch formed by NAND gates ()()6 and 607.At the end of time interval t4, the (1R clock signal on conductor 608 returns to a high level such that the latch circuit formed by NAND gates 606 and 607 is no longer held in the reset state and will. accordingly. latch into the state defined bv the logic level at the output of NAND gate 605 therebv producing the required digital output on conductor 611 which couples to the output of NAND gate 6()6.In a similar fashion the ROM encoder output applied to latch circuit 602 via conductor 612 is latched to produce a digital output on conductor 613. the ROM encoder output applied to latch circuit 603 via conductor 614 is latched to produce a digital output on conductor 615 and the ROM encoder output applied to latch circuit 604 via conductor 616 is latched to produce a digital output on conductor 617. Figure 7 shows output read-latch command generator circuit 700 which comprises cross coupled NOR gates 701 and 702, NAND gate 703 and inverter 704. The inputs to circuit 700 are clock signals from the compare-latch command generator circuit 500 shown in Figure 6. Compare mode clock (11 couples via conductor 504 to an input of NOR gate 701 and compare mode clock (12 couples to an input of NOR gate 702 via conductor 511. These signals alternately set and reset the latch formed by NOR gates 701 and 702 to produce a signal at the output of NOR gate 701 which is low during time interval t and t2 and high during time interval t and t4 (see Figure 10). This output of NOR gate 7()1 couples to an input of NAND gate 703 via conductor 705. Latch mode clock (12 (Figure 6) couples to a second input of NAND gate 703 via conductor 512.As shown in Figure 10, latch mode clock (12 is low during time interval t, and high during time intervals t1, t2 and t4. Thus the coincidence of high levels at the input of NAND gate 703 produces the output read-latch command BR at the output of NAND gate 703 which couples to conductor 608. This signal is coupled to the input of inverter 704 whose output couples to conductor 609 which is the inverted output read-latch command R. WHAT WE CLAIM IS:

1. An analog-to-digital conversion device comprising a reference potential. first comparator means for comparing an analog signal with a reference for producing an intermediate signal and a first conversion signal. subtraction means for subtracting said analog signal from said intermediate signal to produce a residual signal. means for substantially concurrently digitally encoding the first conversion signal and for comparing said residual signal to a second reference to produce a second conversion signal and means for digitally encoding said second conversion signal.

2. An analog to digital converter comprising: an analog signal source: first comparator means coupled to said analog signal source for comparing said analog signal to a first reference voltage and producing a first output signal representative of whether said analog signal exceeds or is less than said first reference voltage; said first comparator means including a first reference voltage source for producing said first reference voltage: first encoder means responsive to said first output signal for producing a first digital number representative of whether said analog signal exceeds or is less than said first reference voltage:

subtractor means responsive to said analog signal. said first reference voltage. and said first output signal for producing a second output signal representative of the difference between said first reference voltage and said analog signal; second comparator means responsive to said second output signal for comparing said second output signal to a second reference voltage and producing a third output signal representative of whether said second output signal exceeds or is less than said second reference voltage; said second comparator means including a second reference voltage source for producing said second reference voltage: second encoder means responsive to said third output signal for producing a second digital number representative of whether said second output signal exceeds or is less than said first reference voltage.

3. The analog-to-digital converter as claimedin claim 2 wherein said subtractor means comprises: amplifier means responsive to said analog input signal and to said first reference voltage for producing said second output voltage so that it is proportional to the difference between said analog input signal and said first reference voltage: first means responsive to said first output signal for controllably electrically coupling said first reference voltage to a first input of said amplifier means; second means responsive to said analog input signal for electrically coupling said analog input signal to a second input of said amplifier means.

A. The analog-to-digital converter as claimed in claim 3 wherein said amplifier means includes: first feedback means coupled between the output of said amplifier means and said second input of said amplifier means for effecting said producing of said proportionalitv of said second output voltage: second feedback means coupled between a constant reference voltage and first reference voltage source for effecting said producing of said proportionality of said second output voltage.

5. The analog-to-digital converter is claimed in claim 2 wherein said first reference voltage is one of a plurality of reference voltages generated by said first reference voltage source. and said second reference voltage is one of a plurality of reference voltages generated bv said second reference voltage source.

6. The analog-to-digital converter as claimed in claim 2 wherein said first and second digital members are binary numbers.

7. The analoe-to-digital converter as claimed in claim 2 wherein sais first and second digital numbers are not binary numbers.

k. The analog-to-digital converter as claimed in claim 2 wherein said first output signal is produced on one of a pluralitv of outputs of said first comparator means and said third output signal is produced on one of a pluralitv of outputs of said second comparator means.

9. The analog-to-digital converter as claimed in claim 6 wherein said first comparator means includes a differential comparison circuit comprising: a constant current source: a first transistor having its emitter coupled to said constant current source and its base coupled to a first clock signal: a second transistor having its emitter coupled to said constant current source and its base coupled to a second clock signal. said first and second clock signals being complementarv: a pair of emitter coupled input transistors having their emitters coupled to the collector of said first transistor and their bases coupled respectively. to said analog input signal and said first reference voltage: : a pair of cross-coupled emitter coupled transistors having their emitters coupled to the collector of said second transistor and having their collectors coupled respectively. to the collectors of said input transistors.

1(). An analog-to-digital converter substantially as hereinbefore described and as shown in the accompanying drawings.