GB1569867A - Data processing systems - Google Patents

Description

(54) IMPROVEMENTS IN OR RELATING TO DATA PROCESSING SYSTEMS (71) We, STANDARD TELEPHONES AND CABLES LIMITED, a British Company, of 190 Strand, London, W.C.2., England, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to an electrical data processing system which uses a processor in assocation with a shift register.

In our application No. 23067/74 (Serial No. 1448041), to which this application is an application for a Patent of Addition, there are described and claimed processors, each of which is a relatively simple one-bit digital computer with an internal random access memory (RAM) in which, inter alia, intermediate processing results may be stored. This invention seeks to extend the usefulness of processors of the type described in the above mentioned application.

According to the invention there is provided an electrical data processing system which includes a processor as claimed in claim 1 of our Patent No. 1448041, a clock pulse source, an external program memory which contains a program of instructions for the control of the data processing operations, the instructions being supplied to the processor singly and successively under the control of clock pulses from a clock pulse source, a shift register having its serial input connected to an output from the processor, connections whereby the clock pulse source supplies clock pulses to the processor and the shift register as well as to the program memory, and connections within the processor such that data transfers between individual address locations of the internal memory of the processor and the shift register are effected under the control of certain instructions of the program.

Embodiments of the invention will now be described with reference to the drawings accompanying the Provisional Specification in which Figure 1 is an embodiment of the invention in which the shift register provides an input multiplexing function.

Figure 2 is an embodiment of the invention in which the shift register provides an output multiplexing function.

Figure 3 shows the use of a shift register to provide both an input and an output multiplexing function.

Figure 4 shows the use of a shift register for the augmentation of the processor's RAM.

Figure 5 shows the use of a shift register with associated circuitry in an interface between a multi-processor system and another processor.

The arrangements described herein use the processor described and claimed in the above-mentioned application, which is a one-bit machine having data inputs connected via noise filters to input staticisers, and data outputs connected to output staticisers in which the results of the processing operations done by the device are staticised. There is also a RAM for data to be used in the processing, which data may include intermediate processing results.

Also included are delay elements and low frequency clocks, the latter being in effect pulse dividers. Instruction words are supplied from an external program memory and each includes six address bits and two function bits. The address bits go to address decoding and selection circuitry while the instruction bits control the operation of a logic unit, which does the processing. As will be seen later, a few of these address codes are in fact used for what are in fact non-address functions.

These instruction words are supplied parallel-wise from the program memory in a fixed cycle of these words.

The shift register-processor combinations described herein are so connected as to use auxiliary input pins and output pins of the processor, and possibly one or more of the other inputs and outputs mentioned above. The designations of the pins thus used are RH, WP, LO and GL. Such an arrangement can work with a delay of exactly two instruction sycles before the data becomes valid on the above pins and also other direct outputs, such as those from the output staticisers. This delay exists because the processor used herein uses two-phase logic, and is an LSI device. The functions of the auxiliary pins referred to above are as follows: (a) RH is a direct input to the processor and the data appearing on this pin is read into the logic unit by the READ instruction. In this case pin RH is allocated address o.

(b) LO is the data output of the arithmetic and logic unit, and is only valid for WRITE instructions. For READ instructions LO remains at logic 0.

(c) WP is an output from the logic unit which is logic 1 for every WRITE instruction (WRX, WRX, WRO) and is equal to logic 0 for all other instructions.

(d) GL is an output from a latch, called the enable latch, within the processor which is set to 1 on the occurrence of one specific address code No. 14, (octal) in this case, and reset to O on another specific address, 15 (octal). Instructions with addresses 14 and 15 are called FLIP instructions.

The above mentioned outputs LO and WP are inhibited if the enable latch is at logic 0. The FLIP instruction (i.e. 14 or 15) produces logic 1 at WP if the function part of the program word indicates a WRITE decode. The action of the logic unit is inhibited if the address decode indicates that the instruction workd is a FLIP instruction.

The four sorts of instructions, defined by the four possible values of the two function bits are: (i) RD which meand READ. With a normal addressx it means read from that address to the logic unit LU. With address 0 it allows direct read in the LU via pin RH. Address 77 is fixed logic 1 value.

(ii) RD, which is Read and Complement. With any address it means read from that address to the LU with complementing. The LU automatically performs the NAND function on data fed into it by RD and RD instructions.

(iii) WR, which meand WRITE. This transfers the result of calculation since the previous WR or WR to the address in the instruction. With address 0 it provides a logic unit reset function.

(iv) WR, which means write the complement of the result of the calculation to the address in the instruction. With address 0 it provides an OR function.

It will be noted that the instruction code differs in a few respects from those described in the abovementioned application No. 23067/74 (Serial No. 1448041).

In the circuit of Figure 1 the shift register SR may be of any number of bits with parallel inputs indicated at IP, its serial input being connected to OP1, which is one of the outputs from the processor BP via its output staticisers. The output of SR is connected to RH, which is a direct input to BP via which the input data is read into the processor's logic unit by a READ instruction. The WP output from BP clocks SR on each WRITE instruction, so that SR is shifted at the rate and timing desired by suitably located WRITE instructions in the progam.

The GL output provides a serial enable signal from the BP in response to a FLIP instruction of the WRITE type. This permits stepping of SR. Thus data entered into SR over the inputs IP can be entered into the random access memory of the processor BP.

We assume that four bits M1 - M4 of the random access memory are used for receiving data from for example a 4 bit shift register. The program for this includes pulse generation as necessary via OP1, to cause parallel loading of SR from inputs IP whereafter a FLIP instruction of the WRITE type produces a first WP output pulse as mentioned above. Each step of the sequence thereafter involves two instructions, RD - RH followed by WR - Mx (i.e.

transfer the result of the previous stage in the processing into address Mx of the RAM), which cause reading from the end-most bit of SR via input RH into the processor's logic unit, followed by writing into Mx from the logic unit. Each of these WR instructions also produces a WP pulse to step SR.

Thus the effect of the RD - RH, WR - Mx. combinations is to transfer the data held in the 4 bit shift register to RAM bits M1 - M4, the data from SR thus replacing data already in the RAM. After the last such instruction word combination a further FLIP instruction of the READ type ends the sequence. This resets the GL output to remove the serial enable signal from SR and prevents further stepping of SR to subsequent WR instructions in the program.

The above instructions are preceded by RD77 (77 in Octal) which is logic 1 follows by WR-OP, (write to OP1) and then WR - OP1 (write with inversion to OP1). This combination generates a pulse at OP1 which defines the start of an input multiplexing operation.

Figure 2 shows the use of a shift register to provide an output multiplex function. Here the data input to the register SR is via the LO output, with clock input from WP via a gate controlled by a pulse 1,and with a serial enable output from GL. The shift register output is via a set of four output latches with respective outputs 21-24, clocked at OP1. The bits which appear on these outputs 21-24 are referred to as the z lists, i.e. both z -z4 respectively.

The sequence starts with the FLIP instruction of the WRITE type, followed by a sequence of instructions for each Z bit. Each of these sequences may involve a calculation whose result is sent to the shift register via LO. Thus these results are assembled in SR and stepped therealong by means of the pulses occurring at the WP for each write instruction in the program sequence, with transfer to the latches under control of OP1. One such sequence coule be Zl = A.B, involving instructions RDA, RDB, WRZ. This means that the content of location A in the processor's internal memory is written to the logic unit, then B is written from the internal memory to the logic unit and the result of the logical AND operation of A with B is formed in the logic unit, whereafter WR writes to Z - via LO. The sequence is terminated by the READ type FLIP instruction as before. The sequence ends with the RD77, WR-OP, WR - OP sequence which as in Figure 1 generates a pulse at OP1 which in this case clocks the data from SR into the output latches Z1-Z4.

Figure 3 combines the input multiplexing and output multiplexing functions, and in one program for this, the FLIP - WRITE instruction is followed by a first sequence for input multiplexing, then a second sequence for the output multiplexing, followed by the FLIP READ instruction.

The instruction sequence in this program is processed by RD77, WR-OP1, RDOP1 and followed by RD77 - WR OP - WR OP2 the former causing parallel load of input data IP into the SR and the latter causing output data in SR to be entered in the output latches. In view of the descriptions already given of Figures 1 and 2 it is felt that no further description of Figure 3 is needed.

Figure 4 shows the use of a shift register SR to augment the RAM of the processor BP. This shift register is of any desired length, e.g. n bits, and a block of m bits of the RAM in BP is assigned to inter-act with the shift register bits. All of these (n + m) bits are assigned to status-defining variables, i.e. variables which have to be held in memory from one program cycle to the next. Thus the effective size of the processor's RAM has been increased byn bits.

From the above it follows that these m bits of the RAM may be regarded as part of an (n + m) bit shift register, which also includes the n bits of SR. Hence this shift register will be arranged to receive (n + m) clock pulses per program cycle.

This program's cycle is divided into a number of portions, known as segments, and at the start of each segment up to m bits of data are exchanged with SR, the number of bits thus exchanged depending on the requirements of the program. In the system desided m < n. In between these data exchanges, the processing operations for the variables currently occupying the m RAM bits are performed i.e. the program works on these bits.

Thus if we assume m = 4 and n = 8 we get the following: Start BP-RAM SR 1st Exchange ABCD EFGHJKLM Evaluate equations for ABCD.

Evaluate other equations.

2nd Exchange EFGH JKLMABCD Evaluate equations for EFGH.

Evaluate other equations 3rd Exchange JKLM ABCDEFGH Evaluate equations for JKLM.

Evaluate other equations.

Return to Start The instruction sequence for each exchange of data commences with RD14, the FLIP instruction followed by sequence of read, write, read inverse and write inverse (RD, WR, RD, WR) as follows: FLIP RD14 RD M1 (A) WRO RD RH (E) WR RD M2 B) and so on for each bit interchange.

This means that after RD14, the content of M1, i.e. A, is read out by RDMl, and sent over output LO by WR 0, whereafter RD - RH takes the end-most bit from SR into BP, whereafter WR M1 puts this bit in M1, so that it replaces A therein. RD M2 initiates the same sequence in respect of bit M2 of the RAM.

The sequence is ended by RD15, the other FLIP instruction. Output GL of BP is at logic 1 from WRO to the end of RD15, and SR clock pulses occur on WR M1 and equivalent instructions for each transfer. These are generated by external gate G. Thus the full sequence for this transfer is as follows: SIR GL LO Clocks FLIP RD14 0 - 0 RD Ml (A) 0 - 0 WRO 1 0 0 RDRH(E) 1 0 0 WR M1 1 (A) 1 RD M2 (B) 1 0 0 WRO 1 (E) 0 RD RH (P) 1 0 0 WR M2 1 (B) 1 RD M3 (C) 1 0 0 WRO 1 (F) 0 RD RH (G) 1 0 0 WR M3 1 (C) 1 RD M4 (D) 1 0 0 WRO 1 (G) 0 RDRH(H) 1 0 0 WE MY 1 (D) 1 RD15 1 0 0 0 (H) 0 note that with the programming tachniques used for BP, the RAM bits which store information derived during processing are generally only used at limited periods in the program cycle, and usually these periods are close together. This makes the use of a shift register cyclable an integral number of times per program cycle especially convenient.

Usually this cycling is once per program cycle, but more than once is possible.

The shift register used can be a CMOS device so designed that the length of the register is determined by a 5-bit code applied to 5 of its input pins. As used herein the lengthdetermining code is preset for each processor program, and is permanently strapped so that the shift register as assigned to processor has a fixed length.

There are certain constraints on the use of such storage: (a) The bits stored in the RAM/SR exchange cannot be used extensively in expressions throughout the program.

(b) The bits involved in any given RAM/SR exchange cannot be used in segments of the program for which these bits are during that segment, in the shift register.

Thus the choice of the bits which can be stored in the shift register is program-dependent.

If the processor has adequate inputs and outputs available, two or more shift registers could be connected to the same processor. In such a case one shift register uses the RH and LO pins as in Figure 4, and the or each other shift register uses one of the other inputs and one of the other outputs referred to in the brief description given above of the processor of our above-mentioned Application.

Figure 5 is an interface between a multiprocessor system, represented by the chain dotted box, and another processor (not shown), which could be a similar processor to the ones in the box, or a larger processor. One of the processors is indicated at BPN. The interface includes a parallel in-parallel out and serial in-serial out shift register SR, and the data in SR is exchanged as required with data in the random access memory of any of the processors such as BPN, and also with the larger processor.

The processor involved in such a data exchange is selected by inserting the address of the wanted processor into the address buffer AP from the larger processor. This buffer, in conjunction with a demultiplexer DEMUX, applies a logic 1 conditions to the EN input of the selected processor, assumed to be BPN. A multiplexer MUX responds to the same address to connect the LO output of the same processor to the serial input of the shift register SR.

The read-only memory ROM contains the program sequence which serves all of the processors in the chain-dotted box, and this program is divided into two areas. The first of these areas is the application program forthe logical functions which the processor is performing on its controlled circuit. This program ends with a RESET PROGRAM COUNTER instruction - this counter being with one which determines the sequence in which the instructions words leave ROM. The second area of ROM contains a data exchange program, which begins with a FLIP instruction and ends with a RESET (WRO) instruction.

The shift register SR may be of any number of bits within the capacity of the processors such as BPN, but usually each data exchange would involve 8 bits or less. When the data exchange is completed, the data originally placed parallel-wise in SR by the large processor occupies an area A of the selected processor's RAM, and the data from the processor's memory area B is in the register SR. Areas A and B of the processor's memory could be the same, could overlap or be completely separate. This data exchange is controlled by a clock CK, which is derived by direct decoding from the output word of the ROM for any WRITE instruction that occurs in the data exchange segment of the program.

The detailed coding for the data exchange program is as follows: FLIP RD14 Sets EN latch of addressed BP RDO WRAl RDO WR A2 Shift register contents to RAMbitsAl-An.

7 WR An RD Bl WRZ RAM bits B 1Bn to RD B2 shift register.

WRZ WRO Sets all EN latches in BPS.

The processor program in ROM normally cycles over the area containing the application program because of the RESET PROGRAM COUNTER instruction between the applica tion and data exchange programs, which causes the data exchange program to be stepped over, i.e. omitted from the operational sequence. When the other processor requires a data exchange with one of the processors such as BPN it loads the buffer AP with the address of the wanted processor - e.g. BPN - and it loads the shift register SR with the data to be sent to that processor.

A flag, derived from AP, causes an inhibit condition to be placed on the RESET PROG RAM COUNTER function of the program in ROM, so that at the end of the next application program cycle, the program in ROM steps on to the date exchange program. This causes data exchange to take place as described above, and at the end of this data exchange another flag is set which removes the inhibit to the RESET PROGRAM COUNTER, so that the application program runs as before. When the other processor reads the data placed in SR by the selected processor, it resets the flags for a subsequent operation.

WHAT WE CLAIM IS: 1. An electrical data processing system which includes a process as claimed in claim 1 of our Patent No. 1,448,041, a clock pulse source, an external program memory which contains a program of instructions for the control of the data processing operations, the instructions being supplied to the processor singly and successively under the control of clock pulses from the clock pulse source, a shift register having its serial input connected to an output from the processor connections whereby the clock pulse source supplies clock pulses to the processor and the shift register as well as to the program memory, and connections within the processor such that data transfers between individual address locations of the internal memory of the processor and the shift register are effected under the control of certain instructions of the program.

2. A system as claimed in claim 1, and wherein the shift register has its serial output connected to an input to the processor.

3. A system as claimed in claim 2, in which the internal memory of the processor has a plurality m of bit locations reserved for the reception of data bits from the shift register, which latter has capacity forn bits, and in which the bit transfers in response to the clock pulses from the processor occur from the shift register to said reserved storage bit position.

4. A system as claimed in claim 2, in which the shift register has a plurality of parallel outputs each of which extends from one of its stages and via each of which a data bit may be read out of the shift register, in which the program which controls the processor includes instructions each of which extends from one of its stages and via each of which a data bit may be read out of the shift register, in which the program which controls the processor includes instructions each of which calls for a data bit to be sent out from the processor via the shift register, and in which when such an instruction occurs in the program the data bit in the processor to which that instruction relates is read from the processor to the shift register and the latter clocked by a clock pulse from the processor to move the bits therein along the shift register.

5. An electrical data processing system substantially as described with reference to Figure 1, Figure 2, Figure 3 Figure 4 or Figure 5 of the drawings accompanying the provisional specification.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (5)

**WARNING** start of CLMS field may overlap end of DESC **. exchange with one of the processors such as BPN it loads the buffer AP with the address of the wanted processor - e.g. BPN - and it loads the shift register SR with the data to be sent to that processor. A flag, derived from AP, causes an inhibit condition to be placed on the RESET PROG RAM COUNTER function of the program in ROM, so that at the end of the next application program cycle, the program in ROM steps on to the date exchange program. This causes data exchange to take place as described above, and at the end of this data exchange another flag is set which removes the inhibit to the RESET PROGRAM COUNTER, so that the application program runs as before. When the other processor reads the data placed in SR by the selected processor, it resets the flags for a subsequent operation. WHAT WE CLAIM IS:

1. An electrical data processing system which includes a process as claimed in claim 1 of our Patent No. 1,448,041, a clock pulse source, an external program memory which contains a program of instructions for the control of the data processing operations, the instructions being supplied to the processor singly and successively under the control of clock pulses from the clock pulse source, a shift register having its serial input connected to an output from the processor connections whereby the clock pulse source supplies clock pulses to the processor and the shift register as well as to the program memory, and connections within the processor such that data transfers between individual address locations of the internal memory of the processor and the shift register are effected under the control of certain instructions of the program.

2. A system as claimed in claim 1, and wherein the shift register has its serial output connected to an input to the processor.

3. A system as claimed in claim 2, in which the internal memory of the processor has a plurality m of bit locations reserved for the reception of data bits from the shift register, which latter has capacity forn bits, and in which the bit transfers in response to the clock pulses from the processor occur from the shift register to said reserved storage bit position.

4. A system as claimed in claim 2, in which the shift register has a plurality of parallel outputs each of which extends from one of its stages and via each of which a data bit may be read out of the shift register, in which the program which controls the processor includes instructions each of which extends from one of its stages and via each of which a data bit may be read out of the shift register, in which the program which controls the processor includes instructions each of which calls for a data bit to be sent out from the processor via the shift register, and in which when such an instruction occurs in the program the data bit in the processor to which that instruction relates is read from the processor to the shift register and the latter clocked by a clock pulse from the processor to move the bits therein along the shift register.

5. An electrical data processing system substantially as described with reference to Figure 1, Figure 2, Figure 3 Figure 4 or Figure 5 of the drawings accompanying the provisional specification.