GB1566442A

GB1566442A - Data transmission systems

Info

Publication number: GB1566442A
Application number: GB3359376A
Authority: GB
Original assignee: Marconi Co Ltd
Current assignee: BAE Systems Electronics Ltd
Priority date: 1977-07-29
Filing date: 1977-07-29
Publication date: 1980-04-30

Description

(54) IMPROVEMENTS IN OR RELATING TO DATA TRANSMISSION SYSTEMS (71) We, THE MARCONI COMPANY LIMITED, of Marconi House, New Street, Chelmsford CMi 1PL, Essex, a British Company, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention relates to transmission systems and more particularly to spread spectrum coding transmission systems.

Spread spectrum coding transmission systems are systems in which information is transmitted by coding a carrier signal firstly with a pseudo-random code pattern of +1's and -l's, by for example phase reverse keying the carrier signal, and then secondly coding the carrier signal so formed with the information in digital form by for example further phase reverse keying. The transmitted signal will normally contain a much larger number of phase reversals due to the spread spectrum coding than those due to the phase reversal imposed as a result of the phase reverse keying due to the information.

For the spread spectrum coding the code required to be imposed on the carrier signal requires to consist of a long pseudo-random sequence. Long codes can be generated in a number of known ways, one such way being the use of feedback logic on a shift register.

Long codes however have the disadvantage that they are difficult to synchronise rapidly at the receiver. Therefore for ease of synchronisation a shorter code length is preferable but a too short code length makes the code relatively simple to break.

It is therefore an object of the present invention to produce a code sequence for a spread spectrum coding system which is relatively difficult to break but is relatively easily synchronised at the receiver of the system.

The present invention therefore provides in its most general aspect a method of generating a coding sequence comprising the steps of generating a first code comprising a predetermined sequence of bits, generating a second code comprising a predetermined sequence of bits, and at the completion of a sequence of bits of the first code using a portion of the second code to determine a new starting point in the sequence of bits of the first code for a further sequence of the first code, the coding sequence output comprising a plurality of first code sequences so generated, wherein the respective bit rates of the first code and the second code are substantially different.

The present invention also provides a code sequence generator including means for generating a first code sequence comprising a predetermined pseudo-random sequence of bits, means for generating a second code sequence comprising a predetermined pseudo-random sequence of bits, and means controlled by the second code sequence arranged to determine at the end of a sequence of the first code a starting point in the sequence of bits of the first code at which the next sequence of the first code commences, wherein the respective bit rates of the first code and the second code are substantially different.

The present invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1 shows block diagrammatically a code generator in accordance with the present invention; Figure 2 shows the auto-correlation function of a code generated according to the present invention Figure 3 shows the power spectrum of a code generated according to the present invention; Figure 4 shows block diagrammatically a first rapid synchronisation scheme for synchronising code sequences generated by the code generator of Figure 1; and Figure 5 shows block diagrammatically a second improved synchronisation scheme for synchronising code sequences generated by the code generator of Figure 1.

In the present invention the spread spectrum signal is generated by phase reverse keying a carrier signal with a pseudo-random pattern of +1's and -1's. The width of the spread is proportional to the code bit rate and the degree of protection which the code provides is proportional to the spectrum width and to the code length. The inventive coding scheme enables long codes to be generated very rapidly by controlling a fast short code generator from a slower and normally longer code. These codes exhibit a similar auto-correlation function to conventional long maximal length pseudo-random sequences of the same bit rate, but it is posible to use a single fixed-pattern surface acoustic wave correlation device to speed up the receiver code synchronisation time by up to 1000 times when compared with a serial bit-by-bit code search.Furthermore a very large number of codes can use the same pattern of correlation device, and also the number of code bits over which the total correlation is performed is many times the length of the correlation device.

Referring now to Figure 1 of the drawings, the proposed codes may be generated in the following way. An m-bit shift register 10 is connected up with some feedback logic 11 comprising for example modulo-2 adders, so as to generate a (2 1) bit maximal length sequence (m will preferably be in the range 6 to 12). The register 10 is clocked at the desired code rate, and a divider 12 generates a code frame pulse every 2"-1 bits. On each frame pulse the position in the sequence at which the m-bit register 10 will commence the next sequence is determined by a new m-bit word from a long-code word generator 13, which generates a new word every frame. The long code word generator 13 is clocked by the output pulse from the divider 12 which also serves as a load control input for the shift register 10.An extra bit in the words from the long-code generator 13 is modulo-2 added to the shift register output in a modulo-2 adder 14 to produce polarity inversion of the output signal.

The effect of the above circuitry is to repetitively generate (2- 1) bit sequences at the high-speed clock rate. The starting position of each sequence is defined by the current word on the output of the long-code generator 13 which is assumed to be randomly selected. Thus the output of the m-bit shift register 10 is a series of randomly phase-shifted (2m1) bit sequences. The object of randomly phase-shifting the sequences is to generate sidebands around each of the discrete frequency components in the spectrum of the non-phase-shifted (2m1) bit pattern so that a continuous spectrum of approximately uniform density is produced.Phase-shifting the sequences produces sidebands on all the frequency components except the d.c. component, which is unaffected by phase shifts, and so tha phase-reversing modulo-2 adder 14 is included on the shift register output to eliminate any significant d.c. component from the output code pattern.

Provided that the words from the long-code generator 13 are random, the autocorrelation function and the power spectrum of the output code sequence approximate very closely to those obtained from a purely random sequence. The exact auto-correlation function may be calculated as follows.

The auto-correlation function (A.C.F.) of a (2m-bit) bit maximal length sequence x(r) is p-1 R(i) - Lim 1 R(i) = Po x ,,p > x(r) . x(r-i) r = -p = 1 for i = nN -1 for i = nN N where N = 2m-1. n is any integer, and i is also an integer. If we are considering square code bits then, when i is not an integer R(i) linearly interpolates between the integer values.

Now consider the A.C.F. of the proposed randomly-phase-shifted sequence for 0 S i < N. When i = 0, x(r) = x(r-i) and hence R(0) = 1. For non-zero values of i, N - i bits of every N - bit sequence in x(r) are multiplied by bits in the same sequence in x(r - i). The remaining i bits in each sequence in x(r) are multiplied by bits in an adjacent sequence in x(r - i). Let us call these groups the overlapping and non-overlapping bits in each sequence.

The A.C.F. of the overlapping bits is -1/N provided that all groupings of the N - i overlapping bits in each sequence are equally represented. This is true if the starting phases of the sequences are randomly distributed among all the N possible values. The A.C.F. of the non-overlapping bits is (- 1/N). a, where a is the correlation between the polarity inversions of adjacent code sequences. If the polarity inverting bits from the long-code generator are a random stream, a = 0.

Since the proportion of overlapping bits is (N-i/N) and of non-overlapping bits is i/N, the total A.C.F. for 0 < i < N is: R(i) = -1 N - i + -α i N N N N = i - N if α = 0 N2 If i N, then none of the bits in any N - bit sequence in x(r) are multiplied by bits in the same sequence in x(r - i). Hence all the bits are non-overlapping bits. Therefore R(i) = ### = if α = 0.

The above arguments have only considered positive values of i. However Auto-Correlation Functions are necessarily even functions and hence the results are equally applicable for negative values of i. This can be summarised as follows: R(i) = 1 for i = 0 I iii - N for 0 < i < N N = 0 for | i | # N This function is shown in Figure 2 and its Fourier transform, the power spectrum is shown in Figure 3. The Auto-Correlation Function may be regarded as the superposition of two triangular Auto-Correlation Functions and hence the power spectrum is given by: P(f) = (1 + 1).(sin x) - (sin Nx) N x Nx where x = fcf and fc = code clock rate.

Note that if N is large, the power spectrum approximately equals the power spectrum of a purely random code which is (sin x).

x The 'hole' in the middle of the spectrum is due to the limited length of the short code and the fact that the d.c. spectral line of the short code is much smaller than all its other low frequency lines. The width of the 'hole' is inversely proportional to N. The spectrum of the randomly phase shifted short codes can be regarded as the line spectrum of a regularly repeated short code with each line 'smeared' out by a (sin Nx) Nx function, caused by the phase-shift keying of each frequency component by a random function clocked at fc/N.

There are a number of useful properties of the above-described phase-shifted short codes for spread-spectrum work and these can be summarised as follows: (a) High-speed codes can be relatively easily generated because only the short code generator (e.g. 10 in Figure 1) need run at the code rate. The long-code generator (e.g. 13 m Figure 1) can run at a bit rate equal to m + 1 N of the code rate where N = 2m - 1 is the short code length. The short code generator need only have fixed tapping points and in a preferred embodiment a maximum of about 10 stages, and hence can be implemented with simple high-speed logic elements. If m = 10, then the speed reduction factor, m + 1 11 = N 1023 - .0108.

(b) Signals using a common communication channel may use the same short code pattern, provided that the long-code patterns of the users are not correlated, and provided that the period of the short code frame is significantly less than one data bit period. This is possible because the code patterns of any two users will only correlate for one in every N code frames on average, and if there are of the order of N frames per data bit there will be minimal interference between the two users. In this way significant protection against unwanted signals is available, even when modulated by the same short code pattern as the wanted signal.

(c) The search rate of a receiver attempting to obtain code lock may be increased by a factor of the order of N compared with a conventional bit-by-bit serial search, by using a surface-acoustic-wave (S.A.W.) delay-line correlator whose code pattern is matched to the short code. The technique for doing this in very poor signal-to-noise ratios is described hereinafter, but the main advantage of the method is that a single type of correlator with a fixed code pattern may be used to synchronise to any of a large number of users, each with a different long-code.

(d) The long-code generator 13 may be designed to produce any desired code length and may be either a linear maximal-length sequence generator or a non-linear generator. If the code is very long and is non-linear, then an 'epoch' synchronising scheme will probably be necessary At a pre-defined instant in time entitled the epoch, the code generator 13 is pre-set to a particular starting value and is left to run freely from then until the next epoch.

In order to acquire synchronism at a time between two epochs, it is necessary to preset the receiver generator to the epoch starting value and then to run the generator at a higher rate than nominal until it has caught up with 'real time'. It is therefore very useful if the normal clock rate of the long-code generator is much less than its maximum clock rate. Hence the relatively low normal clock rate of the long-code generator in the proposed coding scheme is an advantage.

(e) Although hereinbefore it has been assumed that the short code will be a maximal length pseudo-random binary sequence, there may be advantages in using other types of short code pattern. In particular it may be possible to select a short code sequence which at least partly compensates for the (sin x/x)2 roll-off in the power spectrum, which is caused by using square code bits rather than short impulses.

A method of synchronisation of a receiver code generator to a transmitter code generator is to clock the receiver generator at a rate slightly faster or slower than the transmitter generator and to search for the emergence of a narrowband signal from a receiver code mixer when the two codes drift into correlation. The search rate is limited by the integration time necessary to obtain the required signal/noise ratio on the output of the detector which is looking for the narrowband signal. At a given time the receiver is examining only one particular time shift of its code relative to the incoming code. However a S.A.W. correlator enables a receiver to examine the correlation between a large number of input bits and an internal code pattern at any given instant, and hence it provides the advantage of greatly increased code search rates.

One of the main disadvantages of S.A.W. correlators is the difficulty of making the correlator code pattern programmable. Most devices therefore are only capable of correlating the input signal with a fixed pattern of bits, determined by the connections to the pick-up electrodes distributed along the delay-line. If S.A.W. correlators are required for synchronising to a simple pseudo-random code, three main difficulties have been found.

Firstly a correlation pulse is only produced once per complete code pattern, and this can be relatively infrequently if a moderately long code is used. Secondly a very long correlator must be used if high processing gains are required, i.e. if the input signal/noise ratio is very poor. Thirdly. as previously explained, a particular correlator can only synchronise to one code pattern. If the code is changed, a new correlator is required unless it is programmable.

The use of phase-shifted short codes to generate long code sequences enables all of the above difficulties to be largely overcome. The basic scheme for rapid synchronisation is shown in Figure A. The I.F. spread spectrum signal is fed into a S.A.W. correlator 40 which is (2N-1) bits long and whose code pattern is two repetitions of the short code. Hence any shifted version of the short code will completely correlate at some instant with N of the bits in the correlator. The output of the correlator 40 will therefore consist of short bursts of I.F.

carrier at varying instants depending on the phase shift of each short-code pattern received.

The correlator 40 is unlikely to provide sufficient processing gain for these correlation pulses to exceed the random noise level. Therefore it is necessary to perform some signal averaging on the pulses. Before this can be done it must be arranged that the pulses be retimed so that they occur at regular intervals one code frame period apart, and this is achieved by an N-bit tapped S.A.W. delay line 41. The tap position is selected by a receiver long-code word generator 42, which is identical to the long code word generator 13 in the transmitter, such that the code phase shift introduced by the transmitter long-code generator 13 is corrected by the delay line. The polarity inversions introduced in the transmitter by the phase reversing modulo 2 adder 14 are corrected by the balanced modulator 43 following the tapped delay line.These corrections are only valid if the receiver long-code generator 42 Is synchronised within + E code frame of the transmitter code generator.

The output of the N-bit tapped delay line 41 is fed via the balanced modulator 43 to a delay line integrator comprising a resistive network 44, 45, a gating circuit 46 and an N bit delay line 47. Assuming that the correlation pulses have been correctly retimed, they will be integrated in the S.A.W. delay-line integrator 47. This is achieved by arranging for the delay around the integrator loop to be exactly one code frame period, and for the loop gain to be unity. If the delay line 47 is initially filled with zero signal by the gate pulse, then any pulses of I.F. carrier which are applied from the modulator 43 after the gate pulse is removed will start to circulate through the delay line, and will continue to circulate around the loop until the next gate pulse is applied.

When a number of pulses occur separated by multiples of the code frame period, the pulses will add together to create a single large pulse. At the end of the integration period a peak detector 48 searches for a large pulse, and if one is present its instant of occurrence tells the receiver where in the frame it should preset the receiver short code generator in order to correlate with the incoming signal.

Unwanted signals which use the same short code as the wanted signal will generate correlation pulses on the correlator output, but the tapped delay line will not correct the timing of these pulses to produce a uniform stream. Hence they will get randomly distributed throughout the delay-line integrator and will not produce a large amplitude peak.

The above arguments have assumed that the long-code word generator is sufficiently closely in synchronism with the incoming wanted signal that the correlator output pulses are correctly retimed by the tapped delay line 41. If the tap selector controls the position of the output from the delay line 41, while the delay line input is a fixed electrode, then the tap need only be switched to the correct position just before the correlation pulse occurs and it may be switched to the next position any time after the pulse has occurred. Since the switching instants are spaced one frame apart, there is a tolerance of almost one frame period on the timing of the receiver long-code generator 42. When the long-code generator 42 is not in frame synchronisation with the signal, the correlation pulses will be randomly retimed and very little pulse integration will occur.

The procedure for a code search is to advance or delay the timing of the long-code generator 42 in steps of just under one frame period and after each step the delay-line integrator 47 is reset to zero. An integration is performed over an appropriate number of frames to obtain a good signal/noise ratio in the integrator, and the integrator is then examined for a significant pulse. If a large pulse is not found, the integrator is reset, the long-code generator 42 is advanced or delayed, and the process is repeated. When a large pulse is found, this probably indicates that frame synchronism has been achieved and the timing of the pulse gives the time shift required to obtain bit synchronism. It may however be necessary to repeat the measurement when a large pulse is found in order to obtain an adequately low false alarm rate.

The speed-up factor of approximately N when compared with a serial bit-by-bit code search, is possible because the long-code generator 42 may be advanced or delayed by almost one frame after each integration period, whereas a serial search code generator can only be advanced or delayed by approximately one code bit. The periods of integration for a given detector signal/noise ratio should be similar.

Though the system of Figure 4 provides considerable adlvantages over known prior art synchronising systems it suffers from several disadvantages. These are: (a) The correlator 40 is (2N-1) bits long but is only being used to correlate N signal bits at any instant. Hence its processing gain is reduced by 3dB when compared with an N-bit correlator correctly matched to the input signal.

(b) The tapped delay line requires N separately selectable taps which results in a very complex structure for large values of N.

(c) A high power unwanted signal which is using the same short code as the wanted signal would cause large correlation pulses on the correlator output and any one of these pulses could be comparable in amplitude with the sum of all the wanted pulses. This would result in false sync indications.

(d) The allowable uncertainty of the input signal frequency is limited by the requirement that all signal pulses should add coherently over the full integration period. Hence the carrier phase error over the integration period must not exceed 1800. The presence of data modulation on the signal will also affect synchronising performance unless the data rate is significantly less than the integration period.

(e) Accurate integration of all pulses over the full integration period requires that the loop gain of the delay-line integrator be very close to unity. The gain error must be much less than 1/n, where n is number of code frames in the integration period.

The above problems may be overcome or minimised by using the second improved synchronisation scheme outlined in Figure 5.

The (2N-1) bit correlator 40 is replaced by four 5N/4 bit correlators 50, 51, 52, 53, each correlating a different set of N/4 shifts of the short code (strictly the length of the correlators need only be (5N-3)/4 bits). One of the four correlator outputs is selected by the most significant two bits of the words from the long-code generator. The number of bits contributing noise to the output is thus reduced from (2N-1) to (5N-3)/4 which will reduce the noise by approximately 2dB while leaving the signal unaffected. Hence the degradation listed above at (a) can be reduced from 3dB to ldB.

The use of four correlators means that the amount of subsequent retiming of the correlation pulses is limited to N/4 bits instead of N bits. Furthermore the complexity of the delay line tap selectors can be reduced considerably by using a coarse 54 and a fine 55 delay line. The coarse delay line is N/4 bits long with 2P taps, spaced one per 2q bits, and the fine delay line is 2q bits long with a tap for each bit. Thus p + q must equal log2 (N + 1) - 2 and for minimum complexity p should approximately equal q. The coarse and fine delay line settings are controlled by the bits other than the most significant two bits from the long-code word generator.

An alternative to the use of the four 5N/4 bit correlators 50, 51, 52, 53, would be to split the (2N - 1) bit correlator 40 of Figure 4 into eight N/4 bit blocks in series, and to select as output the sum of any five adjacent blocks. This would give four possible output conditions as in Figure 5, except that a variable delay of up to N bits would be necessary as in Figure 4.

A small penalty, incurred when the scheme of Figure 5 is used, is a reduction in the search rate by 25%, because the tolerance of the frame timing of the long-code generator is reduced to 3/4 of a frame instead of almost one frame. Hence the generator can only be advanced or delayed in steps of 3/4 of a frame.

A peak clipping circuit 56 is included after the correlators in order to improve the rejection of a high power unwanted signal using the same short code as the wanted signal.

The clipper should be arranged so that it linearly amplifies the random noise and the low level correlation pulses of the wanted signal and other low level unwanted signals, but clips the correlation pulses from any high level signal using the correct short code. In this way the amplitude of individual high level correlation pulses can be limited so that they are not confused with the integrated wanted pulses. A peak clipper is normally regarded as an undesirable element in the r.f. stages of a receiver; however the action of the correlators is to time-division-multiplex any signals using the same short code in different phases, and in such a situation a peak clipper is found to reduce the amplitude of large signals without affecting the small signals.

The problem of carrier phase coherence imposing limitations on the maximum integration time due to carrier frequency uncertainty and the presence of data modulation may be solved in two ways. Firstly the region of possible frequency uncertainty may be split into a number of adjacent bands, whose width is inversely proportional to the integration period required. For every setting of the long-code generator 42 all of the bands could be searched in turn, allowing a separate period of integration for each band searched. This has the obvious disadvantage of reducing the search rate in proportion to the number of bands, but it can cope with relatively large frequency uncertainties in bad signal/noise conditions.

The nominal centre frequency of each band is determined by the precise delay around the integrator loop, and could be varied by a variable phase shift network 60 somewhere in the loop. Data modulation will substantially degrade the performance of this system if the data rate is greater than the width of the frequency bands.

The alternative way of reducing the phase coherence problem is to reduce the gain of the integrator loop so that it becomes a 'leaky integrator' or a single pole comb filter. The bandwidth of the filter should be adjusted to approximately equal the frequency uncertainty or the data rate, whichever is greater. Any further extension of the integration period to improve the final signal/noise ratio must be achieved by integration of the envelope of the pulses in the peak analyser block 48. This can yield useful results as long as the signal is at least as large as the noise prior to envelope detection. However if the signal is much less than the noise then envelope detection will cause a significant loss in signal/noise ratio.

Figure 5 also includes a carrier burst generator 57 and a gain control circuit 58. These blocks are designed to enable the gain of the integrator loop to be set very precisely either to unity or slightly less, so that the gain is virtually independent of slow changes in gain in the elements of the loop caused by factors such as temperature and ageing.

If the loop is operated as a pure integrator with unity loop gain, the gain can be controlled as follows. Immediately after the gate pulse has been applied to clear the delay line, a short burst of carrier is injected from the carrier burst generator 57. The sampling switch 59 which feeds the gain control circuit 58 samples the delay line output whenever the carrier burst is present and compares its amplitude with the amplitude injected by the burst generator 57 after the gate pulse. If the loop gain is unity this amplitude will remain constant, whereas a gain which is greater or less than unity will cause the amplitude to grow or decay.

The gain control circuit adjusts the loop gain so that the burst amplitude remains constant and hence the loop gain must be unity. It is important that no other signals be allowed to interfere with the burst, and so the balanced modulator output should not be fed to the summing junction when the burst is present. The burst may be timed to occur anywhere in the quarter of the frame period where correlation pulses are not present.

If the delay line 47 is required to operate as a 'leaky integrator' which need never be reset to zero, the carrier burst generator 57 can be eliminated and the carrier burst can be allowed to build up as a natural oscillation in the loop. A small amount of extra gain needs to be switched in when the burst is present so that the loop gain for the burst is set to unity, resulting in slightly less than unity gain for the signals. The timing of the burst would be confined to the time when the extra gain is present since at other times any perturbations will decay to zero.

The proposed scheme for generation of spectrum spreading codes therefore has a number of advantages over the conventional approach which uses a single pseudo-random code.

The two main advantages being firstly that the main (long) code generator of the proposed scheme can be clocked at a small fraction of the rate of the output bit stream, and secondly that a rapid synchronisation method becomes possible with the proposed codes, which uses short fixed-pattern S.A.W. correlation devices such that a number of users on the same channel may use the same S.A.W. devices without significant mutual interference.

WHAT WE CLAIM IS: 1. A method of generating a coding sequence comprising the steps of generating a first code comprising a predetermined sequence of bits, generating a second code comprising a predetermined sequence of bits, and at the completion of a sequence of bits of the first code using a portion of the second code to determine a new starting point in the sequence of bits of the first code for a further sequence of the first code, the coding sequence output comprising a plurality of first code sequences so generated, wherein the respective bit rates of said first code and said second code are substantially different.

2. A method as claimed in Claim 1, wherein the sequence of bits of the second code is longer than the sequence of bits of the first code.

3. A method as claimed in Claim 1 or Claim 2, wherein the first code comprises a sequence of (2"-1) bits and m is an integer in the range 6 to 12.

4. A method as claimed in any preceding claim, wherein the first and second codes are pseudo-random binary sequences.

5. A method as claimed in any preceding claim. wherein the first and second codes are pseudo-random binary sequences and a further portion of the second code is used to produce a polarity inversion of the coding sequence output.

6. A method as claimed in any preceding claim, including the step of synchronising a similar code generator in a receiver with the coding sequence output by clocking the receiver code generator at a rate faster or slower than the coding signal output and searching for a position in which the two codes drift into correlation.

7. A method as claimed in Claim 6, wherein synchronism is obtained using synchronising means comprising surface-acoustic-wave delay line correlator means having a code pattern which is matched to the first code.

8. A method as claimed in Claim 7, wherein the correlator means has a code pattern which is two repetitions of the first code.

9. A method as claimed in Claim 7, wherein the correlator means comprises a plurality of surface-acoustic-wave delay lines each correlating a different set of shifts of the first code.

10. A code sequence generator including means for generating a first code sequence comprising a predetermined pseudo-random sequence of bits, means for generating a second code sequence comprising a predetermined pseudo-random sequence of bits, and

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. pulses in the peak analyser block 48. This can yield useful results as long as the signal is at least as large as the noise prior to envelope detection. However if the signal is much less than the noise then envelope detection will cause a significant loss in signal/noise ratio. Figure 5 also includes a carrier burst generator 57 and a gain control circuit 58. These blocks are designed to enable the gain of the integrator loop to be set very precisely either to unity or slightly less, so that the gain is virtually independent of slow changes in gain in the elements of the loop caused by factors such as temperature and ageing. If the loop is operated as a pure integrator with unity loop gain, the gain can be controlled as follows. Immediately after the gate pulse has been applied to clear the delay line, a short burst of carrier is injected from the carrier burst generator 57. The sampling switch 59 which feeds the gain control circuit 58 samples the delay line output whenever the carrier burst is present and compares its amplitude with the amplitude injected by the burst generator 57 after the gate pulse. If the loop gain is unity this amplitude will remain constant, whereas a gain which is greater or less than unity will cause the amplitude to grow or decay. The gain control circuit adjusts the loop gain so that the burst amplitude remains constant and hence the loop gain must be unity. It is important that no other signals be allowed to interfere with the burst, and so the balanced modulator output should not be fed to the summing junction when the burst is present. The burst may be timed to occur anywhere in the quarter of the frame period where correlation pulses are not present. If the delay line 47 is required to operate as a 'leaky integrator' which need never be reset to zero, the carrier burst generator 57 can be eliminated and the carrier burst can be allowed to build up as a natural oscillation in the loop. A small amount of extra gain needs to be switched in when the burst is present so that the loop gain for the burst is set to unity, resulting in slightly less than unity gain for the signals. The timing of the burst would be confined to the time when the extra gain is present since at other times any perturbations will decay to zero. The proposed scheme for generation of spectrum spreading codes therefore has a number of advantages over the conventional approach which uses a single pseudo-random code. The two main advantages being firstly that the main (long) code generator of the proposed scheme can be clocked at a small fraction of the rate of the output bit stream, and secondly that a rapid synchronisation method becomes possible with the proposed codes, which uses short fixed-pattern S.A.W. correlation devices such that a number of users on the same channel may use the same S.A.W. devices without significant mutual interference. WHAT WE CLAIM IS:

1. A method of generating a coding sequence comprising the steps of generating a first code comprising a predetermined sequence of bits, generating a second code comprising a predetermined sequence of bits, and at the completion of a sequence of bits of the first code using a portion of the second code to determine a new starting point in the sequence of bits of the first code for a further sequence of the first code, the coding sequence output comprising a plurality of first code sequences so generated, wherein the respective bit rates of said first code and said second code are substantially different.

means controlled by the second code sequence arranged to determine at the end of a sequence of the first code a starting point in sequence of bits of the first code at which the next sequence of the first code commences, wherein the respective bit rates of said first code and said second code are substantially different.

11. A code sequence generator as claimed in Claim 10, wherein the sequence of bits of the second code is longer than the sequence of bits of the first code.

12. A code sequence generator as claimed in Claim 10 or Claim 11, wherein the first code comprises a sequence of (2m1) bits and m is an integer in the range 6 to 12.

13. A code sequence generator as claimed in Claim 12, wherein the means for generating the first code sequence comprises an m-bit shift register in combination with feedback logic comprising modulo-2 adding means.

14. A code sequence generator as claimed in any one of Claims 10 to 13, wherein the first and second codes are pseudo-random binary sequences.

15. A code sequence generator as claimed in any one of Claims 10 to 14, including means for producing polarity inversion of the coding sequence output in dependence on a further portion of the second code.

16. A code generator as claimed in Claim 15, wherein the means for producing polarity inversion of the coding sequence output comprises modulo-2 adding means.

17. A code sequence generator as claimed in any one of Claims 10 to 16, in combination with synchronising means comprising surface-acoustic-wave delay line correlator means having a code pattern which is matched to the first code.

18. A code sequence generator as claimed in Claim 17, wherein the correlator means has a code pattern which is two repetitions of the first code.

19. A code sequence generator as claimed in Claim 17 or Claim 18, wherein the correlator means comprises a plurality of surface-acoustic-wave delay lines each correlating a different set of shifts of the first code.

20. A method of generating a coding sequence substantially as hereinbefore described with reference to Figure 1 of the accompanying drawings.

21. A method of generating and synchronising a coding sequence substantially as hereinbefore described with reference to Figures 1 to 4 of the accompanying drawings.

22. A method of generating and synchronising a coding sequence substantially as hereinbefore described with reference to Figures 1 to 3 and 5 of the accompanying drawings.

23. A code signal generator substantially as hereinbefore described with reference to Figure 1 of the accompanying drawings.

24. A code signal generator as claimed in Claim 23, in combination with a synchronising arrangement substantially as hereinbefore described with reference to Figure 4 of the accompanying drawings.

25. A code signal generator as claimed in Claim 23, in combination with a synchronising arrangement substantially as hereinbefore described with reference to Figure 5 of the accompanying drawings.