GB1565841A

GB1565841A - Microprogrammable computer system

Info

Publication number: GB1565841A
Application number: GB2484276A
Authority: GB
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1975-06-19
Filing date: 1976-06-16
Publication date: 1980-04-23
Also published as: DE2527272B2; FR2315124B1; ATA403676A; DE2527272C3; DE2527272A1; BE843132A; NL7606407A; AT367917B; CH600436A5; IT1081208B; FR2315124A1

Description

(54) MICROPROGRAMMABLE COMPUTER SYSTEM (71) We, SIEMENS AKTIEN SELLSCHAFT, a German Company, of Berlin and Munich, Federal Republic of Germany, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to a microprogrammable computer system comprising a control unit and a processing unit.

A growing interest has been taken in micro-programming, which provides several advantages, for the control of digital calculating units, for which control signals for a micro-programme-controlled processor are derived from bit patterns which are combined in micro-command words and are stored in read only (fixed word) stores or control stores in which recordings can be made.

As explained in Chapter 2.8 of the book "Microprogramming: Principles and Practices" by Husson, Prentice Hall 1970, the micro-programme store forms an essential component of a micro-programme control unit and generally determines the costs thereof. Such a store possesses two dimensions which are governed by the number of micro-command words to be stored and the width of, i.e. the number of bits in, each micro-command. The required number of micro-commands is dependent upon the size and the complexity of the microprogrammed machine commands, upon their formats, upon the addressing mechanism, and upon the efficiency of the interrupt treatment of a data-processing system of which the micro-programmed processor forms a fundamental component.

The width of each micro-command word is determined on the basis of the extent of the parallel operation possible in the system and the nature of the coding. A very wide micro-command also facilitates a larger number of elementary operations to be processed largely in parallel in a single processing cycle, so that the number of required micro-command words for a microprogramme assigned to a machine command is reduced.

As already mentioned, either a fixed word store or a store in which recordings can be made can be used. A microprogramme store in which recordings can be made provides advantages in comparison to a fixed word store. Thus a data processing system provided with a micro-programme store in which recordings can be made is capable of being matched considerably more easily as it is possible to alter the micro-programmes. Changes in the system architecture produce no or only slight circuitry alterations, and faults in the programme can be corrected without circuitry alterations. If, however, the micro-programme is stored in a fixed word store, such corrections each necessitate a new fixed word store.

Emulation, i.e. the simulation of alien system properties by corresponding microprogrammes, and the diagnosis of the permanently wired circuit by means of diagnosis micro-programmes, are also easier to effect with a micro-programme store in which recordings can be made (hereinafter referred to as a recordable microprogramme store). In both cases appropriate micro-programmes merely require to be loaded into the recordable microprogramme store from an external store, whereas a fixed word store would have to contain such micro-programmes continuously and therefore would have to possess a larger store capacity.

On the other hand it is not possible to load micro-programmes incorrectly into a micro-programme store constituted by a fixed word store, and in the event of a breakdown of the current supply microprogrammes are retained in a fixed word store, whereas a volatile recordable microprogramme store, which may for example be a semi-conductor store, would have to be reloaded.

Storage media in data processing systems are governed by the Faust rule that the costs per bit increase in proportion to the speed of the store. This also applies to a recordable micro-programme store.

If a recordable micro-programme store is combined, for example with the working store of the central unit of the data processing system, costs are saved in that firstly the working store is a storage medium which in comparison to micro-programme stores is slow but cheap and secondly no special interface is required for the microprogramme store.

Under optimum circumstances the machine cycle of a micro-programmecontrolled processor, i.e. the cycle time for the processing of a micro-command, should be matched to the access time to the micro-programme store in such manner that neither the processor has to wait for the micro-programme store nor the microprogramme store has to wait for the processor.

If, however, in order to achieve substantial cost savings, the micro-programme store is combined with a relatively slow working store, the optimum conditions are not achieved. In this case it is not advisable to extend the machine cycle in such manner that it is matched to the micro-programme store access time.

By means of other cost-favourable measures, however, the processor efficiency which is impaired by the slow microprogramme store can be increased. Thus our U.K. Patent Application No. 11046/76 (Serial No. 1536224) discloses a control unit in which between the recordable microprogramme store and a micro-command register there is arranged a relatively high speed buffer store of low storage capacity, the arrangement being such that the microcommand register can be loaded from the micro-programme store either directly or indirectly via the buffer store. Thus as soon as repeatedly run-through microprogramme loops occur the microcommands can be taken from the buffer store during successive runs of the loop, so that the long access time to the microprogramme store is avoided. Although this measure contributes to an increase in power of the processor, its effectiveness is limited to the processing of micro-programme loops.

Another measure consists in designing the data paths to the recordable microprogramme store to be twice as wide as the micro-command format. With one access to the micro-programme store it is then possible to address two consecutive microcommands which are then transmitted (one of them after intermediate storage) consecutively to the micro-command register.

Theoretically it would thus be possible to save half of all the store accesses, but this theoretical value is not reached as in the event of a programme branch or a microprogramme jump the second microcommand of a store access is not utilised.

This invention seeks to provide a method of controlling a micro-programmed processor which further improves upon the ratio between the average access time to the micro-programme store and the processing cycle, i.e. the time for the processing of a micro-command in the processing unit.

According to this invention there is provided a microprogrammable computer system comprising a processor and a control unit with a read/write microprogramme store, in which can be stored microprogramme commands comprising a plurality of bit pattern sections, the control unit having a command register into which, during the flow of a microprogramme, microcommands are consecutively transferred from the microprogramme store and a decoder which, in use, decodes the microcommand in the command register to produce control signals for control of the processor, the control unit being arranged, in operation, so that for a single microcommand in which said plurality of bit pattern sections define a main function and at least one subsidiary function the decoder decodes the command to produce control signals which control, in parallel, elementary processing operations, determined by the main function and subfunction(s), of a single cycle of the processing unit. and for double microcommands in which said plurality of bit groups define a first main function and a second main function the double microcommand is identified as such and the decoder decodes the two functions consecutively to control two consecutive cycles of the processing unit.

As already mentioned, the microcommand format is generally contrived to be such that a specific number of bit pattern sections are assigned to a main function.

The remaining bit pattern sections then define so-called subsidiary functions which are executed in parallel to the main function during a machine cycle in the processing unit of the processor. These subsidiary functions can for example be tests which influence the sequence address formation for the next micro-command. This microcommand format, which must of course correspond to the circuitry design of the processing unit, thus exploits a possible parallel operation in the processing unit of the processor in order to reduce the number of micro-commands in the assigned microprogramme which are required for the processing of a machine command.

The invention is based on the recognition that individual micro-commands or sequences of micro-commands repeatedly occur in which the bit pattern sections are not used for subsidiary functions. Hitherto this redundancy appeared unavoidable as one was unwilling to sacrifice the advantages of a possible parallel operation in the processing unit. The invention does not change in any way the processing of micro-commands in the processing unit, i.e. it does not result in any structural differences in the circuit arrangement.

The double micro-commands which can be used to accomodate two main functions in one micro-command word provide the advantage, however, of producing two main functions with the read-out of a microcommand word, i.e. of employing the processing unit of the processor for two consecutive processing cycles. Naturally the theoretically possible value of a reduction by half of the number of accesses to the micro-programme store is rarely, if ever, achieved, but in any case such microcommand words considerably contribute to an increase in the performance of the processor. Frequently one has a choice as to the positioning of a sub-function within a micro-programme: for example, when a test condition in the processor is not altered in the course of ten micro-commands, it can be interrogated by the appropriate test statement equally well in the first as in the tenth micro-command. Therefore in designing the micro-programme one has the opportunity to increase further the conditions for the use of double micro-commands.

The increase in performance of the processor is accompanied by a reduction in the micro-programme store space and a reduction in load on the interface to the main store system when the recordable microprogramme store is accommodated therein m addition to the working store.

Preferably each micro-command word comprises a bit pattern section for a group characteristic differentiating between various groups of micro-commands, and each main function bit pattern section comprises a function section and two address sections for micro-command operands which function and address sections together occupy less than half the remaining micro-command format.

In this case preferably, having been made available in the micro-command register, each double micro-command is identified on the basis of its group characteristics, in a first processing cycle only those bit pattern sections associated with the first main function are decoded, with the control signals derived therefrom the first main function is executed in the processing unit, the bit patterns of the first main function in the micro-command register are replaced by those of the second main function without a new access to the micro-programme store simply by reloading the micro-command register, and in a second processing cycle the reloaded part of the double microcommand is decoded and processed.

The invention wll be further understood from the following description by way of example of an embodiment thereof with reference to the accompanying drawings, in which: Figure 1 shows a block circuit diagram of a micro-programmed processor comprising a control unit and a processing unit, where for reasons of functional association the control unit includes a recordable microprogramme store; Figure 2 schematically illustrates the time flow in the processing of simple microcommands; Figure 3 illustrates an example of the basic construction of a micro-command; Figure 4 illustrates a corresponding example of the construction of a double microcommand; and Figure 5 schematically illustrates the time flow in the processing of double microcommands.

The block circuit diagram in Figure 1 of a micro-programme-controlled processor of a data-processing system shows a control unit SE and a processing unit VE. On account of the functional association, a recordable micro-prograrnme store WCM is provided within the control unit SE. A micro-command word stored in this microprogramme store can be addressed via the contents of an address register AR.

Information outputs of the microprogramme store WCM are connected in parallel to the inputs of a micro-command register MBR. This register is connected to a decoder unit DEC which serves to convert the particular information content of the micro-command register MBR into control signals which are fed via control signal lines ST to the individual function units of the processing unit VE.

In the processing unit VE arrows indicate, purely schematically, data paths DIl and D/O which indicate the data flow for data which are to be processed and data which have been processed. Control lines required for this purpose for addressing data which has been requested and is to be emitted are designated ADR.

In order to form the address of a following micro-command in a micro-programme, a switching network FMB is provided which is arranged between the micro-command register MBR and the address register AR.

In addition to this basic structure which is common to all micro-programme-controlled processors, the control unit SE contains, in addition to the bit-parallel connection of the information output of the micro-programme store WCM directly to the micro-command register MBR, an indirect data path via a buffer store MC formed from a high-speed register set. This buffer store can be addressed via the low-order bit positions of the address register AR. The information outputs of the buffer store MC are themselves connected to the inputs of the microcommand register MBR in parallel to the information outputs of the microprogramme store WCM. Therefore in the micro-command register MBR, microcommands can either be produced directly from the micro-programme store WCM or from the buffer store MC for decoding in the decoder unit DEC. This arrangement and the functional sequence of a microcommand in a micro-programme-controlled processor of this type is described and claimed in our U.K. Patent Application No.

11046/76 (Serial No. 1536224) and is not further described here.

Rather, in this connection. it is the time flow of a micro-command which will be explained in detail making reference to Figure 2. The overall time for the processing of a micro-command is composed, in the case of sequential processing, of two entities, namely the access to the microprogramme store WCM with write-in of the addressed micro-command into the microcommand register MBR, and the flow of a processing cycle, which consists of the decoding of the contents of the microcommand register MBR in the decoder unit DEC, the logic-linking of the register contents addressed by the micro-command in the processing unit VE, and the formation of the address of the next micro-command.

In the form of a time flow diagram. this is represented in Figure 2 as follows: 1 designates a processing cycle, in the course of which at a time 2 the address for the next access to the recordable micro-programme store WCM is established. The following time interval 3 is used for the access to the micro-programme store WCM and for the write-in of the addressed micro-command into the micro-command register MBR.

This is followed by the next processing cycle 1. Thus between two consecutive processing cycles 1 there is a second time interval 4 which corresponds to the waiting time during which the processor waits for the availability of the next micro-command.

The basic structure of a micro-command can be seen from the example. illustrated in Figure 3. of a micro-command format. In this example a width of 32 bit positions has been assumed for the micro-command format, as indicated by the digits 8 and 31 at the lower edges of the block. In the block itself sections are shown which comprise differing numbers of bit positions as can be seen from bracketed numerical statements above the sections of the bit patterns.

A first bit pattern section GR comprises three bit positions and in each case characterises one of several groups to which the relevant micro-command is to be assigned.

In this way it is, for example, possible to differentiate between arithmetic and logic word commands of storage or shift commands.

A second bit pattern section F comprises four bit positions and designates the nature of the main function of the micro-command, i.e. for example a specific micro-command of the group of arithmetic and logic word commands, e.g. an AND function.

Third and fourth bit pattern sections ADR1 and ADR2 each comprise five bit positions and contain the addresses of the first and second micro-command operands respectively. Thus the three last-mentioned bit pattern sections F, ADR1 and ADR2 establish a specific main function of the micro-command.

The remaining 15 bit positions of the micro-command format contain further bit pattern sections, which will not be mentioned in detail here, and which define specific sub-functions NF of the microcommand. Such sub-functions can relate to specific tests, the statement of direct operands, the statement of jump sequence addresses, and so on. The processing cycle is determined by the main function and the sub-functions are executed in parallel thereto.

It repeatedly occurs that it is not possible to define an effective sub-function in a micro-command. As. however. the microcommand format is generally fixed, in such a case the 15 bit positions are not used for sub-functions. This fact can be exploited in another respect as shown in Figure 4 which shows a micro-command format which is as wide as the general micro-command format described with reference to Figure 3. As a comparison with Figure 3 shows, this general micro-command format contains two main functions each with 14 bit positions in bit pattern sections F, ADR1 and ADR2.

If, in addition, only two bit positions are required for the group characteristic GR, which here, in a specific state, characterises the group of double micro-commands with two main functions, then of the 32 bit positions of the format 2 bit positions remain empty. In each case one of these bit positions G is assigned to one of the two main functions and facilitates a differentiation between two groups of double microcommands, i.e. it is possible to differentiate for example arithmetic and logical word commands from arithmetic and logical byte commands.

Figure 1 also schematically illustrates the manner in which such a micro-command is to be processed. The micro-command, which like all other micro-commands is read out from the recordable micro-programme store WCM and is made available in the micro-command register MBR, is recognised as a double micro-command during the decoding in the decoding unit DEC on account of its group characteristic GR. Then only its bit positions 8 to 16 are analysed in the following processing cycle, i.e. the first main function is processed. Then the remaining bit positions 17 to 31, which previously were not analysed, are displaced to the position of the first main function (bit positions 2 to 16) in the micro-command register MBR, as schematically indicated in Figure 1 by a broken line. The second main function can then be processed at the correct position in the micro-command register MBR in the next machine cycle, immediately afterwards without a new store access, and does not require a special decoder logic. Therefore the circuitry outlay for the processing of double microcommands is particularly low.

The associated processing time flow is shown in Figure 5, in which references are the same as in Figure 2. Now, in contrast to the representation in Figure 2, between the processing of two main functions in a double micro-command only a short gap 4' occurs between two machine cycles 1. This gap is negligible in comparison to the long waiting time 4 of the processing unit VE in the processing of normal micro-commands, so that the average waiting time of the processor in the processing of a sequence of micro-commands is reduced.

Such sequences can be extended in the course of a micro-programme by attempting to displace sub-functions required in this programme sequence to the end or the beginning of this sequence. If one deliber ately endeavours to use double microcommands then, as found in practice, it is often possible to develop an entire sequence of such commands.

WHAT WE CLAIM IS: 1. A microprogrammable computer system comprising a processor and a control unit with a read/write microprogramme store, in which can be stored microprogram me commands comprising a plurality of bit pattern sections, the control unit having a command register into which, during the flow of a microprogramme, microcommands are consecutively transferred from the microprogramme store and a decoder which, in use, decodes the microcommand in the command register to produce control signals for control of the processor, the control unit being arranged, in operation, so that for a single microcommand in which said plurality of bit pattern sections define a main function and at least one subsidiary function the decoder decodes the command to produce control signals which control, in parallel, elementary processing operations, determined by the main function and subfunction(s), of a single cycle of the processing unit, and for double microcommands in which said plurality of bit groups define a first main function and a second main function the double microcommand is identified as such and the decoder decodes the two functions consecutively to control two consecutive cycles of the processing unit.

2. A computer system as claimed in claim 1, wherein each micro-command word comprises a bit pattern section for a group characteristic differentiating between various groups of micro-commands, and wherein a main function bit pattern section comprises a function section and two address sections for micro-command operands which function and address sections together occupy less than half the remaining micro-command format.

3. A computer system as claimed in claim 2, wherein, in operation: each double micro-command having been made available in the micro-command register, is identified on the basis of its group characteristics; in a first processing cycle only those bit pattern sections associated with the first main function are decoded, the first main function is executed in the processing unit using the control signals derived from those bit pattern sections, and the bit patterns of the first main function in the microcommand register are replaced by those of the second main function without a new access to the micro-programme store by reloading the micro-command register; and in a second processing cycle the reloaded part of the double micro-command is decoded and processed.

4. A micro-programmable computer system substantially as herein described with reference to the accompanying drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. main functions and facilitates a differentiation between two groups of double microcommands, i.e. it is possible to differentiate for example arithmetic and logical word commands from arithmetic and logical byte commands. Figure 1 also schematically illustrates the manner in which such a micro-command is to be processed. The micro-command, which like all other micro-commands is read out from the recordable micro-programme store WCM and is made available in the micro-command register MBR, is recognised as a double micro-command during the decoding in the decoding unit DEC on account of its group characteristic GR. Then only its bit positions 8 to 16 are analysed in the following processing cycle, i.e. the first main function is processed. Then the remaining bit positions 17 to 31, which previously were not analysed, are displaced to the position of the first main function (bit positions 2 to 16) in the micro-command register MBR, as schematically indicated in Figure 1 by a broken line. The second main function can then be processed at the correct position in the micro-command register MBR in the next machine cycle, immediately afterwards without a new store access, and does not require a special decoder logic. Therefore the circuitry outlay for the processing of double microcommands is particularly low. The associated processing time flow is shown in Figure 5, in which references are the same as in Figure 2. Now, in contrast to the representation in Figure 2, between the processing of two main functions in a double micro-command only a short gap 4' occurs between two machine cycles 1. This gap is negligible in comparison to the long waiting time 4 of the processing unit VE in the processing of normal micro-commands, so that the average waiting time of the processor in the processing of a sequence of micro-commands is reduced. Such sequences can be extended in the course of a micro-programme by attempting to displace sub-functions required in this programme sequence to the end or the beginning of this sequence. If one deliber ately endeavours to use double microcommands then, as found in practice, it is often possible to develop an entire sequence of such commands. WHAT WE CLAIM IS:

1. A microprogrammable computer system comprising a processor and a control unit with a read/write microprogramme store, in which can be stored microprogram me commands comprising a plurality of bit pattern sections, the control unit having a command register into which, during the flow of a microprogramme, microcommands are consecutively transferred from the microprogramme store and a decoder which, in use, decodes the microcommand in the command register to produce control signals for control of the processor, the control unit being arranged, in operation, so that for a single microcommand in which said plurality of bit pattern sections define a main function and at least one subsidiary function the decoder decodes the command to produce control signals which control, in parallel, elementary processing operations, determined by the main function and subfunction(s), of a single cycle of the processing unit, and for double microcommands in which said plurality of bit groups define a first main function and a second main function the double microcommand is identified as such and the decoder decodes the two functions consecutively to control two consecutive cycles of the processing unit.