GB1563913A - Method of making schottky-barrier gallium arsenide field effect devices - Google Patents
Method of making schottky-barrier gallium arsenide field effect devices Download PDFInfo
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- GB1563913A GB1563913A GB4897976A GB4897976A GB1563913A GB 1563913 A GB1563913 A GB 1563913A GB 4897976 A GB4897976 A GB 4897976A GB 4897976 A GB4897976 A GB 4897976A GB 1563913 A GB1563913 A GB 1563913A
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 title claims description 33
- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims description 33
- 230000005669 field effect Effects 0.000 title claims description 30
- 238000004519 manufacturing process Methods 0.000 title description 5
- 229910052751 metal Inorganic materials 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 31
- 239000004065 semiconductor Substances 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 230000002829 reductive effect Effects 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 229910052681 coesite Inorganic materials 0.000 claims description 5
- 229910052906 cristobalite Inorganic materials 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 229910052682 stishovite Inorganic materials 0.000 claims description 5
- 229910052905 tridymite Inorganic materials 0.000 claims description 5
- 239000011651 chromium Substances 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 4
- 150000002739 metals Chemical class 0.000 claims description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 2
- 229910017401 Au—Ge Inorganic materials 0.000 claims description 2
- 238000005275 alloying Methods 0.000 claims description 2
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 claims description 2
- 239000006023 eutectic alloy Substances 0.000 claims description 2
- 230000008020 evaporation Effects 0.000 claims description 2
- 238000001704 evaporation Methods 0.000 claims description 2
- 235000015250 liver sausages Nutrition 0.000 claims description 2
- 230000000873 masking effect Effects 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims 4
- 239000013078 crystal Substances 0.000 claims 1
- 230000037230 mobility Effects 0.000 claims 1
- 239000005864 Sulphur Substances 0.000 description 7
- -1 sulphur ions Chemical class 0.000 description 3
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000004943 liquid phase epitaxy Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
- H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
- H01L29/66863—Lateral single gate transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
- H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
- H01L29/8128—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate with recessed gate
Description
(54) METHOD OF MAKING IMPROVED SCHOTTKY-BARRIER
GALLIUM ARSENIDE FIELD EFFECT DEVICES
(71) We, HUGHES AIRCRAFT
COMPANY a Company organised and existing under the laws of the State of
Delaware, United States of America, and having a principal place of business at
Centinela and Teale Street, Culver City,
State of California, United States of
America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be described in and by the following statement:- This invention relates to field effect devices and a process for making same.
More specifically it relates to a gallium arsenide field effect transistor having a selfaligned Schottky-barrier electrode gate region and to a method of making the same.
Field effect transistors have been known for many years and have been used extensively in many applications requiring among other things high input impedance.
low input capacitance high radiation tolerance and bilateral symmetry. Gallium arsenide field effect transistors are preferred over their silicon counterparts in certain high frequency operations because of their low noise and high power capabilities. One of the difficulties in processing gallium arsenide field effect transistors has been in making a reliable
insulator on a gallium arsenide substrate.
This problem has been by-passed by using
Schottky-barrier gates to replace the
insulated gates.
One important electrical parameter of a field effect transistor is its
transconductance. Transconductance is the
change of drain current caused by a change
in the gate voltage. The external
transconductance of a field effect transistor
is increased as the ohmic resistance between
the source and gate of the transistor is
reduced. Another important device
parameter adversely effecting the power
gain of a field effect transistor is the drain
to-gate capacitance. The drain-to-gate capacitance should be as low as possible since it serves as a reverse feedback path for the output signal, and thus tends to reduce the power gain of the device. Both sourceto-gate resistance and drain-to-gate capacitance are directly related to the geometric distances between the three regions of the transistor. To reduce the source-to-gate resistance and thus increase the transistor's transconductance, it is necessary to reduce the physical distance between the two regions. However, as this distance decreases, so does the breakdown voltage between them and this can become a limiting factor in the operation of the transistor. Therefore, it is important to have a process that can produce devices having the distances between the different regions kept within close tolerances.
One well-known gallium arsenide
Schottky-barrier gate field effect transistor is described by Mr. S. M. Sze in "Physics of
Semiconductor Devices", John Wiley, 1969.
at page 410. Such devices are often constructed by growing an N-type gallium arsenide epitaxial layer on a semi-insulating gallium arsenide substrate. The source, gate and drain regions are formed on the epitaxial layer. The Schottky-barrier gate is usually made out of aluminum and is 1 um to 3 tzm long. The distance between gate and source is approximately equal to the distance between gate and drain and is approximately equal to the gate length. that is about I um. The source and drain ohmic contacts are usually made of silvergermanium or gold germanium alloys.
Other more recent prior art devices have eliminated the need to grow the epitaxial layer and instead make use of ion implantation to form the different transistor regions. U.S. Patent No. 3,912,546, which is assigned to the present assignee, describes a process for the fabrication of a GaAs
Schottky-barrier gate field effect transistor, wherein initially a Schottky gate is formed over a section of the field effect transistor channel, and thereafter the gate metal is exposed to a bombardment of protons with sufficient energy to penetrate the metal and enter the field effect transistor channel region, thereby determining the conductivity of the channel.
U.S. Patent No. 3,914,784, which is also assigned to the present assignee, describes certain GaAs field effect transistors wherein the active regions of the devices are formed by implanting suitable ions directly into a semi-insulating substrate.
All above-mentioned prior art devices have satisfactory performance up to a certain frequency level. To achieve an even higher frequency performance for GaAs field effect transistors there is a need for device geometries, and reproducible processes for making them, wherein some device regions can be made closer to each other and wherein the conductivity and thickness of the device channel can be more effectively controlled.
The present invention provides a method of forming a gallium arsenide Schottkybarrier gate field effect transistor including the steps;
forming a semiconductor region on a semi-insulating gallium arsenide substrate;
defining source and drain regions on said semiconductor region whereby a channel region is defined therebetween;
providing source and drain ohmic contacts on said source and drain regions;
forming a photoresist mask on said semiconductor region with an aperture for establishing a Schottky-barrier electrode gate region between said source and drain ohmic contacts;
etching, at a controlled rate, said semiconductor region through said aperture to establish a cavity therein, said cavity having walls which are spaced by a floor, said walls sloping outwardly in a direction from said floor to the opening of said cavity, which opening is wider, between said walls, than said mask aperture, whereby a portion of the channel region having a reduced thickness remains beneath said cavity floor; and
forming a gate electrode, through said mask aperture, on said cavity floor and over said portion of reduced thickness so that the walls of said gate electrode extend, at their base, over said cavity floor but so that they also extend from said cavity floor towards said cavity opening without touching said cavity walls.
By carrying out the latter method, a field effect transistor is produced having a relatively shallow or thin portion between the two relatively thicker portions of the channel. The ohmic contacts are formed on the source and drain regions and the
Schottky-barrier is formed in the relatively thin portion of the channel which forms the gate region of the transistor. The photoresist masks through which selective chemical etching can be carried out also defines the gate metal dimension and controls the size of the gate and its proximity to the source and drain regions formed on the two unetched portions of the channel region.
The etching is carried out at a controlled rate so as to produce a relatively thin channel portion with the desired thickness and doping profile for the required transconductance of the transistor. The conductivity and thickness of the gate region, or the intrinsic channel as this gate region is often referred to, can easily be monitored and allowed to vary in accordance with the ultimate use of the transistor.
As the source-gate region is thicker and has a lower resistance than the channel region, the source resistance is lowered without moving the gate closer to the source. This makes the transistor capable of operating at higher frequencies and with a higher signal-to-noise ratio than its prior art counterparts. Lower noise results from lowering the source resistance. Similarly, the drain region can be placed somewhat further from the gate region to reduce the output capacitance and further increase the power gain of the transistor. This variation, of course, can be made only for some transistors where bidirectionality is not as important as power gain.
An embodiment of the invention will now be described with reference to Figs. 2a-2f of the accompanying drawings, in which drawings:
Fig. I is a diagrammatic cross-sectional view of a prior art Schottky-barrier gate field effect transistor;
Figs. 2a through 2f illustrate, in a series of schematic cross-sectional views, a sequence of some of the most important process steps utilized in fabricating a Schottky-barrier gate field effect transistor in accordance with the present invention.
Referring now to Fig. 1, there is shown one prior art gallium arsenide Schottkybarrier gate field effect transistor generally designated 8. The structure includes a semiinsulating gallium arsenide substrate 10, and an N-type gallium arsenide epitaxial layer 12. The device also includes on the epitaxial layer ohmic contacts 14 and 18 for the source and drain contacts, respectively, and metal-semiconductor Schottky-barrier 16, for the gate of the transistor. Field effect transistor with this structure have a frequency cutoff point lower than that of the present invention. This is primarily due to the higher feedback resistance caused by the generally larger physical distances separating the source and gate regions. The self-aligned gate process introduced by the present invention makes possible the reproducible fabrication of field effect transistors with gate regions closer to the source regions and lower source-gate or feedback resistances.
Referring now to Figs. 2, there is shown in
Fig. 2a a substrate 26 of semi-insulating gallium arsenide material. It is a polished wafer doped with chromium (Cr) and having a < 100 > crystallographic orientation. Its resistivity is typically on the order of 10B- 108 ohm-centimeters. On substrate 26 a semiconducting region 28 is formed through ion implantation or epitaxial deposition or a combination of the two, that is, after forming an epitaxial layer, then the conductivity of that layer can be further increased by implanting it with suitable ions, such as sulphur. Fig. 2b illustrates a semiconducting region 28, formed on substrate 26. If the choice is to form region 28 through an epitaxial deposition, then on the chromium doped gallium arsenide substrate 26 an epitaxial layer 28 is formed, by either vapor phase or liquid phase epitaxy, to a thickness in the range of 0.3 ,um to 1.0 m and a carrier concentration of about 1017/cm3. To maintain a good process yield it is preferred that the thickness of this layer be kept uniform to a degree consistent with the tolerance on device pinch-off voltage. Typically the required tolerance is between +500 A. The more uniform the thickness is, the more uniform the pinch-off voltage of the resulting devices will be.
Local thickness variations, or hillocks, should be minimized to permit intimate contact of mask and wafer surface during subsequent contact photolithography. Such hillocks should not exceed a few tenths of 1 ,am in height above the surrounding surface.
The typical epitaxial layer is gallium arsenide; however, other semiconductor materials such as InxGa1~xAs, with x being some hundredths to tenths, may be used for that purpose.
Alternatively, ion implantation may be used for the formation of the semiconducting region 28. The chromiumdoped, < 100 > crystallographically oriented
GaAs substrate 26, may be implanted with sulphur. The exact dose/energy is determined by the desired device parameters. It may be varied to slightly adjust parameters of the device such as the variation of transconductance as a function of gate bias. For example, microwave sample devices have been built with a pinchoff voltage of a few volts, by implanting the substrate with 6x10'2 sulphur atoms/cm3 at
140 kev, followed by a second ion implantation of l.5x1012 sulphur atoms/cm3 at 50 kev. Following ion implantation the substrate surface is coated with a layer of
SiO2 that may be formed by pyrolysis of silane with oxygen at about 425"C. The SiO2 layer prevents disassociation of the GaAs and out diffusion of the sulphur ions during a subsequent annealing step. Then the wafer must be annealed in a reducing ambient such as flowing forming gas (i.e. 900 N2:10 " H2) for approximately 20 minutes at 800"C. This annealing step serves to electrically activate the implanted sulphur ions and to remove by annealing the lattice defects caused by implantation that would otherwise reduce the carrier mobility in the wafer. The SiO2 layer is then removed using an HF etching solution. Depending on the doping parameters of the substrate, the resulting N-type doped layer exhibits a sheet resistivity in the neighbourhood of 500 ohms per square and a Hall carrier mobility of about 3,500 cm2/V-sec. The exact electrical parameters vary with the quality of the substrate, the implantation dose and energy, and the annealing time and temperature.
A third alternative would be to form the semiconducting region 28 by first forming an N-type epitaxial layer and then implanting it with sulphur ions or other suitable N-type ions at controlled doses and depths.
The next step is to form a photoresist mask on the top of the semiconducting region 28. The structure is then subjected to a suitable GaAs etchant, such as, for example, 73:22:5 parts per volume of H2O:NH4:30%" H2O2, and this removes an annular outer portion of the semiconducting region 28 and part of the substrate under the channel, leaving a mesa-like island region 30 as shown in Fig. 2c. The mesa height is made 0.3 ,um to 0.5 ,um greater than the thickness of the doped region in order to insure that parts of the etched surface exhibit properties characteristic of the underlying substrate. Although not indispensable for the performance of this device, the quality of the mesa step coverage by the metallization is improved if the step over which the gate pad connector is formed is oriented parallel to the < 011 > crystallographic orientation on the (100) surface. Thereby the orientation dependance of the common GaAs etchants is used to advantage in producing the smallest angle 0 (see Fig. 2c). For the etching solution referred to above, this angle will be approximately 540. After etching, the photoresist material is removed, and a second photoresist mask is formed on the exposed surface for the source and drain ohmic contacts. Using a standard metallization technique, appropriate ohmic contacts 32 and 33, as illustrated in Fig. 2d, are formed on the desired source and drain regions respectively, whereby a channel region is defined by the semiconductor region 28. A suitable metallization is 1,000 A of a Au-Ge eutectic alloy followed by 500 A of Ni. The metal pattern produced is heated to about 4500C for a time period ranging between 30 seconds and several minutes in order to produce an improved ohmic metalsemiconductor contact. The timetemperature cycle may be adjusted to yield the lowest contact resistance between the metal and the doped channel. It is desirable to keep this resistance below 5x 10-5 Q-cm2.
During the alloying cycle the metal tends to develop rectangular pits in the (100) surface of the mesa with the longer sides in the < 011 > direction. These pits tend to grow most rapidly by propagation in that same < 011 > direction. Using the mesa orientation prescribed above. the orientation of these etch pits is such that their growth is constrained in the < 011 > direction and the edge acuity of the source to drain opening (described below) is preserved.
A new photoresist masking pattern 34 is formed on the structure as shown in Fig. 2e.
The width of the opening 36 controls the length of the gate metal to be formed at a later stage. This width of opening 36 is typically in the range between 1 ,um and 2 ,um. The exposed portion of the semiconducting region or channel 28, at 36, is etched to a predetermined depth using a wet chemical etch such as 970 mil H2O:20 mil NH4OH:7 mil 300/n H2O2. The depth of the etched window is determined by the pinch-off voltage desired for the device.
This provides a shallow N-type semiconducting portion 38 referred to as an intrinsic channel. When the doping of the channel layer is uniform, the intrinsic channel 38 thickness is related to the pinchoff voltage V, by where
q=electronic charge=1.6x 10'9 coulombs
N=channel doping density in atoms/cm3
t=thickness of the intrinsic channel 38 (in
centimeters)
k=relative dielectric constant EO=permittivity of free space barrier height of the gate metal-to
semiconductor contact o"'.8 V to .9 V for most metals in GaAs.
Achieving the proper depth of etch depends on an accurate knowledge of the initial channel layer thickness and the etch rate. The length 40 of the intrinsic channel 38 depends on the gate mask window 36 and again on the etch rate. It is usually somewhat greater than the gate mask window. Typically, if the gate opening 36 is
I vm, then the lenght 40 of the intrinsic channel 38 is in the range of 1.1 ,um to 1.5 !lem. Without removing the photoresist material, a Schottky-barrier gate metal is formed through the evaporation of a metal on the intrinsic channel. Since the same mask is used for both. etching to form the intrinsic channel and for defining the pate metal length, the gate metal contact is constrained to the intrinsic channel area.
The length of the gate is closely controlled and also its proximity to the source and gate regions is controlled. Aluminum is usually used to form the gate metal, but any other metal or combination of metals used for prior art Schottky gate field effect transistors may also be used with this invention. After the Schottkybarrier formation, the photoresist
is dissolved and washed away, carrying the
excess gate metal with it. Then conductors
are attached to the metallic contacts of the
source, gate and drain regions. The resulting
structure is illustrated in Fig. 2f. Referring
now to Fig. 2f, it contains source region 50, source ohmic contact 32, Schottky-barrier
gate metal 52. intrinsic channel 38, a drain
region 54 and drain ohmic contact 33.
By analogy a P-type Schottky-barrier gate
field effect may be constructed by using a P
type conducting channel.
Various etchants can be used to control
the channel geometry and thickness of the
devices fabricated. and, if desired, the final
device structure of Fig. 2f can be passivated
using either sputter deposited SiO2 or vapor
deposited polycrystalline gallium arsenide
(PGA).
WHAT WE CLAIM IS:
1. A method of forming a gallium arsenide
Schottky-barrier gate field effect transistor
including the steps:
forming a semiconductor region on a
semi-insulating gallium arsenide substrate:
defining source and drain regions on said semiconductor region whereby a channel
region is defined therebetween:
providing source and drain ohmic
contacts on said source and drain regions:
forming a photoresist mask on said semiconductor region with an aperture for
establishing a Schottky-barrier electrode gate region between said source and drain ohmic contacts:
etching, at a controlled rate. said semiconductor region through said aperture to establish a cavity therein, said cavity having walls which are spaced by a floor, said walls sloping outwardly in a direction from said floor to the opening of said cavity, which opening is wider, between said walls.
than said mask aperture. whereby a portion of the channel region having a reduced thickness remains beneath said cavity floor: and
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (9)
1. A method of forming a gallium arsenide
Schottky-barrier gate field effect transistor
including the steps:
forming a semiconductor region on a
semi-insulating gallium arsenide substrate:
defining source and drain regions on said semiconductor region whereby a channel
region is defined therebetween:
providing source and drain ohmic
contacts on said source and drain regions:
forming a photoresist mask on said semiconductor region with an aperture for
establishing a Schottky-barrier electrode gate region between said source and drain ohmic contacts:
etching, at a controlled rate. said semiconductor region through said aperture to establish a cavity therein, said cavity having walls which are spaced by a floor, said walls sloping outwardly in a direction from said floor to the opening of said cavity, which opening is wider, between said walls.
than said mask aperture. whereby a portion of the channel region having a reduced thickness remains beneath said cavity floor: and
forming a gate electrode, through said mask aperture, on said cavity floor and over said portion of reduced thickness so that the walls of said gate electrode extend, at their base, over said cavity floor but so that they also extend from said cavity floor towards said cavity opening without touching said cavity walls.
2. A method according to claim 1, wherein said semiconductor region is formed by growing a thin epitaxial active layer on said substrate.
3. A method according to claim wherein said semiconductor region is formed by implanting an impurity into said substrate.
4. A method according to claim 1, wherein said semiconductor region is formed by growing a thin epitaxial active layer on said substrate and then implanting said epitaxial active layer with ions at controlled depth and dosage.
5. A method according to any one of the preceding claims wherein the gallium arsenide substrate has a bulk resistivity between 108 and 106 ohm-centimeters and has a chromium as a dominant electrically active impurity, and wherein said semiconductor region is formed by growing an N-type epitaxial layer on said substrate, said layer having a carrier concentration of the order of 1017/cm3; implanting an N-type impurity in said epitaxial layer thereby increasing the conductivity of said layer; forming a diffusion barrier layer on the surface of said N-type epitaxial layer subsequent to the N-type implantation thereof whereby the stoichiometry of the surface is preserved; and annealing at a predetermined elevated temperature sufficient to electrically activate ions of said
N-type impurity implanted in said layer and to anneal out substantial amounts of ion implantation damage, whereby carrier mobilities in excess of 3,000 cm2/volt-second are obtained in a layer of substantially uniform thickness.
6. A method according to any of the preceding claims wherein an annular portion of said semiconductor region is removed by etching to provide an insulating mesa-like portion of said substrate on which said source and drain ohmic contacts are formed.
7. A method according to any one of the preceding claims wherein said etching, to establish said cavity is of a (100) crystal plane in the < oTi > direction.
8. A method according to any one of the preceding claims wherein said portion of reduced thickness is closer to the source region than the drain region.
9. A Schottky-barrier gate field effect transistor produced by a method according to any of the preceding claims.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US64012475A | 1975-12-12 | 1975-12-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1563913A true GB1563913A (en) | 1980-04-02 |
Family
ID=24566939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB4897976A Expired GB1563913A (en) | 1975-12-12 | 1976-11-24 | Method of making schottky-barrier gallium arsenide field effect devices |
Country Status (2)
| Country | Link |
|---|---|
| FR (1) | FR2335041A1 (en) |
| GB (1) | GB1563913A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2133621A (en) * | 1983-01-11 | 1984-07-25 | Emi Ltd | Junction field effect transistor |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1131450B (en) * | 1980-05-07 | 1986-06-25 | Cise Spa | PROCEDURE FOR THE PRODUCTION OF MICROWAVE FIELD-EFFECT TRANSISTORS |
| FR2496982A1 (en) * | 1980-12-24 | 1982-06-25 | Labo Electronique Physique | PROCESS FOR PRODUCING FIELD EFFECT TRANSISTORS, SELF-ALIGNED GRID, AND TRANSISTORS THUS OBTAINED |
| FR2558647B1 (en) * | 1984-01-23 | 1986-05-09 | Labo Electronique Physique | SCHOTTKY-TYPE FIELD-EFFECT TRANSISTOR FOR MICROWAVE APPLICATIONS AND METHOD FOR PRODUCING SUCH A TRANSISTOR |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2104704B1 (en) * | 1970-08-07 | 1973-11-23 | Thomson Csf | |
| US3920861A (en) * | 1972-12-18 | 1975-11-18 | Rca Corp | Method of making a semiconductor device |
| US3942186A (en) * | 1973-10-09 | 1976-03-02 | Westinghouse Electric Corporation | High frequency, field-effect transistor |
| US3898353A (en) * | 1974-10-03 | 1975-08-05 | Us Army | Self aligned drain and gate field effect transistor |
-
1976
- 1976-11-24 GB GB4897976A patent/GB1563913A/en not_active Expired
- 1976-12-10 FR FR7637401A patent/FR2335041A1/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2133621A (en) * | 1983-01-11 | 1984-07-25 | Emi Ltd | Junction field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2335041B1 (en) | 1980-08-14 |
| FR2335041A1 (en) | 1977-07-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19921124 |