GB1560069A

GB1560069A - Current detecting circuits

Info

Publication number: GB1560069A
Application number: GB1667478A
Authority: GB
Original assignee: Communications Patents Ltd
Current assignee: Communications Patents Ltd
Priority date: 1978-04-27
Filing date: 1978-04-27
Publication date: 1980-01-30

Description

(54) CURRENT DETECTING CIRCUITS (71) We, COMMUNICATIONS PATENTS LIMITED, a British Company of Carlton House, Lower Regent Street, London SWlY 4LS, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- The present invention relates to current detecting circuits and in particular to circuits for detecting simultaneous conduction of two semi-conductor switches in a switching system in which the switches are arranged to provide current from a common D.C. source to a common load alternately.

A simple D.C. to A.C. converter is known in which at least one pair of semiconductor switches is connected across a D.C. supply with the switches in series. The switches are turned on and off in sequence to produce a rectangular voltage waveform from the D.C. source. When one switch is in its conductive state, the other is in its non-conductive state, and vice-versa. It is essential that the two switches are not simultaneously fully conductive, as if they were a short circuit path would be formed across the D.C. source.

Semi-conductor switches are generally controlled by a square-wave which provides alternate "on" and "off" commands. The response to "on" and/or "off" commands is however not instantaneous. For example, if the switches are transistors, there is exhibited a delay time, td, between an "on" command and the initiation of the main current through the transistor. Likewise there is a storage time, ts, between an "off" command and the interruption of the main current. The storage time ts is usually appreciably longer than the delay time td and is a variable both between transistors of the same nominal type, and as a function of main current and operating temperature.

It is known to incorporate a delay interval in the respective control waveforms whereby the "on" command to one switch is delayed by a fixed interval from the "off" command to the previously conducting switch, the fixed delay being greater than or equal to ts - td. This technique is satisfactory in a situation where the predicted maximum storage time ts and the predicted variations in storage time are short compared with the "on" period of the switch. A typical application of this kind is an inverter circuit operating at 20kHz with a constant load and employing transistors with storage times of 1S which are short compared with the half-period of 25,uS.

In high frequency applications however the storage time can be comparable to the "on" period of the switch. Variations in storage time then become highly significant, and the use of a fixed delay is no longer acceptable.

Our copending application No.19662/74 (Serial No.l 519 141) describes a system comprising means for providing a delay interval between the "off" command to any one switch and the "on" command to the next switch in the sequence, means for detecting when both or at least two successive switches in the sequence conduct simultaneously, and means for increasing the duration of the delay interval when such simultaneous conduction is detected. Thus a self-adjusting delay period is obtained.

It is an object of the present invention to provide a detecting circuit which may be used to detect simultaneous conduction of two switches in a system such as that described in application No.19662/74 (Serial No.l 519 141).

According to the present invention, there is provided a circuit for detecting simultaneous conduction of two semi-conductor switches in a switching system in which the switches are connected in series across a D.C. source and are arranged to provide current from the D.C. source to a common load, comprising means for sensing current drawn from the D.C. supply through the switches, means for sensing current drawn through the load, and means for comparing the sensed currents to detect differences between them, which differences are representative of simultaneous conduction.

Preferably the current sensing means comprise current transformers.

The output from the load current sensing means may be full wave rectified and the rectified output and the output of the supply current sensing means may be subtracted one from the other, the residual signal being applied to a control terminal of a transistor, which transistor provides an output representative of simultaneous conduction. The transistor may be arranged to modify a reference potential provided by a potentiometer.

An embodiment of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a schematic block diagram of an AM transmitter embodying the present invention; Figures 2 and 3 illustrate waveforms appearing in the transmitter of Figure 1; Figure 4 illustrates circuit details of switching control signal generating circuitry; Figure illustrates an output driver stage; Figure 6 illustrates a bridge configuration output stage; and Figure 7 illustrates a simultaneous conduction detector.

Figure 1 is a schematic diagram of an RF transmitter comprising an audio modulator 1 providing a pulse width modulated audio input 2 to a main HT modulator 3. An auxiliary modulator 4 is also provided. The main modulator 3 provides an HT output modulated by the pulse width modulated input 2 to transistor switches 5, 6 via a current detecting circuit 7 the purpose of which is described below. The switch 5 is connected in series with a further switch 8, and the switch 6 is connected in series with a further switch 9. The switches 5, 6, 8 and 9 thus form a power amplifier of bridge form.

If switches 5 and 9 are turned on and switches 6 and 8 are turned off, current is drawn from the output of modulator 3 to earth via switch 5, a load 10, a further current detecting circuit 11 and switch 9. If switches 6 and 8 are turned on and switches 5 and 9 are turned off, current is drawn from the output of modulator 3 to earth via switch 6, circuit 11, load 10 and switch 8, ie. the direction of current flow is reversed.

As the output of modulator 3 operates essentially as an AM voltage source the amplitude of which is representative of the audio input, the output load (ie. an aerial) transmits an AM modulated signal at a frequency controlled by the switching frequency of the switches 5, 6, 8 and 9.

The switches 5, 6, 8 and 9 are operated at an r.f. frequency determined by a switching signal generator which provides an r.f.

square wave output A as shown in Figure 2A. The output A is doubled in frequency by unit 13 to provide output B (Figure ZB) which is applied to a pulse generator in the form of a monostable multivibrator 14. The multivibrator 14 provides an output C (Figure 2C) to a logic circuit 15 which also receives input A (Figure 2A) from source 12, the mark space ratio of the pulses of output C being dependent upon input 16 to the multivibrator 14 as will be described hereinafter. The signal A( Figure 2A) applied to the logic circuit 15 acts as a synchronising signal to ensure that, in a transmitter which includes many modules of the type illustrated operating in parallel, all of the modules operate in phase.

The logic circuit 15 provides outputs D (Figure 2D) and E (Figure 2E) to respective driver stages 17 and 18 for the switches 5, 6, 8 and 9, each of the outputs D and E comprising portions at logic "0" which correspond to periods during which it is desired to turn on the switches controlled by the respective drivers 17 and 18. The drivers 17, 18 receive an auxiliary modulation input from modulator 4. The drivers 17, 18 amplify the logic level pulses at the output of logic circuit 15 to a level sufficient to drive the switches 5, 6, 8 and 9. It will be seen that there is a delay period of length tm between the turning off of one set of switches and the turning on of the other set.

This is to compensate for the combined effects of the delay time between an command to a switch and the initiation of main current through the transistor and the storage time between an "off" command and the interruption of the main current.

The length of the delay period tm is controlled by the input 16 to the multivibrator 14. The input 16 is in turn controlled by a simultaneous conduction detection circuit 19 which receives inputs from detection circuits 7 and 11.

The detection circuit 7 provides an input waveform 20 to circuit 19 which is representative of the combined collector currents of the switches 5, 6, 8 and 9. Ideally this is a cusp waveform (Figure 3A), but in the event of simultaneous conduction of switches 5 and 8 or 6 and 9 the cusp waveform is modified by the addition of narrow spikes at the switching transitions (Figure 3B).

The detection circuit 11 provides an input waveform 21 to the circuit 19 which is rep resentative of the load current. The waveform 21 is full wave rectified to provide a true cusp waveform which is not influenced by simultaneous conduction and does not contain any spikes as these do not appear in the load current. The spikes cannot appear in the load current in any event as the load is resonant.

The circuit 19 subtracts its rectified input 21 from its input 20. The result of this subtraction is zero if there is no simultaneous conduction in the switches and in such circumstances the input 16 to the multivibrator 14 is held at a reference level determined by a voltage source 22. If there is simultaneous conduction however the result of the subtraction is not zero and the input 16 is modified accordingly to increase the width of the pulses (Figure 2C) provided by the multivibrator. Thus the delay tm between the application of "on" command pulses to the switches is increased to automatically adjust the condition of the circuitry to stop the simultaneous conduction.

The voltage source 22 also limits the maximum pulse width of the multivibrator output to prevent the pulse width exceeding one half-cycle of the carrier frequency determined by signal A (Figure 2A).

Referring now to Figure 4, details of components 14 and 15 of Figure 1 are shown. The multivibrator 14 and logic circuit 15 receive inputs A and B via identical pulse shaping circuits 23. The multivibrator is controlled by input 16 via transistor 24.

The logic circuit 15 comprises three NAND gates as shown providing outputs D and E in known manner.

Figure 5 shows details of the driver 17 of Figure 1. Forward and reverse base drive is provided to the power switches 5, 6, 8 and 9 (Figure 1) by a pair of identical half-bridge switching stages employing VMOS field effect transistors (FETs) 25, 26. Each of the FETs 25, 26 is capable of switching for example two amps in typically 5nS. There is a separate coupling transformer 27, 28 coupling the driver to each of the output power switches via terminals 29, 30. Each half-bridge driver feeds the two coupling transformers 27, 28 in parallel. The transformers 27, 28 have a ratio of 2:1 voltage step down, and employ double bifilar windings to minimise leakage inductance.

The FETs 25, 26 conduct by majority carriers and therefore there is no storage time, and hence no possibility of simultaneous conduction if they are driven by straight forward antiphase gate signals. This is a major advantage, and allows very simple gate drive circuitry.

The FETs 25, 26 are of the normally off enhancement mode N-channel type, and require for example + 10 volts gate-tosource voltage to turn them on fully. Thus the gate voltage of the upper transistor 25 of the half-bridge needs to be driven above the drain supply rail by 10 volts. This is achieved by exploiting the very high gate resistance of the FET.

The circuit operates in the following way.

Assume a logic low (0V) input at terminal 31. Transistor 32 is off, transistor 33 is on.

As a result, a positive is transmitted via coupling capacitors 34, 35 to drive the gates of transistors 36 and 26 positive so that these transistors are on. Transistor 26 supplies the load current, turning on tbe appropriate switch in the power amplifier bridge. Transistor 36 activates a current path via diode 37, resistor 38 to turn on a current source transistor 39. The collector current of transistor 39 flows in the path inductor 40, diode 41, transistor 36 (drainsource). Transition to low voltage at the drain of transistor 36, being coupled via capacitor 42 to the gate of transistor 25, holds that transistor off. Energy stored in inductor 40 is proportional to the current attained at the end of the on period of transistor 36. At the end of this period terminal 31 goes to logic high, and consequently transistors 36 and 26 are turned off.Diode 37 turns off, transistor 39 "hangs on" due to the charge on capacitor 43. Current from inductor 40 continues, and the stored energy is transferred into the combined capacitance of capacitor 42 and the input capacitance of transistor 25. The voltage at the gate of transistor 25 rises as a near-quarter sinewave transition at the resonant frequency of inductor 40 and the total capacitance, until clamped by the diodes 44 and 45. Capacitor 42 acquires a small charge as a result of the left to right current flow. The gate of transistor 25 is thus driven positive with respect to the maximum supply rail voltage. Since the gate resistance is very high and the leakage current low, the time constant of this resistance and the input capacitance is long compared to the on period of transistor 25. The gate therefore stays charged until transistor 25 is turned off again.Taking the lowest frequency as 500kHz, the on time of transistor 25 is a maximum of 1yes.

When the input at terminal 31 reverts to logic 0, transistor 36 turns on again, and by reason of the charge on capacitor 42, or the gate of transistor 25 goes negative until clamped by the substrate diode.

Transformer phasing is such that transistor 25 supplies the reverse suck out base current to turn off the main power switches.

Variation of the characteristics of the power switches driven from terminals 29, 30 reflects as some variation of the D.C. input impedance of the driver supply rail which is supplied by the auxiliary modulator 4 (Figure 1) via terminal 46. Capacitive elements 47, 48, 49, 50 and 51, 52, 53 and 54 form part of a low pass filter as will be described below.

Figure 6 shows details of the PA output bridge including four high power output transistors 55, 56, 57 and 58 which corre spond to the switches 5, 6, 8 and 9 of Figure 1. The switching of the output transistors is controlled by the two identical drivers 17, 18 (Figure 1), the outputs 29 and 30 (Figure 5) of driver 17 controlling transistors 55 and 58 respectively via inputs 59 and 60 and inputs 61 and 62 provided by driver 18 con trolling transistors 56 and 57 respectively.

The modulated D.C. supply provided by modulator 3 (Figure 1) is applied to two terminals of the bridge via terminal 63 and transformer 64 which corresponds to current detector 7 (Figure 1). A connection to the modulator 4 is provided via terminal 65. Current passes to the output load 66 via transformer 67 which corresponds to current detecting circuit 11 of Figure 1.

The illustrated bridge configuration is advantageous in that the audio frequency component of the modulated D.C. supply does not appear across the r.f. load.

Similarly, the impedance of the r.f. load at audio frequencies does not influence the impedance "seen" by the modulator. In addition, the r.f. ripple component in the D.C. supply is at twice carrier frequency which is advantageous in the context of the constraints upon the magnitude of the h.t.

decoupling capacitor imposed by the design of the low pass filter of which it is a part.

Outputs 68, 69, 70 and 71 are derived from the current detecting transformer 64 and 67 and applied to the simultaneous conduction detector shown in detail in Figure 7.

The combined collector current of the bridge transistors 55, 56, 57 and 58, which as described above is ideally a cusp waveform but in the event of simultaneous conduction is modified by the addition of narrow spikes at the switching transitions, is represented by the waveform appearing at terminal 71 (Figure 7). The load current is represented by the waveform appearing at terminals 68 and 70, which signals are fullwave rectified by diodes 72, 73 to provide a true cusp waveform. This waveform is not influenced by simultaneous conduction of transistor pair 55, 57 or transistor pair 56, 58 and does not contain any spikes.

The collector current and load current representative waveforms are subtracted one from the other across a resistor 74.

When there is no cross conduction there is zero potential across this resistor. In the event of simultaneous conduction only the associated current spikes appear across this resistor. These spikes are sampled by transistor 75 which has no forward bias and sc is operating in Class 'C' so requiring an in put in excess of about 600 - 700mV before al.y variation in collector current occurs.

Thus very low level spikes and noise are ignored. This transistor 75 controls the timing of the voltage controlled monostable multivibrator 14 (Figure 1) in the drive control logic.

The timing of the monostable multivibrator 14 is varied by the transistor 24 (Figure 4) which is a voltage proportional current source. The D.C. control voltage to transistor 24 is provided from the compound emitter-follower detector output stage formed by transistors 76, 77 (Figure 7). The input to this emitter follower has a preset value determined by the potentiometer 78, the voltage provided by which may be pulled down by the collector current of transistor 75 in response to the simultaneous conduction pulse input applied to its base from across resistor 74.

The extent to which this voltage can be pulled down is limited by a preset 'end stop' potentiometer 79 which limits the excursion of this voltage to a value such that the pulse provided by the monostable multivibrator does not exceed the width of one halfcycle of the particular carrier frequency.

The potentiometer 78 corresponds to the voltage source 22 of Figure 1.

WHAT WE CLAIM IS: 1. A circuit for detecting simultaneous conduction of two semi-conductor switches in a switching system in which the switches are connected in series across a D.C. source and are arranged to provide current from the D.C. source to a common load, comprising means for sensing current drawn from the D.C. supply through the switches, means for sensing current drawn through the load, and means for comparing the sensed currents to detect differences between them, which differences are representative of simultaneous conduction.

2. A circuit according to claim 2, wherein the current sensing means comprise current transformers.

3. A circuit according to claim 1 or 2, comprising means for full wave rectifying the output of the load current sensing means, means for subtracting the rectified output and the output of the supply current sensing means one from the other, and a transistor having a control terminal connected to receive the output of the subtracting means.

4. A circuit according to claim 3, wherein the full wave rectifying means comprises a pair of diodes.

5. A circuit according to claim 3 or 4, comprising an output stage having a control terminal connected to sources of reference potentials determining maximum and mini

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. (Figure 1) via terminal 46. Capacitive elements 47, 48, 49, 50 and 51, 52, 53 and 54 form part of a low pass filter as will be described below. Figure 6 shows details of the PA output bridge including four high power output transistors 55, 56, 57 and 58 which corre spond to the switches 5, 6, 8 and 9 of Figure 1. The switching of the output transistors is controlled by the two identical drivers 17, 18 (Figure 1), the outputs 29 and 30 (Figure 5) of driver 17 controlling transistors 55 and 58 respectively via inputs 59 and 60 and inputs 61 and 62 provided by driver 18 con trolling transistors 56 and 57 respectively. The modulated D.C. supply provided by modulator 3 (Figure 1) is applied to two terminals of the bridge via terminal 63 and transformer 64 which corresponds to current detector 7 (Figure 1). A connection to the modulator 4 is provided via terminal 65. Current passes to the output load 66 via transformer 67 which corresponds to current detecting circuit 11 of Figure 1. The illustrated bridge configuration is advantageous in that the audio frequency component of the modulated D.C. supply does not appear across the r.f. load. Similarly, the impedance of the r.f. load at audio frequencies does not influence the impedance "seen" by the modulator. In addition, the r.f. ripple component in the D.C. supply is at twice carrier frequency which is advantageous in the context of the constraints upon the magnitude of the h.t. decoupling capacitor imposed by the design of the low pass filter of which it is a part. Outputs 68, 69, 70 and 71 are derived from the current detecting transformer 64 and 67 and applied to the simultaneous conduction detector shown in detail in Figure 7. The combined collector current of the bridge transistors 55, 56, 57 and 58, which as described above is ideally a cusp waveform but in the event of simultaneous conduction is modified by the addition of narrow spikes at the switching transitions, is represented by the waveform appearing at terminal 71 (Figure 7). The load current is represented by the waveform appearing at terminals 68 and 70, which signals are fullwave rectified by diodes 72, 73 to provide a true cusp waveform. This waveform is not influenced by simultaneous conduction of transistor pair 55, 57 or transistor pair 56, 58 and does not contain any spikes. The collector current and load current representative waveforms are subtracted one from the other across a resistor 74. When there is no cross conduction there is zero potential across this resistor. In the event of simultaneous conduction only the associated current spikes appear across this resistor. These spikes are sampled by transistor 75 which has no forward bias and sc is operating in Class 'C' so requiring an in put in excess of about 600 - 700mV before al.y variation in collector current occurs. Thus very low level spikes and noise are ignored. This transistor 75 controls the timing of the voltage controlled monostable multivibrator 14 (Figure 1) in the drive control logic. The timing of the monostable multivibrator 14 is varied by the transistor 24 (Figure 4) which is a voltage proportional current source. The D.C. control voltage to transistor 24 is provided from the compound emitter-follower detector output stage formed by transistors 76, 77 (Figure 7). The input to this emitter follower has a preset value determined by the potentiometer 78, the voltage provided by which may be pulled down by the collector current of transistor 75 in response to the simultaneous conduction pulse input applied to its base from across resistor 74. The extent to which this voltage can be pulled down is limited by a preset 'end stop' potentiometer 79 which limits the excursion of this voltage to a value such that the pulse provided by the monostable multivibrator does not exceed the width of one halfcycle of the particular carrier frequency. The potentiometer 78 corresponds to the voltage source 22 of Figure 1. WHAT WE CLAIM IS:

1. A circuit for detecting simultaneous conduction of two semi-conductor switches in a switching system in which the switches are connected in series across a D.C. source and are arranged to provide current from the D.C. source to a common load, comprising means for sensing current drawn from the D.C. supply through the switches, means for sensing current drawn through the load, and means for comparing the sensed currents to detect differences between them, which differences are representative of simultaneous conduction.

mum outputs for the output stage, the output of said transistor being connected to the control terminal so as to control the output stage between the said maximum and minimum outputs.

6. A circuit for detecting simultaneous conduction of two semi-conductor switches in a switching system in which the switches are connected in series across a D.C. source and are arranged to provide current from the D.C. source to a common load, the circuit being substantially as hereinbefore described with reference to the accompanying drawings.