GB1558815A - Semi conductor stress sensor - Google Patents

Description

(54) SEMI CONDUCTOR STRESS SENSOR (71) We, HONEYWELL INC., a Corporation organised and existing under the laws of the State of Delaware, United States of America of Honeywell Plaza, Minneapolis, Minnesota 55408, United States of America, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to a semiconductor stress sensor, and to a method of making it.

According to the invention, there is provided semiconductor stress sensor comprising a diaphragm portion and a constraining portion for constraining the diaphragm portions at peripheral portions thereof, said diaphragm portion being provided by a layer of semiconductor material of a first conductivity type in which a first doped region of second conductivity type is formed to serve as a piezoresistor, said diaphragm portion having a second region located between said doped region and a first surface of the diaphragm portion with a semiconductor junction separating said regions, the maximum concentration of dopant in said first region being spaced from said junction.

An embodiment of the invention will now be described by way of example only with reference to the accompanying drawings, in which: Figure 1 is a graph showing the resistance change A R versus stress S plotted for three different absolute temperatures T1 to T3 and for two different dopant concentrations MC1, MC2 of a p-type silicon piezoresistor, Figures 2A and 2B show two partial views of a semiconductor stress sensor according to the invention, Figures 3A to 3K show different -steps in the method of manufacture of the sensor of Figures 2A and 2B, and Figure 4 shows a dopant atom profile for a semiconductor stress sensor constructed by the method of Figures 3A to 3K.

Referring to Figures 2A and 2B of the drawings, the semiconductor stress sensor has a silicon layer 9 in which piezoresistors are formed by ion implantation. One portion 10 of this silicon layer serves as a constraint and support for a sensor diaphragm portion 11.

A dashed line 12 indicates approximately the boundary between the constraint portion and the diaphragm portion of the stress sensor.

Two piezoresistors 13 and 14 are provided in the silicon layer such that each has a portion in both diaphragm portion 11 and constraint portion 10. Neither piezoresistor intersects the silicon layer surface except near the ohmic contacts, 15, so both are shown by a dashed line outline. The silicon layer is of n-type conductivity silicon where shown except where the piezoresistors 13 and 14 are formed.

These piezoresistors are of p-type conductivity silicon material. Typically, two piezoresistors are used together at one stress sensing location on the diaphragm portion to provide signals to subsequent signal processing circuitry having a double signal strength and usual resistance value temperature coefficient compensation.

Piezoresistor 13 senses radial stress in the diaphragm portion 11 as can be seen by noting that most of the resistance will occur in thin arms along radii drawn from the centre of the diaphragm portion. Piezoresistor 14, on the other hand, will sense tangential stress in the diaphragm portion.

Figure 2B is a cross-sectional view of Figure 2A. The cross section is taken along section line 2B-2B.

The silicon layer 9 can be better understood from the view in Figure 2B where the silicon layer is shown designated therein by a bracket and the numeral 9. That portion of silicon layer 9 to the left of the constraint-diaphragm juncture, or boundary 12, is the constraint portion 10 of Figure 2A. That portion to the right of boundary 12 in Figure 2B is the diaphragm portion 11 of Figure 2A.

Silicon layer 9 is shown with a dashed line 16 which is used to mark approximately a boundary between a stratum 17 of layer 9 having a higher conductivity and another stratum 18 of layer 9 having a lower conductivity. The higher conductivity strata 17 of layer 9 is provided to improve results of the electrolytic etching process used in providing a recess in a substrate 19 upon which layer 9 is formed. The recess occurs to the right of boundary 12 in Figure 2B to provide the diaphragm portion of the stress sensor.

Piezoresistor 13 is shown with dashed line 20 drawn therein to indicate approximately the region of maximum dopant concentration for the dopant implanted to form the piezoresistor.

A surface protection region 21 is shown over piezoresistor 13 in the diaphragm layer portion 11 but not in the region of contact 15. Protective region 21 could be formed by diffusion, epitaxial growth or ion implantation methods.

Again, the most repeatable and accurate stress sensor results when region 21 is provided by ion implantation.

Electrical contact 15 is shown making ohmic contact to piezoresistor 13 through an electrically insulating silicon dioxide ring 22. As mentioned, the silicon dioxide 22 could be extended over silicon layer surface 23 to some thickness to protect piezoresistor 13 from elements that would otherwise come into contact with surface 23. Of course, mechanical performance of the diaphragm is constrained by such a covering of silicon dioxide, thinner layers of oxide providing a thinner constraint portion. The constraint portion may have a negligible effect where the oxide is quite thin and where other errors such as due to mechanical stress in the mounting of the substrate are relatively large.

Turning now to Figure 3, there is depicted the results of process steps performed to provide the structure shown in Figure 2. The initial process steps are shown wherein piezoresistor region 13 of Figure 2 is provided by ion implantation followed by showing the further process steps to provide region 21 of Figure 2 as an implanted region, although other methods of providing region 21, such as diffusion or epitaxial growth, could be used as discussed above. Also clearly after the implantation of piezoresistors, a silicon oxide layer could be provided on the silicon layer surface 23 over region 21 or over the piezoresistor region 13 without region 21 being present.

Figure 3A shows the result of an epitaxial growth of an n-type conductivity layer 30 upon a p+ substrate 31. Substrate 31 has a resistivity of 0.01 il-cm approximately. Layer 30 is grown such that the first stratum 32 of the layer has a resistivity of around 10 to 20 il-cm while the second stratum 33 of the layer has a resistivity of 0.50 Q-cm, the two strata 32, 33 being approximately separated by a line designated 34. The stratum 33 is grown just as the initial strata, that is, both by conventional epitaxial growth techniques, the concentration of the dopant during growth being increased during the final portion of the epitaxial layer growth. Layer 30 has an approximate total thickness of 30 yam with stratum 32 being approximately 20 corm.

As indicated in the preceding, stratum 33 aids in the etching step performed later in the process for the formation of the diaphragm portion of the semiconductor material stress sensor. Stratum 33 will approximate to some degree an equipotential layer to aid in the electrolytic etching occurring in this later step.

Also, stratum 33 provides a poor semiconductor junction injection efficiency for the semiconductor junctions resulting from the provision of piezoresistors while the stratum has a high recombination rate to thereby prevent holes from being etched in the epita- xial layer during the etching process near the piezoresistors.

Thereafter, thermal oxide is grown in a manner well known in the art on the exposed surface 35 of the epitaxial layer. The result is shown in Figure 3B where silicon dioxide has been grown thermally to approximately 12,000 A to form a masking layer 36.

Conventional photoresist techniques are used to cut a pattern in silicon dioxide layer 36 for forming the piezoresistor regions in the diaphragm portion and the piezoresistor resistive lead-outs to the constraint portion.

Following this, thermal oxide of approximately 600 A is regrown on surface 35, the layer designated by numeral 37, to serve as a scattering oxide. This scattering oxide serves as an amorphous coating over the areas selected for ion implantation, that is the piezoresistor and resistive lead-out regions, to cause some scattering of the impinging ions so they do not happen to line up with the silicon lattice in layer 30 and go much deeper than expected for a given average ion energy. Results of these steps are shown in Figure 3C.

At this point in the process, a deep boron implant is made using boron ions having an average energy of approximately 300 kev.

The ion beam is adjusted such that the dose is 5.7 .1014 ionslcm 2. The result is a maximum boron concentration of approximately 10l9 atomsjcm3 and a sheet resistivity of approximately 130 il IC1.

The result of these steps is shown in Figure 3D where a p-type region 38 has been formed below surface 35 of the silicon layer 30 and within stratum 33 of that layer. A second dashed line 39 is shown within p-type conductivity region 38 to indicate that an approximate location of the region of maximum boron concentration. This location is typically 0.7 to 0.9 pom below surface 35 while the pn junction, i.e. the semiconductor junction, defining the deepest portions of ptype conductivity region 38 below surface 35 will be located approximately 1.3 pm below surface 35.

Using these values, the final piezoresistors which will result from p-type conductivity region 38 will have dimensions so as to have about a 5,000 Q resistance value. This resistance value provides a reasonable compromise between (i) having a sufficient output signal when a given amount of stress is exerted on the diaphragm portion of the sensor in face of both the amount of noise unavoidably present and the errors introduced by the signal processing circuit while keeping the required signal processing circuit gain reasonably small, and (ii) having the current necessary to energize the stress sensor piezoresistors sufficiently low that differential heating due to current flow in the stress sensor will not cause erroneous sensor output signals. Piezoresistors having this resistance value can be of convenient dimensions in surface 35 given the resistivity values for p-type conductivity region 38 set out above. The resulting piezoresistor will be neither too long and so difficult to locate at optimum stress sensing positions in the diaphragm nor too narrow so as to create problems involving excessive resistance value tolerances due to variations in providing cuts in the mask in layer 36.

After the boron implantation, the silicon dioxide mask 36 is stripped away from the silicon layer surface 35 by the use of conventional photoresist techniques except where electrical contacts for the piezoresistors are desired. Thus, in Figure 3E, a small portion of the oxide scattering layer 37 remains on surface 35 where protected by a photoresist layer portion 40. The remaining oxide will serve as a marker for locating electrical contacts later while photoresist layer portion 40 will serve as an implantation mask for the remaining ion implantation step. Of course, if less precise and stable stress sensors are satisfactory, the following step might be a diffusion or epitaxial growth step rather than a second ion implantation step.

The second ion implantation step involves impinging phosphorous ions upon the structure shown in Figure 3E to provide a shallow phosphorous implanted region over the boron implanted region except at locations where electrical contacts are desired. The phosphorous ion implantation step takes place using phosphorous ions having an average energy of approximately 50 kev while impinging in an ion beam providing a dose of 1013 ion/cm2.

The maximum phosphorous atom concentration reached is approximately 6.0 1017 atoms/cm3. The region of maximum phosphorous concentration is located at approximately 0.1 pm or less below surface 35. The result is shown in Figure 3F where the photoresist mask has been removed after the second ion implantation step. However, the scattering oxide 37 is still retained to aid in finding the locations for electrical contacts provided in later steps.

The result of this ion implantation step is the formation of an n-type conductivity region 41 which forms or will form a portion of the pn junction or semiconductor junction which separates the remainder of the p-type conductivity region 38, region 38', from the other portions of silicon layer 30. Prior to annealing, the implanted region may not be deep enough to establish the junction defining the upper boundary of region 38' but rather the dopant in stratum 33 determines this boundary. This portion of the semiconductor junction is located between region 38' and surface 35 at approximately just greater than 0.1 pom below surface 35. Thus, the semiconductor junction due, or which will be due after annealing, to the formation of region 41 is a substantial distance from the maximum boron concentration location 39 in p-type conductivity region 38' so that small differences in the depth of this added pn junction have little effect on the electrical and temperature characteristics of p-type conductivity region 38'. And, of course, the variations in depth of the added pn junction will be relatively quite small because of the excellent control available in ion implantation process steps.

Also, the maximum dopant concentrations in each of the regions 41 and 38' are widely separated so that the pn junction therebetween has a satisfactory breakdown voltage. In aid of this goal, the phosphorous concentration in region 41 is kept as small as possible, i.e. substantially less than the maximum boron concentration, being just enough to reconvert the silicon layer at the surface of silicon layer 30 to n-type conductivity material and to assure that the depletion region in operation in region 41 does not reach surface 35.

Upon removing the photoresist implantation mask, the structure must go through an annealing cycle to repair silicon lattice damage due to the ion implantation steps. This annealing cycle performed at 9500C for approximately 10 minutes in dry nitrogen followed by substituting wet oxygen for the dry nitrogen for approximately 20 minutes, the use of wet oxygen resulting in the thermal growth of a silicon dioxide layer. This oxide layer is not allowed to form on the surface 35 immediately in the annealing cycle because heating of the lattice defects might be impeded thereby. Introducing the wet oxygen leads to growing approximately 2,000 A thick silicon dioxide layer 42 on surface 35 and over scattering oxide portion 37.

The annealing-oxidation cycle is done at the relatively low temperature of 950"C to minimize redistribution of the dopants in the implanted regions, region 41 and region 38', which alters the structure of these regions and so the structure of the stress sensor. This also prevents any substantial redistribution of the dopants between the n-type conductivity epitaxial layer 30 and the p±type conductivity substrate 31 which is desirable for achieving a sharp etching cutoff the diaphragm etching step yet to come. The result of these steps is shown in Figure 3G. The region of maximum boron concentration remains at about 0.7 to 0.9 pm while the region of maximum phosphorous concentration occurs near or at surface 35.

The semiconductor junction between regions 38' and 41 is now located at approximately 0.2 pm below surface 35.

A greater thickness of silicon dioxide is required, however, beyond the 2,000 A provided in the annealing-oxidation cycle.

Continuing to thermally grow such oxide, even at the relatively low temperature of the annealing-oxidation cycle, risk redistributing the dopants in the manner described to be avoided in the foregoing paragraph. Therefore, the added silicon dioxide is provided by pyrolytic deposition of silicon dioxide at 3000C until the total silicon dioxide thickness reaches approximately 5,000 A. For convenience, the entire resulting silicon dioxide layer from both steps is included in the silicon dioxide layer 42 shown in Figure 3G.

Next, electrical contact cuts are provided in silicon dioxide layer 42 by the use of conventional photoresist techniques to thereby provide access to the piezoresistors. The result is shown in Figure 3H. The cut or opening in silicon dioxide layer 42 is labeled 43 and provides access to p-type conductivity region 38'.

Ohmic electrical contacts are now provided for contacting the piezoresistors, that is in Figure 3H for contacting p-type conductivity regiun 38'. If a corrosive atmosphere is to be in contact with the stress sensor unit, a special metallization structure may be required to resist deterioration in such atmospheres, possibly using a combination of metals. Unless such extreme circumstances are to be encountered, a typical metallization process such as that conventionally used in providing the usual kinds of monolithic integrated circuits is satisfactory. In typical monolithic integrated circuits, aluminum is deposited to form the interconnection metallization network and satisfactory electrical contacts can be formed in the stress sensor by aluminum using wellknown aluminum metallization steps. The result of such steps is shown in Figure 31 where an electrical contact 44 is shown.

After the metal contacts are formed, the portion of silicon dioxide layer 42 not in the immediate area of the contacts can be removed by conventional photoresist techniques. Once this is done, the silicon dioxide layer has no material over the surface where applied stress is intended to be measured and so the silicon layer can respond without hindrance from such a silicon dioxide covering to provide a proper mechanical response to the applied stress.

However, if the mounting arrangement for the semiconductor material has substantial amount of hysteresis or other errors are predominant in the stress sensor structure, the relatively thin layer of silicon dioxide comprising layer 42 can be left in place since the errors and stress sensor response caused by this layer will be relatively unimportant. The structure with the unnecessary portions of layer 42 removed is shown in Figure 3J.

If a semiconductor material stress sensor is desired in the form of a wafer with the outer regions of the wafer mounted directly on a support, the thickness of substrate 31 is chosen accordingly.

Quite often, however, to minimize the effect of hysteresis in the bonding means mechanically connecting the semiconductor material stress sensor and its support together. Substrate 31 is made sufficiently thick so that a portion of it may be etched or machined away thereby leaving the epitaxial layer or the epitaxial layer and some portion of the substrate as the diaphragm portion and leaving the remaining portions of the substrate and the epitaxial layer adhering thereto as the constraint portions of the semiconductor material stress sensor.

In typically providing this latter structure by etching, the bottom of the substrate 31 is coated with a metal such as platinum, the resulting platinum layer having openings provided therein where etching of the substrate is to occur. Electrical contact is made to the platinum metal and the entire structure is then immersed in an electrolyte where a more or less conventional electrolytic etch is made. The resulting structure is shown in part in Figure 3K which matches Figure 3J except for the recess shown in substrate 31. This recess is labeled 45.

The support then for the entire semiconductor stress sensor is mechanically bonded to the remaining portions of substrate 31. The support should have a coefficient of thermal expansion closely matched to the expansion coefficient of substrate 31 and the bond should be as hysteresis free as possible. A silicon support and a gold eutectic bond might be used, for instance.

Another typical structure which is bonded to substrate 31 is a low thermal expansion glass tube which allows the tube to transmit a gas from some other point to the diaphragm portion of the semiconductor stress sensor tc measure the pressure of the gas by measuring the stress that the gas exerts on the diaphragm.

Another possibility for such a glass tube bonded to the stress sensor is to close the end of the glass tube opposite from the end bonded to the semiconductor stress sensor with the tube either being evacuated or containing a gas of a selected pressure therein. The semiconductor material stress sensor thus becomes a differential pressure sensor with respect to a reference pressure of zero psi (absolute pressure) or some other pressure. Electrostatic bonding is one known method for effecting a bond between the substrate 31 and a low thermal expansion glass.

The structure shown in Figures 2 and 3 indicates that an n-type conductivity epitaxial layer is to be provided on a p±type substrate with the piezoresistors formed also being of p-type conductivity material, although other conductivity arrangements may be employed so long as the piezoresistors and the surrounding semiconductor material have opposite conductivity types.

Figure 4 shows a plot of dopant concentration, C, versus depth below the silicon layer surface, X, for a sensor constructed in the manner described in connection with Figure 3.

Depth below surface 35 of Figure 3 is plotted on the horizontal axis in microns while the dopant concentration in atom/cm3 is plotted on the vertical axis. Curves for the concentration of the implanted p-type conductivity dopant are labeled Cp, the concentration of boron atoms. The remaining curves labeled Cn, are plotted for the implanted n-type conductivity dopant in Figure 3 which is phosphorous.

The concentrations after implanting are shown in dashed lines while the curves of the final structures in Figure 3, after the annealing step, are drawn in solid lines.

The substantial separation between the region of maximum dopant concentrations for both the n-type dopant and the p-type dopant in the final structure is evident from the peaks of the two curves. The intersection of the two solid line curves with one another approximately defines the final location of the pn junction and shows that the junction occurs where there is a relatively low concentration of p-type conductivity dopant. Thus, a small shift in that intersection from where it is shown in the plot of Figure 4 will have relatively little effect on the total number of dopant atoms in the p-type conductivity region and essentially no effect upon the maximum concentration value of the p-type dopant in the p-type conductivity region. Thus, total resistance value and piezoresistor temperature coefficient will not be much affected by a small shift in this intersection.

This substantial separation between the regions of maximum dopant concentrations for both types of dopants also yields a good junction breakdown voltage characteristic. The value achieved exceeds 10 volts.

WHAT WE CLAIM IS: 1. A semiconductor stress sensor comprising a diaphragm portion and a constraining portion for constraining the diaphragm portions at peripheral portions thereof, said diaphragm portion being provided by a layer of semiconductor material of a first conductivity type in which a first doped region of second conductivity type is formed to serve as a piezoresistor, said diaphragm portion having a second region located between said doped region and a first surface of the diaphragm portion with a semiconductor junction separating said regions, the maximum concentration of dopant in said first region being spaced from said junction.

2. The stress sensor of claim 1, wherein said semiconductor layer extends into the constraining portion and wherein ohmic contact is made to said first region at the constraining portion.

3. The stress sensor of claim 1 or 2, wherein said semiconductor layer is provided by two strata of different conductivity, the stratum witli higher conductivity having said first region formed therein.

4. The stress sensor of claim 2 or claim 3 as appendant to claim 2, wherein said first region intersects said first surface of said layer only in said constraining portion.

5. The stress sensor of any one of the preceding claims, wherein said semiconductor layer is formed on a semiconductor material substrate having a recess therein to provide said diaphragm portion.

6. The stress sensor of claim 5, wherein the substrate is bonded to a member having a low coefficient of thermal expansion.

7. The stress sensor of claim 2 or any one of claims 3 to 6 as appendant to claim 2, wherein at the constraining portion the first region extends through the second region to said diaphragm surface to enable said ohmic contact to be made.

8. A semiconductor stress sensor substantially as herein described with reference to the accompanying drawings.

9. A method of making a semiconductor stress sensor according to any one of the

Claims (1)

1. preceding claims.

   10. The method of claim 9 wherein the first region or first and second regions is formed by implanting ions.

   11. The method of claim 9 or 10 wherein the semiconductor layer is formed by epitaxial growth of two strata of one type of conductivity on a silicon substrate.

   12. The method of claim 10 wherein the first and second regions are implanted with boron and phosphorous ions respectively.

   13. The method of any one of claims 9 to 12, wherein the first region is formed by ion implantation with the aid of a first mask which in the location of the first region has a thickness less than that in the location around the first region so as to be suitable for scattering ions in said first region.

   14. The method of claim 13 as appendant to claim 2 wherein the second region is formed by ion implantation with the aid of a second mask, with photo resist thereon, said second mask being located where said ohmic contact is to be made.

   15. The method of any one of claims 9 to 14 as append ant to claim 5, wherein the substrate recess is formed by providing a metal etching mask on a base surface of the substrate and etching electrolytically the semiconductor layer by electrically contacting the metal mask and placing the layer as masked and contacted in an electrolyte bath.

   16. A method of making a semiconductor stress sensor, substantially as herein described with reference to the accompanying drawings.