GB1551290A - Ething of a layer supported on a substrate - Google Patents

Ething of a layer supported on a substrate

Info

Publication number
GB1551290A
GB1551290A GB4434076A GB4434076A GB1551290A GB 1551290 A GB1551290 A GB 1551290A GB 4434076 A GB4434076 A GB 4434076A GB 4434076 A GB4434076 A GB 4434076A GB 1551290 A GB1551290 A GB 1551290A
Authority
GB
United Kingdom
Prior art keywords
ething
substrate
layer supported
supported
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4434076A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE19772723933 priority Critical patent/DE2723933A1/en
Publication of GB1551290A publication Critical patent/GB1551290A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Weting (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
GB4434076A 1975-12-04 1976-11-24 Ething of a layer supported on a substrate Expired GB1551290A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19772723933 DE2723933A1 (en) 1975-12-04 1977-05-26 Etching metal, esp. polycrystalline silicon or aluminium - with definite angle of slope by ion bombardment before plasma etching

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19752554638 DE2554638A1 (en) 1975-12-04 1975-12-04 PROCESS FOR GENERATING DEFINED BOOT ANGLES FOR AN ETCHED EDGE

Publications (1)

Publication Number Publication Date
GB1551290A true GB1551290A (en) 1979-08-30

Family

ID=5963486

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4434076A Expired GB1551290A (en) 1975-12-04 1976-11-24 Ething of a layer supported on a substrate

Country Status (7)

Country Link
JP (1) JPS5269576A (en)
BE (1) BE849065A (en)
DE (1) DE2554638A1 (en)
FR (1) FR2334199A1 (en)
GB (1) GB1551290A (en)
IT (1) IT1065165B (en)
NL (1) NL7613275A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4999083A (en) * 1988-10-02 1991-03-12 Canon Kabushiki Kaisha Method of etching crystalline material with etchant injection inlet
WO2001015221A1 (en) * 1999-08-26 2001-03-01 Infineon Technologies North America Corp. Selective oxide etch for forming a protection layer with different oxide thicknesses
US6207517B1 (en) * 1998-08-18 2001-03-27 Siemens Aktiengesellschaft Method of fabricating a semiconductor insulation layer and a semiconductor component containing the semiconductor insulation layer
EP1691419A2 (en) * 2005-02-10 2006-08-16 NEC Electronics Corporation Field-effect transistor and method of manufacturing a field-effect transistor

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DD136670A1 (en) * 1976-02-04 1979-07-18 Rudolf Sacher METHOD AND DEVICE FOR PRODUCING SEMICONDUCTOR STRUCTURES
DE2754549A1 (en) * 1977-12-07 1979-06-13 Siemens Ag OPTOELECTRONIC SENSOR ACCORDING TO THE PRINCIPLE OF CHARGE INJECTION
DE2837485A1 (en) * 1978-08-28 1980-04-17 Siemens Ag METHOD FOR PRODUCING A CHARGED-COUPLED ARRANGEMENT FOR SENSORS AND STORAGE
JPS55157234A (en) * 1979-05-25 1980-12-06 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
JPS60128622A (en) * 1983-12-16 1985-07-09 Hitachi Ltd Etching method
GB2165692B (en) * 1984-08-25 1989-05-04 Ricoh Kk Manufacture of interconnection patterns
DE4140330C1 (en) * 1991-12-06 1993-03-18 Texas Instruments Deutschland Gmbh, 8050 Freising, De
JP2011243657A (en) * 2010-05-14 2011-12-01 Mitsumi Electric Co Ltd Semiconductor device manufacturing method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4999083A (en) * 1988-10-02 1991-03-12 Canon Kabushiki Kaisha Method of etching crystalline material with etchant injection inlet
US6207517B1 (en) * 1998-08-18 2001-03-27 Siemens Aktiengesellschaft Method of fabricating a semiconductor insulation layer and a semiconductor component containing the semiconductor insulation layer
US6365525B2 (en) 1998-08-18 2002-04-02 Siemens Aktiengesellschaft Method of fabricating a semiconductor insulation layer
WO2001015221A1 (en) * 1999-08-26 2001-03-01 Infineon Technologies North America Corp. Selective oxide etch for forming a protection layer with different oxide thicknesses
EP1691419A2 (en) * 2005-02-10 2006-08-16 NEC Electronics Corporation Field-effect transistor and method of manufacturing a field-effect transistor
EP1691419A3 (en) * 2005-02-10 2007-10-24 NEC Electronics Corporation Field-effect transistor and method of manufacturing a field-effect transistor

Also Published As

Publication number Publication date
FR2334199B1 (en) 1979-04-06
IT1065165B (en) 1985-02-25
JPS5269576A (en) 1977-06-09
BE849065A (en) 1977-04-01
NL7613275A (en) 1977-06-07
FR2334199A1 (en) 1977-07-01
DE2554638A1 (en) 1977-06-16

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee