GB1531126A - Frame pulse train synchronisation circuit arrangements - Google Patents

Abstract

1531126 Multiplexing; frame synchronization SIEMENS-ALBIS AG 14 July 1977 [6 Aug 1976] 29677/77 Heading H4M A frame synchronization arrangement for a receiver in a PCM system in which a frame synchronization word and a synchronizing check bit are alternately transmitted in the synchronizing time channel comprises a frame word extractor RWE which emits a frame word pulse rwi in response to each frame synchronizing word and a frame bit pulse rbi in response to each check bit, a resettable channel counter KLZ and a resetting circuit RSS which is responsive to the pulses rwi and rbi. The circuit RSS, Fig. 2 (not shown) comprises a word pulse counter (ZI) which is arranged to count consecutive break-downs of frame word pulses, a bistable stage (BS) which is responsive to the counter (ZI) reaching a first predetermined count to be set to a specific state in which it determines a second predetermined count of the counter for the frame-correct occurrence of frame word pulses, a gate (TS) which is responsive to the bistable stage being in said specific state to conduct any frame word pulse which occurs as a resetting pulse rsi to the channel counter KLZ, a counter (Z2) which counts frame word pulses which occur when the bistable stage is in said specific state and upon reaching a third predetermined count blocks the emission of further frame word pulses to the channel counter KLZ, and a bit pulse counter (Z3) which is arranged to count frame bit pulses which occur correctly following the occurrence of a frame word pulse which occurs while the bistable stage is in said specific state. The arrangement is such that if the bit pulse counter reaches a fourth predetermined count a frame word pulse counting input of the counter (Z1) is enabled after a delay of two pulse frames and if the fourth predetermined count is not reached the pulse counting input is blocked. Preferably the first predetermined count is equal to 3, whilst the second, third and fourth predetermined counts are each equal to 1, so that a resynchronizing process is initiated not until the frame synchronizing word has failed to appear three times consecutively, the frame alarm state denoting this loss of synchronization being maintained until both a synchronizing check bit and a synchronizing word have been detected in consecutive synchronizing time slots.