GB1516538A - Arrangement for testing a peripheral associated with a data processing - Google Patents

Arrangement for testing a peripheral associated with a data processing

Info

Publication number
GB1516538A
GB1516538A GB4233375A GB4233375A GB1516538A GB 1516538 A GB1516538 A GB 1516538A GB 4233375 A GB4233375 A GB 4233375A GB 4233375 A GB4233375 A GB 4233375A GB 1516538 A GB1516538 A GB 1516538A
Authority
GB
United Kingdom
Prior art keywords
control
fault
digital
test
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4233375A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CII HONEYWELL BULL
Original Assignee
CII HONEYWELL BULL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CII HONEYWELL BULL filed Critical CII HONEYWELL BULL
Publication of GB1516538A publication Critical patent/GB1516538A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2221Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/24Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Testing Electric Properties And Detecting Electric Faults (AREA)
  • Investigating Strength Of Materials By Application Of Mechanical Stress (AREA)

Abstract

1516538 Testing data processing peripheral units COMPAGNIE INTERNATIONALE POUR L'INFORMATION CII-HONEYWELL BULL 15 Oct 1975 [28 Oct 1974] 42333/75 Heading G1U [Also in Division G4] Faulty peripheral equipment of a data processing unit is tested under the control of a stored programme which provides excitation signals to the circuits in the peripheral equipment, digital and analogue signals at test points therein being converted to logic levels and fed via multi-plexing to an analyzing arrangement which identifies the fault. The peripheral P1 e.g. a disc store has circuitry TEST controlling its various functions e.g. analogue circuitry for disc rotation control, digital circuitry for read/write head control, position sensing and write/scan control, Fig. 7 (not shown). These circuits have associated test points e.g. PA 1 PA 2 (analogue) and PL 1 - PL 8 (digital). The data processor central unit P2 has stored therein a test programme operative when the peripheral malfunctions Figs. 6a, 6b (not shown). Programme signals are sent to a control circuit COM Fig. 4 (not shown) which in response triggers setting circuit INIT to reset stores M1, M2 to zero, and signal back to control COM. Multi-plexers MULT are then set to relay selected information from their inputs SPA1, SPA2 and SPL1-SPL8 to the central unit P2 which contains analysis unit EXAM. Control COM also supplies excitation signals STi to the circuit under test, these being equivalent to normal operating conditions. The digital signals (logic levels or pulses) at the digital test points PL1-PL8 pass via circuit TRANS which converts them to logic levels and feeds them to the multi-plexers MULT. The analogue test point signals are compared to reference levels in comparators El, E2, stored Ml, M2 and also fed to the multi-plexers. The selected information is passed to analysis unit EXAM which compares the results to a list TAB representing correct responses and fault responses. If a fault response is detected, a stored dictionary DIC is consulted, which provides an identification of the fault. If no fault is found, the stored programme progresses to monitor other test points or alter the input conditions.
GB4233375A 1974-10-28 1975-10-15 Arrangement for testing a peripheral associated with a data processing Expired GB1516538A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7436010A FR2289967A1 (en) 1974-10-28 1974-10-28 DEVICE FOR TEST AND DIAGNOSIS OF A PERIPHERAL DEVICE OF A DATA PROCESSING UNIT

Publications (1)

Publication Number Publication Date
GB1516538A true GB1516538A (en) 1978-07-05

Family

ID=9144494

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4233375A Expired GB1516538A (en) 1974-10-28 1975-10-15 Arrangement for testing a peripheral associated with a data processing

Country Status (3)

Country Link
DE (1) DE2548235A1 (en)
FR (1) FR2289967A1 (en)
GB (1) GB1516538A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2149539A (en) * 1983-11-10 1985-06-12 Gen Signal Corp Modular output driver for vital processor systems
CN107446931A (en) * 2017-05-16 2017-12-08 东北林业大学 Have the white birch SPL8 genes and its encoding proteins of multiple function
CN109324592A (en) * 2018-09-12 2019-02-12 四川宏华电气有限责任公司 A kind of drilling machine electric control product test macro

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4044244A (en) * 1976-08-06 1977-08-23 International Business Machines Corporation Automatic tester for complex semiconductor components including combinations of logic, memory and analog devices and processes of testing thereof
DE3022371A1 (en) * 1980-06-14 1981-12-24 Philips Patentverwaltung Gmbh, 2000 Hamburg DATA INPUT OR OUTPUT DEVICE WITH FUNCTIONAL CHECK

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3832535A (en) * 1972-10-25 1974-08-27 Instrumentation Engineering Digital word generating and receiving apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2149539A (en) * 1983-11-10 1985-06-12 Gen Signal Corp Modular output driver for vital processor systems
CN107446931A (en) * 2017-05-16 2017-12-08 东北林业大学 Have the white birch SPL8 genes and its encoding proteins of multiple function
CN109324592A (en) * 2018-09-12 2019-02-12 四川宏华电气有限责任公司 A kind of drilling machine electric control product test macro
CN109324592B (en) * 2018-09-12 2024-03-22 四川宏华电气有限责任公司 Drilling machine electric control product testing system

Also Published As

Publication number Publication date
DE2548235A1 (en) 1976-05-06
FR2289967B1 (en) 1977-10-28
FR2289967A1 (en) 1976-05-28

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee