GB1514762A - Solid-state fail-safe logic system - Google Patents

Abstract

1514762 Fail safe transistor logic circuits GENERAL SIGNAL CORP 15 May 1975 [30 May 1974] 20715/75 Heading H3T A fail-safe logic gate comprises a circuit connected between an A.C. input terminal 10 and a power supply terminal 16 and arranged to pass only the A.C. to the input side of an isolating coupler, e.g. D3, D4 or a Hall device and an active second circuit comprising the output side D4 of the coupler and input terminals 11, 12 for D.C. signals, whereby an A.C. output signal is available only in the presence of the A.C. and D.C. signals. The gate is suitable for replacement of relays having back and front contacts in a railway signalling system. In operation a capacitor charges via Dl and D2 on negative half cycles of the A.C. signal at 10, a transistor T1 being turned on during positive half cycles so as to discharge C1 via the LED D3 which thus irradiates the photo-diode D4 with pulses of light. The space between D3 and D4 may be filled with insulating material such as glass. If terminal 11 receives a D.C. signal positive relative to 12, pulses, corresponding to the pulses of light will be passed by C2 and amplifier T3, T4 to output terminal 15. Terminals 11 or 12 may be connected to the common line 17. In Fig. 1 c (not shown) T1 is replaced by a resistor so as to form a diode pump. In Fig. 2 (not shown) three sub-circuits 20 are connected to a single sub-circuit 25 to form an OR gate. Fig. 3A (not shown) illustrates a fail-safe circuit for producing the D.C. signal at A, B in response to the presence or absence of an A.C. signal at 32. It comprises a complementary pushpull transistor amplifier responsive to A.C. signals and feeding a series tuned circuit, a winding being coupled to the inductor feeding a bridge rectifier giving when the A.C. signal is present a negative D.C. signal of greater absolute value than the power supply and termed a "super-minus" signal. This signal is fed to a three-transistor switching circuit which provides a super-minus or positive output respectively in response to a super-minus or zero input. Figs. 4, 5 and 7 (not shown) depict block diagrams including the circuits shown in Fig. 1A and 3A for simulating back and front contacts of relays. Fig. 8 shows a circuit for monitoring the voltage applied to a load 60 from a D.C. source 71 controlled by a switching circuit 50 in response to a logic signal 55. An AND gate 20, 25 of the form shown in Fig. 1A is responsive to the A.C. logic signal 55 and to the D.C. voltage across load 60 and provides an A.C. logic signal at 15 only in response to correct operation of switching circuit 50. Driver 30 provides a super-minus output under these conditions. A further check on the D.C. power supply to load 60 is provided by a LED 86 irradiating a photo-transistor T10. In the absence of power in load 60, LED 86 is modulated by clock pulses at 85, but in the presence of voltage across load 60, LED 86 is reversed biased so that T10 provides no output. Fig. 9 (not shown) relates to three circuits of the type shown in Fig. 8 arranged to monitor three separate loads.