GB1512379A - Communications control unit for use in multiprocessor data processing systems - Google Patents

Abstract

1512379 Data processing PLESSEY CO Ltd 28 Oct 1975 [28 Oct 1974] 46570/74 Heading G4A Asynchronous data transfer between a plurality of input channels CH1-CH256 and a multi-processor data processing complex (e.g. for air traffic control) is via a communications control unit comprising the following integers: (1) a micro-program controlled input multiplexer IAL which assembles information supplied over individual channels into standard format words; (2) a pair of stores buffer A, B used alternately and on a mutually exclusive basis for input and output, each store having a plurality of locations for storing assembled standard format words together with the associated channel indentities; (3) respective output data handler OPL dedicated to each of the processors and controlled by its own exclusive microprogram unit OSEQ to asynchronously transmit all the information in one of the stores to the associated processor; and (4) a store control unit SAU which effects the input/output change-over of the buffer stores A, B and multiplexes demands ODEM to the stores from the microprogram units OSEQ of the data handlers OPL. Each channel has a byte assembler AR, Fig. 2 which includes an assembly shift register and an output buffer register. The byte assemblers are scanned by a channel counter CC, Fig. 4, in the control unit MIC of the input multiplexer, and detection of an assembler having an assembled byte in its output buffer register causes a pair of 1-bit pointers to be read from storage CBS which is addressed by the counter CC. The pointers indicate whether the assembled byte is the first, second or third byte of a word, first and second bytes being loaded into a respective scratch pad memory SPBYTE, Fig. 2, and a third byte being loaded into the current input buffer store A, B together with the previously assembled first and second bytes of the corresponding word and the associated channel address to complete a 4-byte word. This loading of a word into the input buffer take place after an input demand IDEM to the store control unit SAU has been granted, and is followed by incrementing a buffer address counter BAC. The store control unit SAU grants input/ output demands IDEM, ODEM in a priority order, IDEM having the highest priority. Change over of the buffer stores A, B between input and output functions is effected in response to the buffer address counter BAC indicating that the input buffer is full or the end of a regular time-out-interval, whichever comes first. When the change-over occurs, the address of the last used input buffer location is transferred to a last address register LAREG, Fig. 4 and then to a separate last address register for each of the output data handlers OPL, the latter also being notified of the change-over so that the associated processor can be informed that a new set of data is ready for transmission. Communication between an output data handler OPL and its processor is set up and maintained by an exchange of signals including an interrupt request. The associated last address register is decremented for each 4-byte word extracted from the output buffer store for transmission serial by byte over an 8-bit channel. Other bytes may be inserted to make up the word format of the receiving processor. For example the processor may have a 6-byte format, and the contents of a fault status register may be inserted as one of the bytes. Various bits of this register may be set as a result of an incorrect exchange of signals between the OPL and its processor and as a result of fault monitor time-out.