GB1501754A - Data-processing system - Google Patents

Abstract

1501754 Digital computers COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII-HONEYWELL BULL 31 Jan 1975 [1 Feb 1974] 4391/75 Heading G4A In a data processing system, an input and output controller controlling data transfers between a central unit (CPU) and at least one group of peripheral members, each group being connected to a respective peripheral controller connected to the central unit by a respective physical channel, controls operations by means of stored channel programmes and has a stored physical channels table with an entry for each physical channel for information relative to the physical channel, and at least one logical channels table, information relative to a peripheral member being gathered in a logical channel entry in such a logical channels table, execution of a channel programme instruction being via a logical channels table entry, the logical channel being then placed in a queue to await execution. As disclosed there is, for each of 6 physical channels, a logical channels table with 256 entries. Each channel programme (in main memory) has a 4-word header portion specifying where peripheral states may be memorized, a semaphore address, channel numbers (physical and logical) and priority (channel programmes can interrupt other channel programmes of lower priority). The rest of the channel programme is a series of 2-word channel entries, specifying a channel order (i.e. command), flags (relating to, e.g., data chaining, command chaining, interrupts), address information (e.g. main memory address for data transfer) and sometimes a count. Logical channels are queued to await execution (once selected by a channel programme) by chaining their logical channel entries together (in a given logical channels table, i.e. relating to a given physical channel), each entry giving the address and priority of the next. In general, at any given time, a plurality of channel programmes may be assigned logical channels associated with the same physical channel and may have progressed to different extents (some may not have started, i.e. may be still queuing): only one will be using the physical channel at any given time. The logical channel number is sent to the appropriate peripheral controller. Two pointers, advanced under control of the appropriate peripheral controller, are provided for each channel programme, to indicate the point reached &c. Interlocking tag signals are used on the physical channels. A peripheral controller can pass to another logical channel by specifying its number, or take the earliest in the queue of those of the highest priority present. Messages of notification of "emergencies" (e.g. channel exceptions, terminations) can be generated by the peripheral controllers (with interrupt of the channel programme) or input and output controller and stored in one of two zones of the logical channels table entry or a zone of the physical channels table entry, according to the type. The messages can be extracted from the tables by instructions, or simulated operations which attach the messages to one or other of a number of semaphores according to the type. A (single) queue of messages awaiting extraction is provided.