GB1498400A - Pulse code modulation systems - Google Patents

Abstract

1498400 Pulse code modulation POST OFFICE 13 Jan 1975 [19 Dec 1973] 58776/73 Heading G4A [Also in Divisions H3-H5] In order to permit a multi-way telephone conference, e.g. a three-way conference between subscribers X, Y, Z, 8-bit compressed pulse code modulated (PCM) words representative of signals from, say, subscribers Y and Z are directly added in a PCM word adder and the sum is sent as a PCM word to subscriber X. Each PCM word, e.g. Y, comprises a sign bit Y 0 , a set of 2-3 segment-identifying or exponent bits (referring to one of the 7 segments of the PCM companding curve-see Fig. 1 (not shown)-wherein 2 bits are used for segment 1 and 3 bits for segments 2-7), and a set of 4-5 magnitude or mantissa bits (5 bits for segment 1 and 4 bits for segments 2-7). The words Y, Z are fed into registers B, C respectively, the B register having stages B 0 , B 1 -B 2 , D B , E B and B 4 -B 8 , and the C register having corresponding stages. If a word Y in segment 1 is stored in register B, Y 0 is stored in B 0 , Y 1 and Y 2 in B 1 and B 2 , D B is set to 1, Y 3 is stored in E B and Y 4 -Y 7 in B 4 -B 7 , and B 8 is set to 1 (B 8 =1 leads to the mid-value between two signals being output, as required by the mid-riser PCM law). For a word Y in one of segments 2-7, the storage is similar except that Y 3 is stored in D B and E B is set to 1. These two alternatives are selected by decoding the first two segment-identifying bits Y 1 , Y 2 by means of a logic circuit 17 to detect the presence of a word Y in segment 1 (Y 1 Y 2 =00), the appropriate bits being gated to the B register via gates 26-31, a similar procedure being carried out for word Z by a logic circuit 18 and further gates (not shown). The segment-identifying bits of words Y, Z are fed to a logic circuit 19 which detects and passes the larger exponent to a logic circuit 20 so that the mantissas may be adjusted, signals being sent from logic circuit 19 to registers 21, 22, holding the magnitude bits of words Y, Z respectively, to shift that set of magnitude bits corresponding to the smaller exponent to the right by an amount equal to the difference of the exponents. The sum or difference of the shifted magnitude bits in registers 21, 22 is obtained by a logic circuit 23 which includes a binary full adder, the sum being calculated if the signs of Y, Z (given by Y 0 , Z 0 ) are the same (as determined by a logic circuit 15), and the difference otherwise. If the result of a subtraction of the magnitude bits in registers 21, 22 is negative, this is indicated in an overflow bit register 37 (also used in addition), the output of register 37 being fed to a logic circuit 16 to generate the sign of the result, the sign X 0 for output word X being stored in stage R 0 of an R register. A complementing logic circuit 24 then produces a positive number from the output of logic circuit 23. The positive output of logic circuit 24 is fed to a logic circuit 25, where the number stored therein is shifted either left or right until the most significant bit stored in F is "1". For left or right shifts, a number corresponding to the number of shifts is subtracted from or added to the larger exponent stored in logic circuit 20 (for right shifts, only 1 shift can occur, since the exponent of a sum can never exceed the larger exponent of the two numbers being added by more than 1). When R 1 R 2 =00, the shift procedure is stopped, possibly before the most significant bit is stored in F. The relationship of the output PCM word X to the stages of register R is then: stored in R 0 , R 1 , R 2 , F, R 4 -R 7 ; If R 1 R 2 #00, the relationship when shifting is complete is: X 0 X 1 X 2 X 3 ... X 7 stored in R 0 , R 1 , R 2 , G, R 4 -R 7 , (the least significant bit from logic circuit 25 is ignored in each case). The stage F is fed from the most significant bit position of logic circuit 25 and the stage G from logic circuit 20. The output PCM word X is then selected appropriately from register R by means of gates (not shown) according as R 1 R 2 =00 or not. The invention may be applied to a multiplexed telephone system wherein a conference facility may be set up for 3 or more subscribers by means of a conference unit incorporating at least one PCM word adder as described above, three different embodiments of such a conference unit being given in Figs. 6-8 (not shown).