GB1494347A - Ring crossing mechanism - Google Patents

Abstract

1494347 Data processing COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII-HONEYWELL BULL 28 Nov 1974 [30 Nov 1973 2 April 1974] 51656/74 Heading G4A In a multi-program computer system having a plurality of processes in a running, ready, wait or suspended state and comprising a memory, a CPU controlled by one of the processes, an operating system for creating and deleting processes and a communication centre linking the operating system and the processes, the latter comprises first means providing a partial address for a selected one of the processes (e.g. the head of ready queue) and second means addressed by the first means to provide an address for the selected process. The storage area of main store assigned to any process is called a process control block (400, Fig. 4, not shown) and contains the addresses of memory areas assigned to the process, contents of registers &c. It is addressed by the operating system using hardware tables (Fig. 5, not shown) non-current process control blocks being accessed using their job and process logic name. The active process control block is accessed using the contents of a base address register (501) to address system base (502) in main storage which gives a pointer to a J table (503). This pointer indexed by the job number gives a pointer to a P table (504) which in turn when indexed by the process number gives a process control block pointer from which the absolute address of a block may be derived. The system base also contains a G table word defining the segment and address of a G segment table (801, Fig. 9, not shown) which contains pointers to general memory segments. The first table entry GO points to the segment containing queues of processes ready (803c-803g) and processes waiting (803a-803b) which are manipulated by a dispatcher. A further queue (805a-805c) links processes not being used to extend the ready or wait queues. The head of the ready queue is indicated by an internal process queue word IPQW (905) in the system base, this representing the displacement of the head of the queue from the base of the GO segment. When a decoded micro instruction indicates that the word IPQW is to be fetched from the system base and the head of queue pointed to by it is to be transferred to scratch pad memory, the dispatcher fetches the GO segment descripter from the G table pointed to by the system base. If bits 16-31 of the word are zero the ready queue is empty. Otherwise if a process is currently running the dispatcher determines whether the process or the waiting process has the higher priority by searching the priority byte of the current process from the system base or process control block for comparison with the new process priority and if necessary the current process is rolled out (for storage of its data in its process control block) and placed in a ready queue and the new process is rolled in. When a switch system base instruction is received the address syllable (AS, Fig. 15a, not shown) of the switch base instruction is the address pointing to a new copy of the system base to be loaded into main memory and scratch pad memory and 60 byte zone starting at the address is transferred into the area of main storage assigned to the system base. This instruction executes for the highest privilege and input/output interrupts are locked out whilst it is occurring.