GB1493592A - Frequency shift keying data transmission systems - Google Patents

Abstract

1493592 Data transmission; FSK systems SERCK INDUSTRIES Ltd 21 Jan 1975 [25 Jan 1974 8 Nov 1974] 03502/74 and 48389/74 Heading H4P In an FSK system, marks are represented by a half cycle of one frequency and space by another, both of approximately sinusoidal waveform in which phase is continuous and slope of the waves is rectilinear at cross-over points, the time lengths of mark and space symbols being matched to half periods of respective keying frequencies. Areas embraced by mark and space half cycles may be equalized by reducing the amplitude of lower frequency half cycles which may be achieved by passing the signals to a gated attenuator which may be a potentiometer element switched by a transistor. D.C. restoration and/or clamping may be performed at receiver and/or transmitter positions. In one transmitter embodiment, Fig. 6, a generator 21 provides a rectangular waveform dependent on data input equal to a half period of corresponding frequency, this being passed through a digital filter 22 which converts it to a wave with continuous phase and constant slope at cross-overs which is passed to a driver unit 23. The generator 21 and filter 22 are described in greater detail in Figs. 7 and 9 (not shown) the latter including a clocked shift register arrangement having output resistors (R1-Rp) providing an ascending/decending linear staircase output through an amplifier (28) to a smoothing network. The receiver Fig. 11 may include a Gaussian low pass filter providing an input to a zero crossing detector 32 giving a square output corresponding to detected zero crossings, marks and spaces being detected by measuring time duration of the respective excursions. This may be achieved by counting the number of cycles of receiver clock pulses each duration and compared with a threshold number exactly midway between expected number of cycles in marks/spaces such that an excess above the threshold may be a space and deficiency a mark. A logical arrangement is described in connection with Fig. 13 (not shown). The zero crossing detector may be as given in Fig. 12 (not shown) and comprise a balanced differential input operational amplifier (35) with a negative feedback resistor (36) to limit the gain, with a resistor (Ro) providing initial setting, and to compensate for non zero triggering level of a following comparator (37). A CR network (38) forms a high pass filter and sends one input of comparator (37) is earthed, its output switches from a high to low level when input from the filter becomes positive hence the arrangement acts as a zero crossing detector and produces a half cycle per bit rectangular waveform. A feedback resistor (Rf) ensures that any slow rising input causes a sharp transition the output but is made large enough to prevent any significant hysteresis effect. In conditions of high noise level, a zero D.C. restoration circuit such as is given in Fig. 17 (also not shown) may be used having input peak detecting arrangements (117-119) for positive polarity and (120-122) for negative polarity, peak outputs from which are added algebraically by resistors (123, 124) and applied through an amplifier and further summing resistors (125, 126) to restore the D.C. level to a determined value. A simple form of clock pulse generator may comprise NAND gates (111-114) with feedback capacitor (115) and resistor (116) forming a CR circuit of appropriate time constant. Several other forms of transmitter and receiver are described in the Specification. The filter to convert from square to approximately sinusoidal waveform may be of the "Butterworth" type.